US12363997B2 - Semiconductor device - Google Patents

Semiconductor device

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Publication number
US12363997B2
US12363997B2 US17/972,945 US202217972945A US12363997B2 US 12363997 B2 US12363997 B2 US 12363997B2 US 202217972945 A US202217972945 A US 202217972945A US 12363997 B2 US12363997 B2 US 12363997B2
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layer
region
semiconductor substrate
igbt
fwd
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US20230037409A1 (en
Inventor
Masanori Miyata
Shuji Yoneda
Masaru Senoo
Yuki YAKUSHIGAWA
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Denso Corp
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Denso Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/137—Collector regions of BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/141—Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs
    • H10D62/142—Anode regions of thyristors or collector regions of gated bipolar-mode devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/422—PN diodes having the PN junctions in mesas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/60—Impurity distributions or concentrations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates

Definitions

  • the present disclosure relates to a semiconductor device in which an insulated gate bipolar transistor (hereinafter, referred to as IGBT) element having an insulated gate structure and a free wheel diode (hereinafter, referred to as FWD) element are formed on a common semiconductor substrate.
  • IGBT insulated gate bipolar transistor
  • FWD free wheel diode
  • a semiconductor device As a switching element used in inverters and the like, for example, a semiconductor device has been proposed in which an IGBT region having an IGBT element and an FWD region having an FWD element are formed on a common semiconductor substrate.
  • the present disclosure describes a semiconductor device having a semiconductor substrate including an IGBT region with an IGBT element and a FWD region with an FWD element.
  • the semiconductor device may have a first conductivity type drift layer, a second conductivity type base layer disposed on the drift layer, a second conductivity type collector layer disposed opposite to the base layer with respect to the drift layer in the IGBT region, and a first conductivity type cathode layer disposed opposite to the base layer with respect to the drift layer in the FWD region.
  • the collector layer may have an extension portion that covers only a part of the cathode layer on a side adjacent to the drift layer.
  • the collector layer may have an extension portion that entirely covers the cathode layer on a side adjacent to the drift layer, and has an area density of 3.5 ⁇ 10 12 cm ⁇ 2 or less.
  • FIG. 6 is a diagram showing a simulation result regarding a relationship between a length of the extension portion and an on voltage of the IGBT element and a forward voltage of a FWD element;
  • An N + -type emitter region may be formed in a surface layer portion of the base layer so as to be in contact with the trench.
  • a P + -type collector layer and an N + -type cathode layer may be formed adjacent to a second surface of the semiconductor substrate.
  • a P + -type shield layer may be formed entirely in a region between the drift layer and the collector layer and the cathode layer. In other words, a region of the cathode layer adjacent to the drift layer may be entirely covered with the shield layer.
  • an upper electrode may be formed adjacent to the first surface of the semiconductor substrate, and electrically connected to the emitter region and the base layer.
  • a lower electrode may be formed adjacent to the second surface of the semiconductor substrate, and electrically connected to the collector layer and the cathode layer.
  • a region where the collector layer is formed may serve as the IGBT region, and a region where the cathode layer is formed may serve as the FWD region.
  • an FWD element having a PN junction may be provided by the N-type cathode layer, the N-type drift layer, and the P-type base layer.
  • the FWD element since the region of the cathode layer adjacent to the drift layer is entirely covered with the shield layer, when the FWD element is turned on and operates as a diode, electrons supplied from the cathode layer may be difficult to flow toward the base layer because of the shield layer. That is, in the semiconductor device described above, the forward voltage of the FWD element may increase.
  • the present disclosure provides a semiconductor device capable of suppressing an increase in the forward voltage of the FWD element while suppressing snapback of the IGBT element.
  • the semiconductor device further includes: an emitter region of a first conductivity type disposed in a surface layer portion of the base layer in the IGBT region; a gate insulating film disposed in a portion of the base layer between the drift layer and the emitter region in the IGBT region; a gate electrode disposed on the gate insulating film; a first electrode disposed adjacent to the first surface of the semiconductor substrate and electrically connected to the base layer and the emitter region; and a second electrode disposed adjacent to the second surface of the semiconductor substrate and electrically connected to the collector layer and the cathode layer.
  • the collector layer includes an extension portion that covers only a part of a region of the cathode layer adjacent to the drift layer.
  • the extension portion is provided on the cathode layer adjacent to the drift layer, it is possible to suppress snapback when the IGBT element is turned on.
  • the extension portion is arranged so as to cover only a part of the cathode layer on the drift layer side. Therefore, when the FWD element is in an on state, movement of carriers (e.g., electrons) from the cathode layer to the base layer will not be hampered, and an increase in forward voltage of the FWD element can be suppressed.
  • a semiconductor device includes a semiconductor substrate having an insulated gate bipolar transistor (IGBT) region with an IGBT element and a free wheel diode (FWD) region with a FWD element.
  • the semiconductor substrate includes: a drift layer of a first conductivity type; a base layer of a second conductivity type disposed on the drift layer; a collector layer of the second conductivity type disposed opposite to the base layer with respect to the drift layer in the IGBT region; and a cathode layer of the first conductivity type disposed opposite to the base layer with respect to the drift layer in the FWD region.
  • the semiconductor substrate has a first surface adjacent to the base layer and a second surface adjacent to the collector layer and the cathode layer.
  • the semiconductor device further includes: an emitter region of a first conductivity type disposed in a surface layer portion of the base layer in the IGBT region; a gate insulating film disposed in a portion of the base layer between the drift layer and the emitter region in the IGBT region; a gate electrode disposed on the gate insulating film; a first electrode disposed adjacent to the first surface of the semiconductor substrate and electrically connected to the base layer and the emitter region; and a second electrode disposed adjacent to the second surface of the semiconductor substrate and electrically connected to the collector layer and the cathode layer.
  • the collector layer includes an extension portion that entirely covers a region of the cathode layer adjacent to the drift layer.
  • the extension portion has an area density of 3.5 ⁇ 10 12 cm ⁇ 2 or less.
  • the extension portion is provided on the cathode layer adjacent to the drift layer, it is possible to suppress snapback when the IGBT element is turned on.
  • the extension portion has the area density of 3.5 ⁇ 10 12 cm ⁇ 2 or less. Therefore, an increase in the forward voltage of the FWD element can be suppressed.
  • a semiconductor device of the present embodiment is used as a power switching element of a power supply circuit such as an inverter or a DC-to-DC converter.
  • the semiconductor device of the present embodiment has a reverse conducting (RC)-IGBT in which an IGBT region 1 a having an IGBT element and an FWD region 1 b having an FWD element are formed in the same semiconductor substrate 10 .
  • a collector layer 21 and a cathode layer 22 are disposed adjacent to a second surface 10 b of the semiconductor substrate 10 .
  • a region above the collector layer 21 serves as the IGBT region 1 a
  • a region above the cathode layer 22 serves as the FWD region 1 b.
  • the semiconductor device has the semiconductor substrate 10 forming an N ⁇ -type drift layer 11 .
  • the semiconductor substrate 10 is provided by a silicon substrate, and has a thickness of about 127 micrometres ( ⁇ m).
  • a base layer 12 is disposed on the drift layer 11 . In other words, the base layer 12 is disposed adjacent to a first surface 10 a of the semiconductor substrate 10 .
  • Each of the trenches 13 is filled with a gate insulating film 14 disposed so as to cover a wall surface of the trench 13 , and a gate electrode 15 disposed on the gate insulating film 14 .
  • the gate electrode 15 is made of polysilicon or the like. Accordingly, a trench gate structure is formed.
  • An N + -type emitter region 16 having a higher carrier concentration than the drift layer 11 is disposed in a surface layer portion of the base layer 12 in the IGBT region 1 a . That is, the emitter region 16 is disposed adjacent to the first surface 10 a of the semiconductor substrate 10 in the IGBT region 1 a .
  • a P + -type contact region 17 having a higher carrier concentration than the base layer 12 is disposed in the surface layer portion of the base layer 12 in the IGBT region 1 a .
  • the emitter region 16 is disposed so as to terminate in the base layer 12 and to be in contact with a side surface of the trench 13 .
  • the contact region 17 is disposed so as to terminate in the base layer 12 and is interposed between two emitter regions 16 .
  • the emitter regions 16 extend in a bar shape along the longitudinal direction of the trenches 13 so as to be in contact with the side surfaces of the trenches 13 in regions between adjacent two trenches 13 , and terminate at position more to inside than the ends of the trenches 13 .
  • the contact regions 17 extends in a bar shape along the longitudinal direction of the trenches 13 so as to be in contact with the emitter regions 16 .
  • An interlayer insulating film 18 is disposed on the first surface 10 a of the semiconductor substrate 10 .
  • the interlayer insulating film 18 is made of borophosphosilicate glass (BPSG) or the like.
  • the interlayer insulating film 18 is formed with a contact hole 18 a to expose the emitter regions 16 and the contact region 17 located between the adjacent trenches 13 on the first surface 10 a of the semiconductor substrate 10 in the IGBT region 1 a .
  • the interlayer insulating film 18 is formed with a contact hole 18 b to expose the base layer 12 and a contact hole 18 c to expose the gate electrode 15 on the first surface 10 a of the semiconductor substrate 10 in the FWD region 1 b.
  • the upper electrode 19 is disposed on the interlayer insulation film 18 .
  • the upper electrode 19 is electrically connected to the emitter regions 16 and the contact region 17 through the contact hole 18 a formed in the interlayer insulating film 18 .
  • the upper electrode 19 is electrically connected to the base layer 12 through the contact hole 18 b formed in the interlayer insulating film 18 .
  • the upper electrode 19 is also electrically connected to the gate electrode 15 through the contact hole 18 c formed in the interlayer insulating film 18 .
  • the upper electrode 19 is disposed on the interlayer insulating film 18 , and the upper electrode 19 functions as an emitter electrode in the IGBT region 1 a and functions as an anode electrode in the FWD region 1 b .
  • the upper electrode 19 corresponds to a first electrode.
  • the collector layer 21 is deeper than the cathode layer 22 with reference to the second surface 10 b of the semiconductor substrate 10 . That is, the depth of the collector layer 21 is greater than the depth of the cathode layer 22 , from the second surface 10 b of the semiconductor substrate 10 .
  • the collector layer 21 has an extension portion 21 a extending to a position above the cathode layer 22 . That is, the collector layer 21 has the extension portion 21 a covering a portion of the cathode layer 22 adjacent to the drift layer 11 .
  • the extension portion 21 a is formed not to cover an entire region above the cathode layer 22 , so that a part of a surface of the cathode layer 22 adjacent to the drift layer 11 is exposed from, that is, not covered with the extension portion 21 a , the part being opposite to the collector layer 21 in the planar direction.
  • the length of the extension portion 21 a along the arrangement direction of the collector layer 21 and the cathode layer 22 is defined as the length x of the extension portion 21 a.
  • connection region 23 is disposed between the part of the cathode layer 22 exposed from the extension portion 21 a and the FS layer 20 .
  • the connection region 23 has a lower carrier concentration than the cathode layer 22 and has the same carrier concentration as the drift layer 11 . More specifically, the connection region 23 is provided by a portion of the drift layer 11 .
  • the FS layer 20 , the collector layer 21 , the cathode layer 22 , and the connection region 23 as described above are formed, for example, as follows. That is, after ion-implanting impurities for forming the FS layer 20 , impurities for forming the collector layer 21 including the extension portion 21 a are ion-implanted. Thereafter, impurities for forming the cathode layer 22 are ion-implanted between the portion for forming the extension portion 21 a and the second surface 10 b of the semiconductor substrate 10 , and then a heat treatment is performed.
  • the carrier concentration thereof has a normal distribution, as shown in FIGS. 2 A and 2 B .
  • the connection region 23 of the present embodiment has a constant carrier concentration since the connection region 23 is provided by the portion of the drift layer 11 .
  • the collector layer 21 and the cathode layer 22 are disposed adjacent to each other.
  • the IGBT region 1 a and the FWD region 1 b are partitioned depending on whether the layer located on the second surface 10 b of the semiconductor substrate 10 is the collector layer 21 or the cathode layer 22 . That is, in the present embodiment, the region above the collector layer 21 , which is at the second surface 10 b of the semiconductor substrate 10 , serves as the IGBT region 1 a , and the region above the cathode layer 22 , which is at the second surface 10 b of the semiconductor substrate 10 , serves as the FWD region 1 b . In the present embodiment, therefore, it can be said that the extension portion 21 a is disposed in the FWD region 1 b.
  • a lower electrode 24 is disposed opposite to the drift layer 11 with respect to the collector layer 21 and the cathode layer 22 .
  • the lower electrode 24 is electrically connected to the collector layer 21 and the cathode layer 22 .
  • the lower electrode 24 is formed on the second surface 10 b of the semiconductor substrate 10 . That is, the lower electrode 24 that functions as a collector electrode in the IGBT region 1 a and a cathode electrode in the FWD region 1 b is provided.
  • the lower electrode 24 corresponds to a second electrode.
  • the semiconductor device of the present embodiment is configured as described above, and thus forms the IGBT element in the IGBT region 1 a .
  • the IGBT element includes a base provided by the base layer 12 , an emitter provided by the emitter region 16 and a collector provided by the collector layer 21 .
  • a PN-junction FWD element is formed in the FWD region 1 b .
  • the PN-junction FWD element includes an anode provided by the base layer 12 , and a cathode provided by the drift layer 11 , the FS layer 20 , the cathode layer 22 and the connection region 23
  • the configuration of the semiconductor device according to the present embodiment has been described above.
  • the N-type, the N + -type, and the N ⁇ -type correspond to a first conductivity type
  • the P-type and the P + -type correspond to a second conductivity type. Since the semiconductor device of the present embodiment is configured as described above, the semiconductor substrate 10 includes the collector layer 21 , the cathode layer 22 , the connection region 23 , the FS layer 20 , the drift layer 11 , the base layer 12 , the emitter regions 16 , and the contact region 17 .
  • the PN junction between the base layer 12 and the drift layer 11 is brought into a reverse conduction state to form a depletion layer.
  • the gate electrode 15 is applied with a low-level voltage (for example, 0 V) that is lower than a threshold voltage Vth of the insulated gate structure, a current does not flow between the upper electrode 19 and the lower electrode 24 .
  • a high-level voltage equal to or higher than the threshold voltage Vth of the insulated gate structure is applied to the gate electrode 15 of the IGBT region 1 a in a state where the lower electrode 24 is applied with the voltage higher than that of the upper electrode 19 .
  • an inversion layer is formed in a portion of the base layer 12 that is in contact with the trench 13 in which the gate electrode 15 is arranged.
  • the voltages to be applied to the upper electrode 19 and the lower electrode 24 are switched, and the upper electrode 19 is applied with the higher voltage than that applied to the lower electrode 24 , so a forward voltage application is performed.
  • the FWD element operates as a diode because holes are supplied to the base layer 12 and electrons are supplied to the cathode layer 22 .
  • the extension portion 21 a is disposed on the cathode layer 22 . Therefore, when the IGBT element is turned on, or when the IGBT element is in the on state, as shown in FIG. 3 , electrons reach the portion of the FS layer 20 located in the IGBT region 1 a , and then move toward the FWD region 1 b along the planar direction of the semiconductor substrate 10 . The electrons are then discharged from the cathode layer 22 . The holes supplied from the collector layer 21 to the drift layer 11 are supplied also from the extension portion 21 a to the drift layer 11 . Therefore, as shown in FIGS.
  • the holes can be supplied to the drift layer 11 also from the extension portion 21 a . Therefore, the hole concentration at the boundary between the region 1 a and the FWD region 1 b can be increased.
  • FIGS. 5 A and 5 B a solid line represents the simulation result of the configuration in which the extension portion 21 a is arranged so as to cover the entire region above the cathode layer 22 .
  • the extension portion 21 a is arranged not to cover the entire region above the cathode layer 22 as in the present embodiment, since the hole concentration at the boundary between the IGBT region 1 a and the FWD region 1 b can be increased, it is possible to suppress the occurrence of snapback.
  • FIG. 6 shows a simulation result of the configuration in which the width of the cathode layer 22 is 24 ⁇ m.
  • the extension portion 21 a is formed not to cover the entire region above the cathode layer 22 , and the part of the cathode layer 22 is exposed from the extension portion 21 a . That is, the length x of the extension portion 21 a is less than 24 ⁇ m. Therefore, as shown in FIG. 6 , it is possible to restrict the forward voltage of the FWD element from increasing.
  • FIG. 6 shows the simulation result when a current of 400 A is applied at 150° C.
  • Von represents the on-voltage
  • Vf represents the forward voltage.
  • the on-voltage decreases with an increase in the length x of the extension portion 21 a .
  • the cathode layer 22 is partly exposed from the extension portion 21 a and the length x of the extension portion 21 a is set according to the required on-voltage or the like.
  • the length x is 23 ⁇ m, it is possible to sufficiently reduce the on-voltage while suppressing an increase in the forward voltage. That is, when the ratio of the length x of the extension portion 21 a to the width of the cathode layer 22 is 23/24, it is possible to sufficiently reduce the on-voltage while suppressing the increase in the forward voltage.
  • FIG. 8 in a case where the carrier concentration of the collector layer 21 is fixed at 1.0 ⁇ 10 18 cm ⁇ 3 , it is confirmed that the forward voltage of the FWD element sharply increases when the depth d of the collector layer 21 is 0.5 ⁇ m or more.
  • FIG. 9 in a case where the depth d of the collector layer 21 is fixed at 0.5 ⁇ m, it is confirmed that the forward voltage of the FWD element sharply increases when the carrier concentration of the collector layer 21 is 1.0 ⁇ 10 17 cm ⁇ 3 or more.
  • FIGS. 8 and 9 are simulation results when the carrier concentration is constant along the depth direction.
  • the basic configuration of the semiconductor device of the present embodiment is the same as that of the first embodiment, but the collector layer 21 is configured to have multiple peaks in the carrier concentration, as shown in FIG. 11 .
  • the collector layer 21 is disposed such that the maximum peak position P 1 at which the carrier concentration is maximum is positioned closer to the drift layer 11 (that is, closer to the FS layer 20 ) than the center C 1 of the collector layer 21 in the depth direction of the semiconductor substrate 10 .
  • Such a collector layer 21 is formed by, for example, performing ion-implantations multiple times with different acceleration voltages.
  • the maximum peak position P 1 of the collector layer 21 is located closer to the drift layer 11 than the center C 1 . Therefore, an occurrence of avalanche breakdown can be suppressed, and the short circuit safe operating area (SCSOA) can be improved.
  • SCSOA short circuit safe operating area
  • the maximum peak position P 1 of the carrier concentration of the collector layer 21 is set to be adjacent to the drift layer 11 .
  • the amount of holes injected into a position at which the electric field intensity has the peak is easily increased during the short circuit, and the electron excessive state can be alleviated. Therefore, it is possible to suppress the occurrence of avalanche breakdown.

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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JP2024080317A (ja) * 2022-12-02 2024-06-13 株式会社デンソー 半導体装置とその製造方法
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US20250301773A1 (en) 2025-09-25
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