US10971510B2 - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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US10971510B2
US10971510B2 US16/295,762 US201916295762A US10971510B2 US 10971510 B2 US10971510 B2 US 10971510B2 US 201916295762 A US201916295762 A US 201916295762A US 10971510 B2 US10971510 B2 US 10971510B2
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signal line
memory cell
wiring layer
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US20200098767A1 (en
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Tetsu Morooka
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Kioxia Corp
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Toshiba Memory Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H01L27/1157—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • H01L27/11524—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H01L27/11551—
    • H01L27/11578—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels

Definitions

  • the embodiments of the present invention relate generally to a semiconductor memory device.
  • a NAND flash memory is known as a kind of semiconductor memory device.
  • a NAND flash memory comprising three-dimensionally stacked memory cell transistors is also known.
  • FIG. 1 is a block diagram illustrating a semiconductor memory device according to an embodiment
  • FIG. 2 is a circuit diagram of one block BLK included in a memory cell array
  • FIG. 3 is a sectional view of a memory cell array
  • FIG. 4 is a plan view illustrating how the memory cell array is at position P 1 shown in FIG. 3 ;
  • FIG. 5 is a plan view illustrating how the memory cell array is at position P 2 shown in FIG. 3 ;
  • FIG. 6 is a plan view of the wiring layer 24 shown in FIG. 4 ;
  • FIG. 7 is a view illustrating an example of the connection relationship between a semiconductor film and a bit line
  • FIG. 8 is a sectional view illustrating a method of manufacturing a memory cell array
  • FIG. 9 is a plan view illustrating the method of manufacturing the memory cell array and shows a state after FIG. 8 ;
  • FIG. 10 is a sectional view illustrating the method of manufacturing the memory cell array and shows a state after FIG. 8 ;
  • FIG. 11 is a view illustrating the method of manufacturing the memory cell array and shows a state after FIG. 10 ;
  • FIG. 12 is a view illustrating the method of manufacturing the memory cell array and shows a state after FIG. 11 ;
  • FIG. 13 is a view illustrating the method of manufacturing the memory cell array and shows a state after FIG. 12 ;
  • FIG. 14 is a view illustrating the method of manufacturing the memory cell array and shows a state after FIG. 13 ;
  • FIG. 15 is a view illustrating the method of manufacturing the memory cell array and shows a state after FIG. 14 ;
  • FIG. 16 is a view illustrating the method of manufacturing the memory cell array and shows a state after FIG. 15 ;
  • FIG. 17 is a view illustrating the method of manufacturing the memory cell array and shows a state after FIG. 16 ;
  • FIG. 18 is a view illustrating the method of manufacturing the memory cell array and shows a state after FIG. 17 ;
  • FIG. 19 is a view illustrating the method of manufacturing the memory cell array and shows a state after FIG. 18 ;
  • FIG. 20 is a view illustrating the method of manufacturing the memory cell array and shows a state after FIG. 19 ;
  • FIG. 21 is a view illustrating the method of manufacturing the memory cell array and shows a state after FIG. 20 ;
  • FIG. 22 is a view illustrating the method of manufacturing the memory cell array and shows a state after FIG. 21 ;
  • FIG. 23 is a view illustrating the method of manufacturing the memory cell array and shows a state after FIG. 22 ;
  • FIG. 24 is a view illustrating the method of manufacturing the memory cell array and shows a state after FIG. 23 ;
  • FIG. 25 is a view illustrating the method of manufacturing the memory cell array and shows a state after FIG. 24 ;
  • FIG. 26 is a view illustrating the method of manufacturing the memory cell array and shows a state after FIG. 25 ;
  • FIG. 27 is a sectional view illustrating the method of manufacturing the memory cell array and shows a state after FIG. 26 ;
  • FIG. 28 is a plan view of a memory cell array according to another embodiment.
  • FIG. 29 is a plan view illustrating an opening of the memory cell array according to still another embodiment.
  • a semiconductor memory device comprising:
  • each of the wiring layers including a first face recessed in a first direction parallel to a surface of the substrate, a second face recessed in a second direction parallel to the surface of the substrate and different from the first direction, a third face recessed in a third direction parallel to the surface of the substrate and different from the first and second directions, and a fourth face recessed in a fourth direction parallel to the surface of the substrate and different from the first to third directions;
  • FIG. 1 is a block diagram illustrating the semiconductor memory device 1 according to the embodiment.
  • the semiconductor memory device 1 comprises a memory cell array 10 , a row decoder 11 , a column decoder 12 , a sense amplifier 13 , an input/output circuit 14 , a command register 15 , an address register 16 , a sequencer (control circuit) 17 , etc.
  • the memory cell array 10 includes j blocks BLK 0 to BLK(j ⁇ 1) integer not less than 1. Each of the blocks is provided with a plurality of memory cell transistors.
  • the memory cell transistors are made of electrically rewritable memory cells.
  • a plurality of bit lines, a plurality of word lines and a source line are arranged in the memory cell array 10 so as to control the voltages applied to the respective memory cell transistors.
  • a specific configuration of blocks BLK will be described later.
  • the row decoder 11 receives a row address from the address register 16 and decodes this row address.
  • the row decoder 11 performs a selection operation of, for example, word lines, based on the decoded row address.
  • the row decoder 11 transfers the voltages required for the write operation, read operation and erase operation to the memory cell array 10 .
  • the column decoder 12 receives a column address from the address register 16 and decodes this column address.
  • the column decoder 12 performs a selection operation of bit lines, based on the decoded column address.
  • the sense amplifier 13 senses and amplifies data that is read from a memory cell transistor to a bit line. In a write operation, the sense amplifier 13 transfers write data to a bit line.
  • the input/output circuit 14 is connected to an external device (host device) via a plurality of input/output lines (DQ lines).
  • the input/output circuit 14 receives command CMD and address ADD from the external device.
  • the command CMD received by the input/output circuit 14 is sent to the command register 15 .
  • the address ADD received by the input/output circuit 14 is sent to the address register 16 . Further, the input/output circuit 14 exchanges data DAT with reference to the external device.
  • the sequencer 17 receives control signals CNT from the external device.
  • the control signals CNT include a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, and the like.
  • the “n” suffixed to the signal names indicates an active row.
  • the sequencer 17 controls the operation of the entire semiconductor memory device 1 based on the command CMD stored in the command register 15 and control signal CNT.
  • FIG. 2 is a circuit diagram of one block BLK included in the memory cell array 10 .
  • Each of the blocks BLK is provided with a plurality of string units SU.
  • four string units SU 0 to SU 3 are shown by way of example.
  • the number of string units SU included in one block BLK can be optionally determined.
  • Each of the string units SU includes a plurality of NAND strings (memory strings) NS.
  • the number of NAND strings NS included in one string unit SU can be optionally determined.
  • Each of the NAND strings NS includes a plurality of memory cell transistors MT and two select transistors ST 1 and ST 2 .
  • the memory cell transistors MT are connected in series between the source of select transistor ST 1 and the drain of select transistor ST 2 .
  • the memory cell transistors may be referred to as memory cells or cells.
  • FIG. 2 shows a configuration example in which NAND string NS is provided with eight memory cell transistors MT (MT 0 to MT 7 ), but the number of memory cell transistors MT provided in NAND string NS is larger in practice and can be optionally determined.
  • Each of the memory cell transistors MT includes a control gate and a charge storage layer, and holds data in a nonvolatile manner. Each memory cell transistor MT can hold data of one bit or data of two or more bits.
  • select transistors ST 1 of string unit SU 0 are commonly connected to select gate line SGD 0 .
  • the gates of select transistors ST 1 of string units SU 1 to SU 3 are connected to select gate lines SGD 1 to SGD 3 , respectively.
  • the gates of select transistors ST 2 of string unit SU 0 are commonly connected to select gate line SGS 0 .
  • the gates of select transistors ST 2 of string units SU 1 to SU 3 are connected to select gate lines SGS 1 to SGS 3 , respectively.
  • a common select gate line SGS may be connected to string units SU 0 to SU 3 included in each block BLK.
  • the control gates of memory cell transistors MT 0 to MT 7 included in each block BLK are connected to word lines WL 0 to WL 7 , respectively.
  • each bit line BL is commonly connected to a plurality of blocks BLK, and is connected to one NAND string NS in each string unit SU included in each of the blocks BLK.
  • the sources of select transistors ST 2 included in each block BLK are commonly connected to a source line SL.
  • Source line SL is commonly connected to a plurality of blocks BLK, for example.
  • the data in a plurality of memory cell transistors MT included in each block BLK can be erased in a collective manner, for example. Read and write operations are collectively performed for a plurality of memory cell transistors MT that are commonly connected to one word line WL of one string unit SU. A set of memory cell transistors MT that share the same word line in each string unit are referred to as a cell unit CU.
  • the 1-bit data stored in a plurality of memory cell transistors MT included in cell unit CU is referred to as a page. In other words, the write operation and the read operation for cell unit CU are performed in, units of pages.
  • the NAND strings NS may be provided with dummy cell transistors.
  • two dummy cell transistors are connected in series between select transistor ST 2 and memory cell transistor MT 0 .
  • two dummy cell transistors are connected in series between memory cell transistor MT 7 and select transistor ST 1 .
  • a plurality of dummy word lines are connected to the gates of the dummy cell transistors, respectively.
  • the configurations of the dummy cell transistors are similar to those of the memory cell transistors.
  • the dummy cell transistors are not for storing data and have a function of relieving the disturbance which the memory cell transistors and select transistors may undergo during the write operation and erase operation.
  • FIG. 3 is a sectional view of the memory cell array 10 .
  • FIG. 4 is a plan view illustrating how the memory cell array 10 is at position P 1 shown in FIG. 3 .
  • FIG. 5 is a plan view illustrating how the memory cell array 10 is at position P 2 shown in FIG. 3 .
  • the sectional view shown in FIG. 3 corresponds to the view taken along line A-A′ of FIGS. 4 and 5 .
  • the X direction and the Y direction are defined as being perpendicular to each other in a horizontal plane, and the Z direction is defined as the stacking direction.
  • a substrate for example, a silicon substrate
  • an insulating layer 21 formed of, for example, silicon oxide (SiO 2 ) and a conductive layer 22 formed of, for example, polycrystalline silicon are stacked in this order.
  • the conductive layer 22 functions as a source line SL.
  • the source line SL is formed such that it spreads over the XY plane.
  • the source line SL may be formed of a laminated film in which a conductive layer formed of polycrystalline silicon, a metal layer formed, for example, of tungsten (W) and a conductive layer formed of polycrystalline silicon are stacked in this order.
  • a single wiring layer 24 functioning as select gate lines SGS, a plurality of wiring layers 24 functioning as word lines WL, and a single wiring layer functioning as select gate lines SGD are stacked in this order, with respective interlayer insulating layers 23 interposed.
  • the interlayer insulating layers 23 are formed of silicon oxide, for example.
  • the wiring layers 24 are formed of tungsten (W), for example.
  • Each wiring layer 24 may be provided with a barrier metal film (for example, titanium nitride (TiN)) covering the upper face, side faces, and bottom face of the main body portion of tungsten (W).
  • TiN titanium nitride
  • Select gate lines SGS are not limited to those formed by one layer, and may be formed by three wiring layers 24 , for example.
  • Select gate lines SGD are not limited to those formed by one layer, and may be formed by three wiring layers 24 , for example.
  • each of the wiring layers 24 is provided with a cross-shaped opening (memory hole) AH 1 . That is, the wiring layer 24 has first to fourth faces (curved faces) SF 1 to SF 4 .
  • first to fourth faces (curved faces) SF 1 to SF 4 In FIG. 4 , four directions are defined such that the direction toward the right side of the X axis is +X direction, the direction toward the left side of the X axis is ⁇ X direction, the direction toward the upper side of the Y axis is +Y direction, and the direction toward the lower side is ⁇ Y direction.
  • the first face SF 1 is a curved face depressed in the +X direction.
  • the second face SF 2 is a curved face depressed in the ⁇ Y direction.
  • the third face SF 3 is a curved face depressed in the ⁇ X direction.
  • the fourth face SF 4 is a curved face depressed in the +Y direction.
  • FIG. 6 is a plan view of the wiring layer 24 shown in FIG. 4 .
  • the first face SF 1 and the third face SF 3 are opposed to each other in the X direction.
  • the second face SF 2 and the fourth face SF 4 are opposed to each other in the Y direction.
  • the fourth face SF 4 is located between the first face SF 1 and the third face SF 3 , as viewed in the X direction, and is different in position from the first face SF 1 and the third face SF 3 , as viewed in the +Y direction.
  • the second face SF 2 is located between the first face SF 1 and the third face SF 3 , as viewed in the X direction, and is different in position from the first face SF 1 and the third face SF 3 , as viewed in the ⁇ Y direction.
  • a fifth face SF 5 is located between the first face SF 1 and the fourth face SF 4 .
  • the fifth face SF 5 is continuous with the first face SF 1 and the fourth face SF 4 and is located in a direction between the +X direction and the +Y direction.
  • a sixth face SF 6 is located between the second face SF 2 and the third face SF 3 .
  • the sixth face SF 6 is continuous with the second face SF 2 and the third face SF 3 and is located in a direction between the ⁇ X direction and the ⁇ Y direction.
  • a seventh face SF 7 is located between the first face SF 1 and the second face SF 2 .
  • the seventh face SF 7 is continuous with the first face SF 1 and the second face SF 2 and is located in a direction between the +X direction and the ⁇ Y direction.
  • An eighth face SF 8 is located between the third face SF 3 and the fourth face SF 4 .
  • the eighth face SF 8 is continuous with the third face SF 3 and the fourth face SF 4 and is located in a direction between the ⁇ X direction and the +Y direction.
  • the first face SF 1 to the eighth face SF 8 are provided such that they pass through the same plane. Also, the first face SF 1 to the eighth face SF 8 are in the same layer.
  • the curvature changes from the first face SF 1 toward the fifth face SF 5 . Further, the curvature changes from the fifth face SF 5 toward the fourth face SF 4 .
  • the first face SF 1 , the fourth face SF 4 and the fifth face SF 5 include a portion in which the curvature increases from the first face SF 1 toward the fifth face SF 5 and a portion in which the curvature decreases from the fifth face SF 5 toward the fourth face SF 4 .
  • the curvature is an amount representing a degree of curvature of a curve. F example, the curvature of a circumference of radius r is 1/r, and the radius of curvature is r. An increase in the curvature means that the radius of curvature decreases, and a decrease in the curvature means that the radius of curvature increases.
  • the curvature changes from the second face SF 2 toward the sixth face SF 6 . Further, the curvature changes from the sixth face SF 6 toward the third face SF 3 .
  • the second face SF 2 , the sixth face SF 6 and the third face SF 3 include a portion in which the curvature increases from the second face SF 2 toward the sixth face SF 6 and a portion in which the curvature decreases from the sixth face SF 6 toward the third face SF 3 .
  • the curvature changes from the first face SF 1 toward the seventh face SF 7 . Further, the curvature changes from the seventh face SF 7 toward the second face SF 2 .
  • the first face SF 1 , the seventh face SF 7 and the second face SF 2 include a portion in which the curvature increases from the first face SF 1 toward the seventh face SF 7 and a portion in which the curvature decreases from the seventh face SF 7 toward the second face SF 2 .
  • the curvature changes from the third face SF 3 toward the eighth face SF 8 . Further, the curvature changes from the eighth face SF 8 toward the fourth face SF 4 .
  • the third face SF 3 , the eighth face SF 8 and the fourth face SF 4 include a portion in which the curvature increases from the third face SF 3 toward the eighth face SF 8 and a portion in which the curvature decreases from the eighth face SF 8 toward the fourth face SF 4 .
  • the distance D 1 between the first face SF 1 and the third face SF 3 is larger than the distance D 2 between the fifth face SF 5 and the sixth face SF 6 and the distance between the seventh face SF 7 and the eighth face SF 8 .
  • the distance between the second face SF 2 and the fourth face SF 4 is larger than the distance D 2 between the fifth face SF 5 and the sixth face SF 6 and the distance between the seventh face SF 7 and the eighth face SF 8 .
  • the first face SF 1 is opposed to a first signal line 29 - 1 .
  • the second face SF 2 is opposed to a second signal line 29 - 2 .
  • the third face SF 3 is opposed to a third signal line 29 - 3 .
  • the fourth face SF 4 is opposed to a fourth signal line 29 - 4 .
  • the first to fourth signal lines will be described later.
  • the first face SF 1 includes a first portion having a concave curvature.
  • the second face SF 2 includes a second portion having a concave curvature.
  • the third face SF 3 includes a third portion having a concave curvature.
  • the fourth face SF 4 includes a fourth portion having a concave curvature.
  • the fifth face SF 5 includes a fifth portion having a convex curvature.
  • the sixth face SF 6 includes a sixth portion having a convex curvature.
  • the seventh face SF 7 includes a seventh portion having a convex curvature.
  • the eighth face SF 8 includes an eighth portion having a convex curvature.
  • the wiring layer 24 includes a first point SF 1 , a third point SF 3 opposed to the first point SF 1 in the X direction, a second point SF 2 located between the first point SF 1 and the third point SF 3 in the X direction and being different in position from them, as viewed in the ⁇ Y direction, and a fourth point SF 4 opposed to the second point SF 2 in the +Y direction.
  • the wiring layer 24 includes on the surface thereof: a seventh point SF 7 toward which the distance to the circle increases between the first point SF 1 and the second point SF 2 and which is located inside the circle; a sixth point SF 6 toward which the distance to the circle increase between the second paint SF 2 and the third point SF 3 and which is located inside the circle; an eighth point SF 8 toward which the distance to the circle increases between the third point SF 3 and the fourth point SF 4 and which is located inside the circle; and a fifth point SF 5 toward which the distance to the circuit increases between the fourth point SF 4 and the first point SF 1 and which is located inside the circle.
  • the distance to the circle is maximal at the midpoint between the first point SF 1 and the second point.
  • SF 2 (namely, at the seventh point SF 7 ), at the midpoint between the second point SF 2 and the third point SF 3 (namely, at the sixth point SF 6 ), at the midpoint between the third point and the fourth point SF 4 (namely, at the eighth point SF 8 ) and at the midpoint between the fourth point SF 4 and the first point SF 1 (namely, at the fifth point SF 5 ).
  • Four memory cell transistors MTa, MTb, MTc, and MTd are provided in the opening AH 1 of the wiring layer 24 .
  • Memory cell transistor MTa includes a block insulating film 25 - 1 , a charge storage film (charge trap film) 26 - 1 , a floating gate electrode 27 - 1 , a tunnel insulating film 28 - 1 , a semiconductor film (channel film) 29 - 1 , and a cover film 30 - 1 .
  • the block insulating film 25 - 1 is provided on b the first face SF 1 of the wiring layer 24 .
  • the charge storage film 26 - 1 is provided on a side face of the block insulating film 25 - 1 .
  • the floating gate electrode 27 - 1 is provided on a side face of the charge storage film 26 - 1 .
  • the tunnel insulating film 28 - 1 is provided on a side face of the floating gate electrode 27 - 1 .
  • the semiconductor film 29 - 1 is provided on a side face of the tunnel insulating film 28 - 1 .
  • the cover film 30 - 1 is provided on a side face of the semiconductor film 29 - 1 .
  • the semiconductor film 29 is also referred to as a signal line.
  • the charge storage film 26 - 1 and the floating gate electrode 27 - 1 each have a function of storing electric charge.
  • the charge storage film 26 - 1 and the floating gate electrode 27 - 1 may be collectively referred to as a charge storage film.
  • the semiconductor film 29 - 1 is a region where the channel of memory cell transistor MTa is formed.
  • the cover film 30 - 1 is a member required in the manufacturing process to be described later.
  • the block insulating film 25 - 1 is formed of silicon oxide, for example.
  • the charge storage film 26 - 1 is an insulating film formed of, for example, silicon nitride (SiN) or a metal oxide (e.g., hafnium oxide).
  • the floating gate electrode 27 - 1 is formed of polycrystalline silicon, for example.
  • the tunnel insulating film 28 - 1 is formed of silicon oxide, for example.
  • the semiconductor film 29 - 1 is formed of polycrystalline silicon, for example.
  • the cover film 30 - 1 is formed of, for example, silicon nitride (SiN) or silicon oxide.
  • Memory cell transistor MTb is provided on the second face SF 2 of the wiring layer 24 and includes a block insulating film 25 - 2 , a charge storage film 26 - 2 , a floating gate electrode 27 - 2 , a tunnel insulating film 28 - 2 , a semiconductor film 29 - 2 , and a cover film 30 - 2 .
  • Memory cell transistor MTc is provided on the third face SF 3 of the wiring layer 24 and includes a block insulating film 25 - 3 , a charge storage film 26 - 3 , a floating gate electrode 27 - 3 , a tunnel insulating film 28 - 3 , a semiconductor film 29 - 3 , and a cover film 30 - 3 .
  • Memory cell transistor MTd is provided on the fourth face SF 4 of the wiring layer 24 and includes a block insulating film 25 - 4 , a charge storage film 26 - 4 , a floating gate electrode 27 - 4 , a tunnel insulating film 28 - 4 , a semiconductor film 29 - 4 , and a cover film 30 - 4 .
  • the configurations of memory cell transistors MTb to MTd are similar to the configuration of memory cell transistor MTa.
  • the configurations of select transistors ST 1 and ST 2 are similar to the configuration of memory cell transistor MTa.
  • the block insulating films 25 - 1 to 25 - 4 are formed, for example, of a film that is continuous in an XY plane.
  • the charge storage film 26 and the floating gate electrode 27 are provided for each memory cell transistor. MT. That is, the charge storage film 26 and the floating gate electrode 27 are separated in the Z direction, for each memory cell transistor MT.
  • the tunnel insulating film 28 extends in the Z direction and is provided in common to the NAND string NS.
  • the semiconductor film 29 extends in the Z direction and is provided in common to the NAND string NS.
  • the cover film 30 extends in the Z direction and is provided in common to the NAND string NS.
  • each of the interlayer insulating layers 23 is provided with a cross-shaped opening AH 2 .
  • the size of opening AH 2 is smaller than that of opening AH 1 .
  • Tunnel insulating film 28 - 1 is provided in the concave portion recessed in the +X direction of the interlayer insulating layer 23 .
  • Semiconductor film 29 - 1 is provided on the side face of tunnel insulating film 28 - 1 .
  • Cover film 30 - 1 is provided on the side face of semiconductor film 29 - 1 .
  • Tunnel insulating film 28 - 2 is provided in the concave portion recessed in the ⁇ Y direction of the interlayer insulating layer 23 .
  • Semiconductor film 29 - 2 is provided on the side face of tunnel insulating film 8 - 2 .
  • Cover film 3 - 2 provided on the side face of semiconductor film 29 - 2 .
  • Tunnel insulating film 28 - 3 is provided in the concave portion recessed in the ⁇ X direction of the interlayer insulating layer 23 .
  • Semiconductor film 29 - 3 is provided on the side face of tunnel insulating film 28 - 3 .
  • Cover film 30 - 3 is provided on the side face of semiconductor film 3 .
  • Tunnel insulating film 28 - 4 is provided in the concave portion recessed in the +Y direction of the interlayer insulating layer 23 .
  • Semiconductor film 29 - 4 is provided on the side face of tunnel insulating film 28 - 4 .
  • Cover film 30 - 4 is provided on the side face of semiconductor film 29 - 4 .
  • the semiconductor films 29 - 1 to 29 - 4 are connected together at their lower end portions, and are in contact with, and electrically connected to, the conductive layer 22 serving as source line SL.
  • the gaps of openings AH 1 and AH 2 are filled with a core layer 31 .
  • the core layer 31 is formed of silicon oxide, for example.
  • An insulating layer 32 is provided on the uppermost interlayer insulating layer 23 and the core layer 31 .
  • the insulating layer 32 is formed of silicon oxide, for example.
  • bit lines BL are provided on the insulating layer 32 .
  • the bit lines BL are electrically connected to the semiconductor films 29 via a contact plug 33 .
  • Bit lines BL are formed of tungsten (W), for example.
  • FIG. 7 is a view illustrating an example of the connection relationship between the semiconductor films 29 and the bit lines BL.
  • Semiconductor films 29 - 1 to 29 - 4 are electrically connected to bit lines BL 0 to BL 3 , respectively.
  • the connection relationship between the semiconductor films 29 and the bit lines BL can be optionally designed.
  • the physical arrangement of the bit lines BL can be optionally designed.
  • Openings AH 1 are arranged either in a lattice pattern or in a staggered fashion (zigzag fashion), so that a plurality of NAND strings NS are arranged.
  • FIGS. 8 to 27 are plan views and sectional views illustrating a method of manufacturing the memory cell array 10 .
  • FIGS. 8, 10, and 27 are sectional views taken along line A-A′ of FIG. 4 .
  • a silicon substrate 20 is prepared. Subsequently, as shown in FIG. B, an insulating layer 21 and a conductive layer 22 (source line SL) are formed in this order on the silicon substrate 20 .
  • the conductive layer 22 may be a laminated film in which a plurality of conductive layers are stacked.
  • the conductive layer 22 may be a laminated film in which a conductive layer formed of polycrystalline silicon, a metal layer formed of, for example, tungsten (W) and a conductive layer formed of polycrystalline silicon are stacked in this order.
  • a plurality of interlayer insulating layers 23 and a plurality of sacrifice layers 40 are alternately stacked on the conductive layer 22 , for example, by the CVD (chemical vapor deposition) method, thereby forming a laminated film.
  • An interlayer insulating layer 23 is disposed on the lowermost layer of the laminated film and on the uppermost layer of the laminated film.
  • the interlayer insulating layers 23 are formed of silicon oxide, for example.
  • the sacrifice layers 40 are formed of, for example, silicon nitride (SiN).
  • the sacrifice layers 40 may be formed of any material as long as it provides a sufficient wet etching selection ratio with respect to the interlayer insulating layers 23 , and silicon oxynitride (SiON) or the like may be used.
  • a mask layer 41 is formed on the laminated film by lithography so as to expose a region where a cross-shaped opening (memory hole) AH is to be formed.
  • a cross-shaped opening AH is formed in the laminated film by anisotropic etching such as RIE (reactive ion etching).
  • the opening AH exposes the conductive layer 22 .
  • FIG. 11( a ) is a sectional view of the region AH shown in FIG. 10 .
  • FIG. 11( b ) is a plan view illustrating how the memory cell array 10 is at position P 1 shown in FIG. 11( a ) .
  • FIG. 11( c ) is a plan view illustrating how the memory cell array 10 is at position P 2 shown in FIG. 11( a ) . That is, FIG. 11( a ) is a sectional view taken along line B-B′ shown in FIGS. 11( b ) and 11( c ) .
  • the sacrifice layers 40 are isotropically etched through the opening AH.
  • the isotropic etching is, for example, wet etching that uses phosphoric acid (H 3 PO 4 ) as an etchant.
  • H 3 PO 4 phosphoric acid
  • silicon oxide films 25 are formed on the side faces of the sacrifice layers 40 .
  • the silicon oxide films are formed, for example, by oxidizing the side faces of the sacrifice layers 40 .
  • a block insulating film 25 is formed on the side face of each sacrifice layer 40 .
  • a charge storage film 26 is formed on the side face of the opening AH, for example, by the CVD method.
  • the charge storage film 26 is formed of, for example, silicon nitride (SiN) or a metal oxide (e.g., hafnium oxide).
  • polycrystalline silicon film 27 a is formed on the side face of the charge storage film 26 , for example, by the CVD method. As a result, the concave portions formed in the sacrifice layers 40 are filled with the charge storage film 26 and polycrystalline silicon film 27 a.
  • polycrystalline silicon film 27 a is etched back by isotropic etching. Thereby, polycrystalline silicon film 27 a is divided for each sacrifice layer 40 . That is, polycrystalline silicon film 27 a is not provided in the plan view ( FIG. 15( c ) ) corresponding to position P 2 .
  • the charge storage film 26 is etched back by isotropic etching. Thereby, the charge storage film 26 is divided for each sacrifice layer 40 . That is, the charge storage film 26 is not provided in the plan view ( FIG. 16 ( c ) ) corresponding to position P 2 .
  • polycrystalline silicon film 27 b is formed again on the side face of the opening AH, for example, by the CVD method. As a result, the gaps above and under polycrystalline silicon films 27 a are filled with polycrystalline silicon film 27 b.
  • a cover film 42 is formed on the side face of the opening AH, for example, by the CVD method.
  • the cover film 42 is an insulating film formed of, for example, silicon nitride (SiN) or silicon oxide.
  • the cover film 42 is etched back by isotropic etching such that the cover film 42 is divided for each convex portion of the cross-shaped opening AH.
  • the cover film 42 remains on each of the four convex portions of the cross-shaped opening AH.
  • Polycrystalline silicon film 27 b is exposed in the concave portion between the two adjacent, convex portions.
  • polycrystalline silicon film 27 b is etched back by isotropic etching such that polycrystalline silicon film 27 b is divided for each convex portion of the opening AH.
  • the cover film 42 is present on the convex portions of the opening AH, so that polycrystalline silicon film 27 b formed on the convex portions of the opening AH remains without being etched.
  • polycrystalline silicon film 27 b is etched back by isotropic etching. Thereby, polycrystalline silicon film 27 b is divided for each sacrifice layer 40 . That is, in the opening AH, the interlayer insulating layers 23 are exposed in addition, a floating gate electrode 27 is formed by polycrystalline silicon films 27 a and 27 b.
  • a silicon oxide film is formed on the side face of the opening AH, for example, by the CVD method.
  • a tunnel insulating film 28 in contact with the floating gate electrode 27 is formed.
  • the silicon oxide film formed on the conductive layer 22 is removed.
  • a semiconductor film 29 is formed on the side face of the tunnel insulating film 28 , for example, by the CVD method.
  • the semiconductor film 29 is a polycrystalline silicon film.
  • the semiconductor film 29 is formed on the conductive layer 22 as well.
  • a cover film 30 is formed on the side face of the semiconductor film 29 , for example, by the CVD method.
  • the cover film 30 is an insulating film formed of, for example, silicon nitride (SiN) or silicon oxide.
  • the cover film 30 is etched back by isotropic etching such that the cover film 30 is divided for each convex portion of the opening AH.
  • the cover film 30 remains on each of the four convex portions of the opening AH.
  • the semiconductor film 29 is exposed in the concave portion between the two adjacent convex portions.
  • the semiconductor film 29 is etched back by isotropic etching such that the semiconductor film 29 is divided for each convex portion of the opening AH.
  • the cover film 30 is present on the convex portions of the opening AH, so that the semiconductor film 29 formed on the convex portions of the opening AH remains without being etched.
  • the tunnel insulating film 28 is etched back by isotropic etching such that the tunnel insulating film 28 is divided for each convex portion of the opening AH.
  • the cover film 30 is present on the convex portions of the opening AH, so that the tunnel insulating film 28 formed on the convex portions of the opening AH remains without being etched.
  • the charge storage film 26 is etched back by isotropic etching such that the charge storage film 26 is divided for each convex portion of the opening AH.
  • the cover film 30 is present on the convex portions of the opening AH, so that the charge storage film 26 formed on the convex portions of the opening AH remains without being etched.
  • silicon oxide is filled in the gaps of the openings AH (AH 1 and AH 2 ), for example, by the CVD method.
  • a core layer 31 is formed in the center of the opening AH.
  • CMP chemical mechanical polishing
  • the sacrifice layers 40 are replaced with a plurality of wiring layers 24 (word lines WL, and select gate lines SGS and SGD). Specifically, the sacrifice layers 40 are removed by performing wet etching using phosphoric acid (H 3 PO 4 ) as an etchant, via the regions where the side faces of the sacrifice layers 40 are exposed or via the opening. As a result, the block insulating film 25 is exposed in the recesses in which the sacrifice layers 40 were formed.
  • phosphoric acid H 3 PO 4
  • a wiring layer 24 is formed on the side face of the block insulating film 25 , for example, by the CVD method, such that the wiring layer 24 fills the recesses in which the sacrifice layers 40 were formed.
  • the wiring layer 24 includes a main body part (tungsten (W) or the like) and a barrier metal film (titanium nitride (TiN) or the like) covering the upper face, the side face, and the bottom face of the main body part.
  • an insulating layer 32 formed of, for example, silicon oxide is formed on the uppermost interlayer insulating layer 23 and the core layer 31 , for example, by the CVD method.
  • a contact plug 33 to be electrically connected to the semiconductor film 29 is formed on the semiconductor film 29 and in the insulating layer 32 .
  • a bit line BL to be electrically connected to the contact plug 33 is formed on the contact plug 33 and the insulating layer 32 .
  • a memory cell array according to the present embodiment is formed.
  • the semiconductor memory device 1 includes a plurality of wiring layers 24 (word line WL, select gate line SGD, and select gate line SGS) provided above the substrate 20 , with a plurality of interlayer insulating layers 23 interposed.
  • Each of the wiring layers 24 is provided with a cross-shaped opening AH.
  • the wiring layer 24 includes a first face SF 1 recessed in the first direction parallel to the surface of the substrate 20 , a second face SF 2 parallel to the surface of the substrate 20 and recessed in the second direction different from the first direction, a third face SF 3 parallel to the surface of the substrate 20 and recessed in a third direction different from the first and second directions, and a fourth face SF 4 parallel to the surface of the substrate 20 and recessed in a fourth direction different from the first to third directions.
  • Memory cell transistors MTa, MTb, MTc and MTd are provided on the first to fourth faces SF 1 to SF 4 of the wiring layer 24 , respectively.
  • Each memory cell transistor MT includes a block insulating film 25 , a charge storage film 26 provided on a side face of the block insulating film 25 , a floating gate electrode 27 provided on a side face of the charge storage film 25 , a tunnel insulating film 28 provided on a side face of the floating gate electrode 27 , and a semiconductor film 29 provided on a side face of the tunnel insulating film 28 .
  • four memory cell transistors MT can be arranged in the same plane of one opening AH. With this configuration, it is possible to provide a semiconductor memory device that can be highly integrated.
  • isotropic film formation and isotropic etching (wet etching, or CDE (chemical dry etching)) enables cell division without using high aspect processing.
  • FIG. 28 is a plan view of a memory cell array 10 according to another embodiment.
  • the sectional view of the memory cell array 10 is similar to that shown in FIG. 3
  • FIG. 28 is a plan view corresponding to position P 1 shown in FIG. 3 .
  • Each of wiring layers 24 is provided with an opening AH 1 .
  • the opening AH 1 has a hexagon-like shape (a six-petal shape) having six protrusions.
  • the wiring layer 24 has six curved faces SF recessed outward from the center of the opening AH 1 .
  • Six memory cell transistors MTa to MTf are provided on the six curved faces SF of the wiring layer 24 , respectively.
  • Each memory cell transistor MT includes a block insulating film 25 , a charge storage film 26 , a floating gate electrode 27 , a tunnel insulating film 28 , a semiconductor film (channel film) 29 , and a cover film 30 .
  • six memory cell transistors MT may be provided in the same level layer of the hexagon-like opening AH 1 .
  • the opening AH 1 formed in the wiring layer 24 may have an octagon-like shape (an eight-petal shape) having eight protrusions.
  • the wiring layer 24 has eight curved faces SF recessed outward from the center of the opening AH 1 .
  • eight memory cell transistors MT are provided in the same level layer of the opening AH 1 .
  • the number of convex portions the opening has is not limited to 4, 6, or 8, but can be optionally determined as long as it is 3 or more.
  • the number of memory cell transistors arranged in the same level layer is not limited to 4, 6, or 8, but can be optionally determined as long as it is 3 or more.
  • PG floating gate
  • MONOS metal-oxide-nitride-oxide-silicon
  • a charge storage film 26 formed of an insulating material is provided between a block insulating film 25 and a tunnel insulating film 28 , and a floating gate electrode 27 is not employed.
  • the PG type memory cell transistor may have a configuration in which a floating gate electrode 27 is provided between a block insulating film 25 and a tunnel insulating film 28 , and a charge storage film 26 is not employed.

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