US10454240B2 - Method of producing an optoelectronic component - Google Patents

Method of producing an optoelectronic component Download PDF

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Publication number
US10454240B2
US10454240B2 US15/761,585 US201615761585A US10454240B2 US 10454240 B2 US10454240 B2 US 10454240B2 US 201615761585 A US201615761585 A US 201615761585A US 10454240 B2 US10454240 B2 US 10454240B2
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Prior art keywords
carrier
top side
region
metallization
semiconductor chip
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US15/761,585
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US20180351324A1 (en
Inventor
Christoph Walter
Roland Enzmann
Markus Horn
Jan Seidenfaden
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Osram Oled GmbH
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Osram Opto Semiconductors GmbH
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Assigned to OSRAM OPTO SEMICONDUCTORS GMBH reassignment OSRAM OPTO SEMICONDUCTORS GMBH ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: Seidenfaden, Jan, WALTER, CHRISTOPH, ENZMANN, ROLAND, HORN, MARKUS
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    • H01S5/02272—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0235—Method for mounting laser chips
    • H01S5/02355—Fixing laser chips on mounts
    • H01S5/0237—Fixing laser chips on mounts by soldering
    • H01L33/0079—
    • H01L33/62—
    • H01L33/642—
    • H01S5/02268—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0235—Method for mounting laser chips
    • H01S5/02375—Positioning of the laser chips
    • H01S5/0238—Positioning of the laser chips using marks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/024—Arrangements for thermal management
    • H01S5/02461—Structure or details of the laser chip to manipulate the heat flow, e.g. passive layers in the chip with a low heat conductivity
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/018—Bonding of wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/858—Means for heat extraction or cooling
    • H10H20/8582—Means for heat extraction or cooling characterised by their shape
    • H01L2933/0066—
    • H01L2933/0075—
    • H01L33/0095—
    • H01L33/641—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/036—Manufacture or treatment of packages
    • H10H20/0364—Manufacture or treatment of packages of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/036—Manufacture or treatment of packages
    • H10H20/0365—Manufacture or treatment of packages of means for heat extraction or cooling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/858—Means for heat extraction or cooling
    • H10H20/8581—Means for heat extraction or cooling characterised by their material

Definitions

  • This disclosure relates to a method of producing an optoelectronic component.
  • a method of producing an optoelectronic component including providing a carrier including a top side, creating at the top side of the carrier a region that is recessed with respect to a mounting region of the top side to form a step between the mounting region and the recessed region, arranging at the top side of the carrier a metallization extending over the mounting region and the recessed region, creating a separating track in the metallization, wherein the metallization is completely severed at least in sections in the mounting region and is at least not completely severed in the recessed region, and arranging an optoelectronic semiconductor chip above the mounting region of the top side, wherein the optoelectronic semiconductor chip is aligned at the separating track.
  • FIG. 1 schematically shows a plan view of a top side of a carrier arranged in a carrier assemblage.
  • FIG. 2 schematically shows a sectional side view of the carrier.
  • FIG. 3 schematically shows a sectional side view of an optoelectronic component including the carrier and an optoelectronic semiconductor chip.
  • Our method of producing an optoelectronic component comprises steps of providing a carrier comprising a top side, creating at the top side of the carrier a region that is recessed with respect to a mounting region of the top side, wherein a step is formed between the mounting region and the recessed region, arranging at the top side of the carrier a metallization extending over the mounting region and the recessed region, creating a separating track in the metallization, wherein the metallization is completely severed at least in sections in the mounting region and is at least not completely severed in the recessed region, and arranging an optoelectronic semiconductor chip above the mounting region of the top side, wherein the optoelectronic semiconductor chip is aligned at the separating track.
  • the method results in a distinct optical contrast between the material of the carrier that is exposed in the mounting region in the region of the separating track and the metallization not completely severed in the recessed region in the region of the separating track.
  • a high-contrast alignment marking is formed as a result. The alignment marking allows a reliable automated positioning of the optoelectronic semiconductor chip above the mounting region of the top side of the carrier.
  • the optoelectronic semiconductor chip may be arranged in a manner projecting over the step. This advantageously reduces a risk of that part of the optoelectronic semiconductor chip arranged in a projecting manner being contaminated by a connecting material used to connect the optoelectronic semiconductor chip to the carrier during the process of arranging the optoelectronic semiconductor chip above the mounting region of the top side of the carrier.
  • Aligning at the separating track may comprise optically detecting a position of a boundary between the metallization completely severed at least in sections in the mounting region and the metallization at least not completely severed in the recessed region.
  • a pronounced optical contrast arises in this method between the material of the carrier that is exposed in the region of the metallization completely severed at least in sections in the mounting region and the metallization at least not completely severed in the recessed region, which pronounced optical contrast may be reliably detected in an automated manner, for example, by an optical image recognition system.
  • the position of the boundary may be detected in a precise manner as a result.
  • the position of the boundary is precisely defined by the separating track such that overall, a precise alignment of the optoelectronic semiconductor chip with only small inaccuracies is made possible.
  • the separating track may be created rectilinearly and perpendicularly to the step.
  • a particularly simple and accurate alignment of the optoelectronic semiconductor chip is made possible as a result.
  • creating the separating track rectilinearly is advantageously possible in a particularly simple manner.
  • the carrier may be provided in a carrier assemblage. After the process of creating the separating track, the carrier assemblage is divided to singulate the carrier. In this case, an outer edge of the carrier is formed by the dividing. The recessed region adjoins the outer edge such that the step is oriented parallel to the outer edge.
  • the method thereby enables a parallel production of a plurality of carriers in common work processes. The production costs per carrier and the time required to produce a carrier are reduced as a result.
  • a further advantage is that the process steps performed on the carrier assemblage may be carried out more simply and with higher accuracy owing to the larger dimensions of the carrier assemblage.
  • the recessed region adjoining the outer edge of the carrier advantageously ensures that the carrier, at its top side in the region of the outer edge, comprises no bones by which a precise alignment and mounting of the optoelectronic semiconductor chip are made more difficult or prevented.
  • Creating the separating track may be carried out by sawing or by a laser.
  • these methods enable the separating track to be created rapidly, simply and reproducibly with a precisely defined track depth and track width.
  • the separating track may be created such that the metallization is not severed in the recessed region.
  • this results in a particularly distinct contrast between the metallization completely severed at least in sections in the mounting region and the metallization not severed in the recessed region at the separating track.
  • a solder may be arranged on the metallization on the mounting region of the top side.
  • the optoelectronic semiconductor chip is then arranged on the solder.
  • the solder may mechanically secure the optoelectronic semiconductor chip and electrically contact the optoelectronic semiconductor chip.
  • the optoelectronic semiconductor chip may be a laser chip.
  • the optoelectronic component is then a laser component.
  • the laser chip may be arranged such that an emission facet of the laser chip projects over the step.
  • this ensures that during the process of arranging the laser chip above the mounting region of the top side of the carrier, no connecting material used to secure the laser chip, for example, solder reaches the emission facet of the laser chip.
  • An anode contact of the laser chip may face the top side of the carrier.
  • An emission region of the laser chip may thereby be arranged particularly close to the top side of the carrier, as a result of which an effective cooling of the laser chip may be achieved.
  • FIG. 1 shows a plan view of a carrier 200 in a schematic illustration.
  • FIG. 2 shows a sectional side view of the carrier 200 .
  • the sectional plane on which the carrier 200 is cut in the illustration in FIG. 2 is depicted in FIG. 1 .
  • the carrier 200 may also be referred to as a surmount.
  • the carrier 200 is configured as a substantially flat sheet comprising a top side 201 .
  • the carrier 200 may comprise an electrically insulating material, for example, silicon or a ceramic.
  • the carrier 200 may be provided in a carrier assemblage 300 .
  • the carrier assemblage 300 is indicated in the illustration in FIG. 1 .
  • the carrier assemblage 300 comprises a plurality of carriers 200 of identical type arranged in a plane alongside one another and connected to one another integrally in a continuous fashion.
  • the individual carriers 200 may, for example, each comprise a rectangular shape and be arranged in a rectangular grid in the carrier assemblage 300 .
  • the carrier assemblage 300 enables a parallel production of a plurality of carriers 200 in common work processes. It is only after the conclusion of the common processing steps that the individual carriers 200 are singulated by the carrier assemblage 300 being divided along separating planes 310 . Dividing the carrier assemblage 300 along the separating planes 310 may be carried out by a sawing process, for example.
  • the top side 201 of the carrier 200 comprises a mounting region 210 and a region 220 that is recessed with respect to the mounting region 210 .
  • a step 230 is formed at the boundary between the recessed region 220 and the mounting region 210 , the height of the top side 201 of the carrier 200 changing at the step.
  • the recessed region 220 of the top side 201 of the carrier 200 is arranged such that, after the process of dividing the carrier assemblage 300 along the separating planes 310 , the recessed region 220 adjoins an outer edge 240 of the carrier 200 formed at a separating plane. This means that the recessed region 220 is arranged in a marginal region of the top side 201 of the carrier 200 . It is expedient if both the outer edge 240 of the carrier 200 formed at the separating plane 310 and the step 230 formed between the recessed region 220 and the mounting region 210 run rectilinearly and are oriented parallel to one another.
  • the recessed region 220 may have been created by the top side 201 of the carrier 200 having been processed by part of the material of the carrier 200 having been removed in the recessed region 220 , for example, by an etching method or a separating method, for instance a sawing method.
  • the recessed regions 220 of a plurality of carriers 200 of the carrier assemblage 300 may have been created simultaneously in this case.
  • a plurality of recessed regions 220 per carrier 200 may have been created, for example, at mutually opposite outer edges of the respective carrier 200 , as illustrated in the example in FIGS. 1 and 2 .
  • a metallization 250 has been arranged at the top side 201 of the carrier 200 .
  • the metallization 250 extends both over the recessed region 220 and over the mounting region 210 of the top side 201 of the carrier 200 .
  • the metallization 250 may comprise titanium, platinum and/or gold, for example.
  • the metallization 250 comprises a thickness (measured perpendicularly to the top side 201 of the carrier 200 ) which is smaller than the depth of the recessed region 220 .
  • the metallization 250 may comprise a thickness of 1 ⁇ m.
  • a separating track 270 has been created in the metallization 250 at the top side 201 of the carrier 200 .
  • the separating track 270 is configured rectilinearly and extends perpendicularly to the step 230 between the recessed region 220 and the mounting region 210 and thus also perpendicularly to the outer edge 240 of the carrier 200 formed during the process of dividing the carrier assemblage 300 .
  • the separating track 270 extends both over the mounting region 210 and over the recessed region 220 of the top side 201 of the carrier 200 .
  • the metallization 250 is completely severed at least in sections in the region of the separating track 270 such that in the region of the separating track 270 in the mounting region 210 the material of the carrier 200 is at least partly exposed.
  • the metallization 250 in the separating track 270 is at least not completely severed. Consequently, in the recessed region 220 of the top side 201 of the carrier 200 in the region of the separating track 270 the material of the carrier 200 is not exposed, but rather still covered by the metallization 250 .
  • the separating track 270 it is possible to create the separating track 270 such that in the recessed region 220 of the top side 201 of the carrier 200 the metallization 250 is not severed at all by the separating track 270 .
  • the separating track 270 expediently comprises a depth larger than the thickness of the metallization 250 , but smaller than the sum of the thickness of the metallization 250 and the depth by which the recessed region 220 is recessed with respect to the mounting region 210 .
  • the separating track 270 may comprise a depth of a few ⁇ m, for example.
  • the separating track 270 may have been created by sawing or a laser, for example. If the separating track 270 has been created by sawing, then the separating track 270 may also be referred to as a sawing track.
  • a solder 260 has been arranged on the metallization 250 at the top side 201 of the carrier 200 .
  • the process of arranging the solder 260 may have been carried out before or after the process of creating the separating track 270 .
  • the solder 260 extends over a part of the mounting region 210 of the top side 201 of the carrier 200 and may also extend over a part of the recessed region 220 of the top side 201 of the carrier 200 . However, the solder 260 does not extend over that part of the top side 201 of the carrier 200 in which the separating track 270 runs.
  • the process of arranging the solder 260 may be dispensed with if the optoelectronic semiconductor chip subsequently arranged above the top side 201 of the carrier 200 is secured and electrically contacted in some other way.
  • FIG. 3 shows a schematic sectional side view of the carrier 200 in a processing state temporally succeeding the illustration in FIGS. 1 and 2 .
  • An optoelectronic semiconductor chip 110 has been arranged above the top side 201 of the carrier 200 .
  • the carrier 200 and the optoelectronic semiconductor chip 110 jointly form an optoelectronic component 100 .
  • the optoelectronic semiconductor chip 110 may be a laser chip, for example.
  • the optoelectronic component 100 is a laser component.
  • the optoelectronic semiconductor chip 110 has been arranged above the mounting region 210 of the top side 201 of the carrier 200 . In this case, the optoelectronic semiconductor chip 110 was aligned at the separating track 270 to define the position and/or orientation of the optoelectronic semiconductor chip 110 at the top side 201 of the carrier 200 .
  • the position of a boundary 280 between the metallization 250 completely severed at least in sections in the mounting region 210 and the metallization 250 at least not completely severed in the recessed region 220 of the top side 201 of the carrier 200 was detected.
  • This detection may be carried out optically, for example, by a camera, for example.
  • an optically clearly discernible contrast between the metallization 250 and the exposed material of the carrier 200 is formed, which contrast is well suited to an optical detection and the position of which contrast relative to the step 230 at the top side 201 of the carrier 200 is precisely defined.
  • the optoelectronic semiconductor chip 110 has been arranged above the top side 201 of the carrier 200 such that it projects over the step 230 .
  • the length of the projection was able to be precisely defined by the alignment at the separating track 270 , in particular by the alignment at the boundary 280 .
  • the optoelectronic semiconductor chip 110 comprises a top side 111 and an underside 112 opposite the top side 111 .
  • the optoelectronic semiconductor chip 110 was arranged above the top side 201 of the carrier 200 such that the top side 111 of the optoelectronic semiconductor chip 110 faces the top side 201 of the carrier 200 .
  • the optoelectronic semiconductor chip 110 is arranged on the solder 260 arranged in the mounting region 210 of the top side 201 of the carrier 200 and is secured by the solder 260 .
  • solder 260 it is possible to dispense with arranging the solder 260 at the top side 201 of the carrier 200 and instead, for example, to arrange a solder at the top side 111 of the optoelectronic semiconductor chip 110 before the latter is arranged above the top side 201 of the carrier 200 .
  • an adhesive for example, an electrically conductive adhesive or another securing material may also be used to secure the optoelectronic semiconductor chip 110 .
  • An electrical contact of the optoelectronic semiconductor chip 110 for example, an anode contact 120 may be formed at the top side 111 of the optoelectronic semiconductor chip 110 .
  • the anode contact 120 electrically conductively connects to the metallization 250 of the carrier 200 by the solder 260 . This makes it possible to electrically drive the optoelectronic semiconductor chip 110 via the metallization 250 .
  • the optoelectronic semiconductor chip 110 is a laser chip
  • that side face of the optoelectronic semiconductor chip 110 projecting over the step 230 between the recessed region 220 and the mounting region 210 at the top side 201 of the carrier 200 forms an emission facet 130 of the optoelectronic semiconductor chip 110 .
  • the latter emits a laser beam at the emission facet 130 in a direction perpendicular to the emission facet 130 .
  • the point where the laser beam emerges may lie near the top side 111 of the optoelectronic semiconductor chip 110 .
  • the projection of the emission facet 130 over the step 230 at the top side 201 of the carrier 200 prevents solder 260 from reaching the emission facet 130 and contaminating the latter during the securing of the optoelectronic semiconductor chip 110 at the top side 201 of the carrier 200 .
  • the recessed region 220 created at the top side 201 of the carrier 200 ensures that in the region of the step 230 no bones formed at the outer edge 240 of the carrier 200 during the process of dividing the carrier assemblage 300 are present, which bones might adversely affect the securing and alignment of the optoelectronic semiconductor chip 110 .

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Semiconductor Lasers (AREA)
  • Led Device Packages (AREA)
US15/761,585 2015-09-23 2016-09-15 Method of producing an optoelectronic component Active US10454240B2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE102015116092 2015-09-23
DE102015116092.7 2015-09-23
DE102015116092.7A DE102015116092B4 (de) 2015-09-23 2015-09-23 Verfahren zum Herstellen eines optoelektronischen Bauelements
PCT/EP2016/071847 WO2017050636A1 (de) 2015-09-23 2016-09-15 Verfahren zum herstellen eines optoelektronischen bauelements

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US20180351324A1 US20180351324A1 (en) 2018-12-06
US10454240B2 true US10454240B2 (en) 2019-10-22

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US (1) US10454240B2 (enExample)
JP (1) JP6779283B2 (enExample)
DE (1) DE102015116092B4 (enExample)
WO (1) WO2017050636A1 (enExample)

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DE102017108385A1 (de) * 2017-04-20 2018-10-25 Osram Opto Semiconductors Gmbh Laserbarren und Halbleiterlaser sowie Verfahren zur Herstellung von Laserbarren und Halbleiterlasern
DE102020111394A1 (de) 2020-04-27 2021-10-28 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zum herstellen einer halbleiterlaseranordnung und halbleiterlaseranordnung
DE102021131795A1 (de) 2021-12-02 2023-06-07 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Laserbauelement und verfahren zur herstellung eines laserbauelements

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US20180351324A1 (en) 2018-12-06
JP6779283B2 (ja) 2020-11-04
DE102015116092B4 (de) 2018-06-14
DE102015116092A1 (de) 2017-03-23
JP2018527757A (ja) 2018-09-20

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