TWI908733B - 在區域選擇沉積中減緩側向膜成長的方法 - Google Patents
在區域選擇沉積中減緩側向膜成長的方法Info
- Publication number
- TWI908733B TWI908733B TW109124199A TW109124199A TWI908733B TW I908733 B TWI908733 B TW I908733B TW 109124199 A TW109124199 A TW 109124199A TW 109124199 A TW109124199 A TW 109124199A TW I908733 B TWI908733 B TW I908733B
- Authority
- TW
- Taiwan
- Prior art keywords
- film
- metal
- barrier layer
- processing method
- substrate processing
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
- H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
- H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
- H10P14/432—Chemical deposition, e.g. chemical vapour deposition [CVD] using selective deposition
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/61—Formation of materials, e.g. in the shape of layers or pillars of insulating materials using masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
- H10P14/6326—Deposition processes
- H10P14/6328—Deposition from the gas or vapour phase
- H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
- H10P14/6326—Deposition processes
- H10P14/6328—Deposition from the gas or vapour phase
- H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H10P14/6339—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
- H10P14/6502—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials
- H10P14/6506—Formation of intermediate materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
Landscapes
- Chemical Vapour Deposition (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Plasma & Fusion (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201962875882P | 2019-07-18 | 2019-07-18 | |
| US62/875,882 | 2019-07-18 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW202113119A TW202113119A (zh) | 2021-04-01 |
| TWI908733B true TWI908733B (zh) | 2025-12-21 |
Family
ID=74209997
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW109124199A TWI908733B (zh) | 2019-07-18 | 2020-07-17 | 在區域選擇沉積中減緩側向膜成長的方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US11804376B2 (https=) |
| JP (1) | JP7531981B2 (https=) |
| KR (1) | KR102780321B1 (https=) |
| TW (1) | TWI908733B (https=) |
| WO (1) | WO2021011761A1 (https=) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021162871A1 (en) | 2020-02-13 | 2021-08-19 | Lam Research Corporation | High aspect ratio etch with infinite selectivity |
| KR102866849B1 (ko) | 2020-02-19 | 2025-10-01 | 램 리써치 코포레이션 | 그래핀 통합 (graphene integration) |
| JP2022137698A (ja) * | 2021-03-09 | 2022-09-22 | 東京エレクトロン株式会社 | 成膜方法および成膜システム |
| US20240030062A1 (en) * | 2021-04-16 | 2024-01-25 | Lam Research Corporation | Integration of fully aligned via through selective deposition and resistivity reduction |
| JP7583669B2 (ja) * | 2021-04-30 | 2024-11-14 | 東京応化工業株式会社 | 表面処理方法、基板表面の領域選択的製膜方法及び表面処理剤 |
| JP2024523510A (ja) * | 2021-07-06 | 2024-06-28 | 東京エレクトロン株式会社 | 自己組織化単分子層を使用する選択的な膜形成 |
| JP7833545B2 (ja) * | 2021-11-26 | 2026-03-19 | ソウルブレイン シーオー., エルティーディー. | 高誘電率薄膜用マスキング剤、それを利用した選択領域蒸着方法、それから製造された半導体基板及び半導体素子 |
| JP2023117045A (ja) * | 2022-02-10 | 2023-08-23 | 東京エレクトロン株式会社 | 基板処理方法 |
| JP7853009B2 (ja) * | 2022-02-14 | 2026-04-28 | 東京エレクトロン株式会社 | 成膜方法及び成膜装置 |
| JP2023142601A (ja) * | 2022-03-25 | 2023-10-05 | 東京エレクトロン株式会社 | 成膜方法及び成膜装置 |
| WO2023204453A1 (ko) * | 2022-04-19 | 2023-10-26 | 인천대학교 산학협력단 | 영역-선택적 원자층 증착법을 이용한 박막의 선택적 증착방법 및 박막이 선택적으로 형성된 기판 |
| CN119096004A (zh) * | 2022-04-19 | 2024-12-06 | 仁川大学校产学协力团 | 使用原子层沉积法的薄膜的区域选择性沉积方法以及选择性形成薄膜的基板 |
| JP2025044774A (ja) * | 2023-09-20 | 2025-04-02 | 東京エレクトロン株式会社 | 基板処理方法及び基板処理装置 |
| US20250185329A1 (en) * | 2023-12-04 | 2025-06-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Selective formation of etch stop layers and the structures thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201835367A (zh) * | 2017-02-14 | 2018-10-01 | 荷蘭商Asm Ip控股公司 | 選擇性沉積之方法、用於有機層沉積之設備以及積體電路金屬化結構 |
| US20190164749A1 (en) * | 2017-11-20 | 2019-05-30 | Tokyo Electron Limited | Method of selective deposition for forming fully self-aligned vias |
Family Cites Families (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6100195A (en) * | 1998-12-28 | 2000-08-08 | Chartered Semiconductor Manu. Ltd. | Passivation of copper interconnect surfaces with a passivating metal layer |
| US6541863B1 (en) * | 2000-01-05 | 2003-04-01 | Advanced Micro Devices, Inc. | Semiconductor device having a reduced signal processing time and a method of fabricating the same |
| AU2002952384A0 (en) * | 2002-10-31 | 2002-11-14 | Swinburne University Of Technology | Structures |
| US7772128B2 (en) * | 2006-06-09 | 2010-08-10 | Lam Research Corporation | Semiconductor system with surface modification |
| JP2008021814A (ja) * | 2006-07-13 | 2008-01-31 | Hitachi Ltd | 電界効果トランジスタ、有機薄膜トランジスタおよび有機トランジスタの製造方法 |
| JP2008171978A (ja) | 2007-01-11 | 2008-07-24 | Konica Minolta Holdings Inc | 有機薄膜トランジスタ |
| TWI365551B (en) * | 2007-12-14 | 2012-06-01 | Ind Tech Res Inst | Method of fabricating a electrical device |
| JP2009256796A (ja) | 2008-03-27 | 2009-11-05 | Horiba Ltd | 単分子膜形成装置及び方法 |
| CN102598333A (zh) | 2009-10-26 | 2012-07-18 | Imec公司 | 制造有机器件的方法 |
| WO2014139793A1 (en) | 2013-03-15 | 2014-09-18 | Asml Netherlands B.V. | Methods for providing lithography features on a substrate by self-assembly of block copolymers |
| US9076845B2 (en) * | 2013-10-03 | 2015-07-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming a high density dielectric etch-stop layer |
| JP6263450B2 (ja) * | 2014-07-24 | 2018-01-17 | 東京エレクトロン株式会社 | 有機単分子膜形成方法 |
| CN107406977A (zh) | 2015-02-26 | 2017-11-28 | 应用材料公司 | 使用自组装单层的选择性电介质沉积的方法 |
| JP6792134B2 (ja) * | 2015-10-27 | 2020-11-25 | 富士通株式会社 | 半導体装置及びその製造方法 |
| US9875907B2 (en) * | 2015-11-20 | 2018-01-23 | Applied Materials, Inc. | Self-aligned shielding of silicon oxide |
| WO2017151639A1 (en) * | 2016-03-03 | 2017-09-08 | Applied Materials, Inc. | Improved self-assembled monolayer blocking with intermittent air-water exposure |
| US9716005B1 (en) * | 2016-03-18 | 2017-07-25 | Applied Materials, Inc. | Plasma poisoning to enable selective deposition |
| JP2017222928A (ja) | 2016-05-31 | 2017-12-21 | 東京エレクトロン株式会社 | 表面処理による選択的堆積 |
| US10068764B2 (en) * | 2016-09-13 | 2018-09-04 | Tokyo Electron Limited | Selective metal oxide deposition using a self-assembled monolayer surface pretreatment |
| US11430656B2 (en) * | 2016-11-29 | 2022-08-30 | Asm Ip Holding B.V. | Deposition of oxide thin films |
| TWI739984B (zh) * | 2017-01-31 | 2021-09-21 | 美商應用材料股份有限公司 | 就圖案化應用進行選擇性沉積之方案 |
| KR102363262B1 (ko) * | 2017-03-23 | 2022-02-16 | 삼성디스플레이 주식회사 | 유기 발광 표시 장치의 제조 방법 |
| TWI850084B (zh) * | 2017-06-14 | 2024-07-21 | 美商應用材料股份有限公司 | 用於達成無缺陷自組裝單層的晶圓處理設備 |
| JP7279024B2 (ja) | 2017-09-12 | 2023-05-22 | アプライド マテリアルズ インコーポレイテッド | 化学エッチングによる選択的堆積の欠陥除去 |
-
2020
- 2020-07-16 KR KR1020227001116A patent/KR102780321B1/ko active Active
- 2020-07-16 WO PCT/US2020/042305 patent/WO2021011761A1/en not_active Ceased
- 2020-07-16 US US16/930,842 patent/US11804376B2/en active Active
- 2020-07-16 JP JP2022503017A patent/JP7531981B2/ja active Active
- 2020-07-17 TW TW109124199A patent/TWI908733B/zh active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201835367A (zh) * | 2017-02-14 | 2018-10-01 | 荷蘭商Asm Ip控股公司 | 選擇性沉積之方法、用於有機層沉積之設備以及積體電路金屬化結構 |
| US20190164749A1 (en) * | 2017-11-20 | 2019-05-30 | Tokyo Electron Limited | Method of selective deposition for forming fully self-aligned vias |
Also Published As
| Publication number | Publication date |
|---|---|
| JP7531981B2 (ja) | 2024-08-13 |
| JP2022541535A (ja) | 2022-09-26 |
| US11804376B2 (en) | 2023-10-31 |
| US20210020444A1 (en) | 2021-01-21 |
| WO2021011761A1 (en) | 2021-01-21 |
| KR102780321B1 (ko) | 2025-03-11 |
| TW202113119A (zh) | 2021-04-01 |
| KR20220034785A (ko) | 2022-03-18 |
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