TWI799501B - 組態記憶體單元及操作積體電路之方法 - Google Patents
組態記憶體單元及操作積體電路之方法 Download PDFInfo
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- TWI799501B TWI799501B TW108102414A TW108102414A TWI799501B TW I799501 B TWI799501 B TW I799501B TW 108102414 A TW108102414 A TW 108102414A TW 108102414 A TW108102414 A TW 108102414A TW I799501 B TWI799501 B TW I799501B
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- integrated circuit
- memory cell
- configuration memory
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
- G11C14/009—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4078—Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
- G11C11/4125—Cells incorporating circuit means for protecting against loss of information
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0064—Verifying circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0097—Erasing, e.g. resetting, circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
- G11C14/0063—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
- G11C14/0072—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is a ferroelectric element
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
- G11C14/0081—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/52—Protection of memory contents; Detection of errors in memory contents
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/005—Circuit means for protection against loss of information of semiconductor storage devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/79—Array wherein the access device being a transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
- H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
Applications Claiming Priority (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201862625036P | 2018-02-01 | 2018-02-01 | |
US62/625,036 | 2018-02-01 | ||
US201862642453P | 2018-03-13 | 2018-03-13 | |
US62/642,453 | 2018-03-13 | ||
US201862656923P | 2018-04-12 | 2018-04-12 | |
US62/656,923 | 2018-04-12 | ||
US16/249,291 | 2019-01-16 | ||
US16/249,291 US10714180B2 (en) | 2018-02-01 | 2019-01-16 | Hybrid configuration memory cell |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201935483A TW201935483A (zh) | 2019-09-01 |
TWI799501B true TWI799501B (zh) | 2023-04-21 |
Family
ID=67392330
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW108102414A TWI799501B (zh) | 2018-02-01 | 2019-01-22 | 組態記憶體單元及操作積體電路之方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US10714180B2 (zh) |
CN (1) | CN111656449B (zh) |
DE (1) | DE112019000653T5 (zh) |
TW (1) | TWI799501B (zh) |
WO (1) | WO2019152228A1 (zh) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10714180B2 (en) | 2018-02-01 | 2020-07-14 | Microsemi Soc Corp. | Hybrid configuration memory cell |
US11031078B2 (en) | 2019-03-08 | 2021-06-08 | Microsemi Soc Corp. | SEU stabilized memory cells |
US10819318B1 (en) | 2019-09-23 | 2020-10-27 | Microchip Technology Inc. | Single event upset immune flip-flop utilizing a small-area highly resistive element |
FR3106692B1 (fr) | 2020-01-27 | 2024-01-19 | St Microelectronics Rousset | Dispositif de mémoire vive statique non-volatile et procédé de commande correspondant. |
CN112306726B (zh) * | 2020-10-20 | 2022-05-03 | 中国电子科技集团公司第五十二研究所 | 一种抗单粒子翻转系统及方法 |
CN116997965A (zh) | 2021-03-08 | 2023-11-03 | 微芯片技术股份有限公司 | 选择性交叉耦合反相器以及相关设备、系统和方法 |
US11671099B2 (en) | 2021-05-21 | 2023-06-06 | Microchip Technology Inc. | Logic cell for programmable gate array |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060023503A1 (en) * | 2004-07-28 | 2006-02-02 | Aplus Flash Technology, Inc. | Novel NVRAM memory cell architecture that integrates conventional SRAM and flash cells |
US20080253180A1 (en) * | 2005-07-05 | 2008-10-16 | Michel Nicolaidis | Hardened Memory Cell |
US20090059657A1 (en) * | 2007-08-27 | 2009-03-05 | Cannon Ethan H | Cmos storage devices configurable in high performance mode or radiation tolerant mode |
US20100027321A1 (en) * | 2007-11-30 | 2010-02-04 | Bin Li | Non-Volatile Single-Event Upset Tolerant Latch Circuit |
US20130107615A1 (en) * | 2007-02-12 | 2013-05-02 | Avalanche Technology, Inc. | Memory sensing circuit |
US20130308373A1 (en) * | 2012-05-18 | 2013-11-21 | Alexander Mikhailovich Shukh | Nonvolatile Latch Circuit |
US20150340090A1 (en) * | 2013-12-06 | 2015-11-26 | Empire Technology Development Llc | Non-volatile sram with multiple storage states |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3654394A (en) | 1969-07-08 | 1972-04-04 | Gordon Eng Co | Field effect transistor switch, particularly for multiplexing |
US4577149A (en) | 1982-07-06 | 1986-03-18 | Sperry Corporation | Detection of catastrophic failure of dielectric, improper connection, and temperature of a printed circuit assembly via one wire |
US5552627A (en) | 1990-04-12 | 1996-09-03 | Actel Corporation | Electrically programmable antifuse incorporating dielectric and amorphous silicon interlayers |
US6762621B1 (en) | 1998-12-31 | 2004-07-13 | Actel Corporation | Programmable multi-standard I/O architecture for FPGAs |
US6317359B1 (en) * | 1999-07-07 | 2001-11-13 | Iowa State University Research Foundation, Inc. | Non-volatile magnetic circuit |
US6775178B2 (en) | 2002-04-04 | 2004-08-10 | Honeywell International Inc. | SEU resistant SRAM using feedback MOSFET |
US7109752B1 (en) | 2004-02-14 | 2006-09-19 | Herman Schmit | Configurable circuits, IC's, and systems |
GB2417588B (en) | 2004-08-23 | 2008-06-04 | Seiko Epson Corp | Memory cell |
FI124317B (fi) | 2007-02-12 | 2014-06-30 | Abb Oy | Sähkömoottorikäyttö |
US7468904B2 (en) | 2007-02-23 | 2008-12-23 | Bae Systems Information And Electronic Systems Integration Inc. | Apparatus for hardening a static random access memory cell from single event upsets |
KR100949264B1 (ko) | 2008-06-10 | 2010-03-25 | 주식회사 하이닉스반도체 | 반도체 소자의 모니터링 회로 |
US8269204B2 (en) | 2009-07-02 | 2012-09-18 | Actel Corporation | Back to back resistive random access memory cells |
CN103828238A (zh) * | 2011-07-29 | 2014-05-28 | 科洛斯巴股份有限公司 | 使用双端非易失性存储器的现场可编程门阵列 |
US9746967B2 (en) | 2011-09-15 | 2017-08-29 | Apple Inc. | Concurrent touch and negative pixel scan |
US8933502B2 (en) | 2011-11-21 | 2015-01-13 | Sandisk Technologies Inc. | 3D non-volatile memory with metal silicide interconnect |
WO2013078439A2 (en) * | 2011-11-22 | 2013-05-30 | Silicon Space Technology Corporation | Memory circuit incorporating radiation hardened memory scrub engine |
US9001578B2 (en) * | 2012-09-11 | 2015-04-07 | Seagate Technology Llc | Soft erasure of memory cells |
US8929125B2 (en) * | 2013-02-20 | 2015-01-06 | Micron Technology, Inc. | Apparatus and methods for forming a memory cell using charge monitoring |
CN109326581B (zh) | 2014-03-24 | 2023-01-10 | 太浩研究有限公司 | 使用间隔体击穿的反熔丝元件 |
KR102265464B1 (ko) * | 2014-12-12 | 2021-06-16 | 삼성전자주식회사 | 분리 센싱 타입의 센싱 회로를 가지는 반도체 메모리 장치 및 그에 따른 데이터 센싱 방법 |
JP6797895B2 (ja) | 2015-07-27 | 2020-12-09 | パワー ダウン セミコンダクター インコーポレイテッド | 共振駆動回路を用いた低電力sramビットセル |
US10635619B2 (en) | 2016-10-12 | 2020-04-28 | Cirrus Logic, Inc. | Encoding for multi-device synchronization of devices |
JP2018156700A (ja) * | 2017-03-16 | 2018-10-04 | 東芝メモリ株式会社 | 不揮発性半導体記憶装置 |
KR102245385B1 (ko) | 2017-03-28 | 2021-04-27 | 에스케이하이닉스 주식회사 | 자기 소자를 포함하는 lut, 이를 포함하는 fpga 및 기술 매핑 방법 |
US20190228825A1 (en) | 2018-01-24 | 2019-07-25 | Microsemi Soc Corp. | Vertical resistor based sram cells |
US10714180B2 (en) | 2018-02-01 | 2020-07-14 | Microsemi Soc Corp. | Hybrid configuration memory cell |
-
2019
- 2019-01-16 US US16/249,291 patent/US10714180B2/en active Active
- 2019-01-19 CN CN201980010057.0A patent/CN111656449B/zh active Active
- 2019-01-19 DE DE112019000653.3T patent/DE112019000653T5/de active Pending
- 2019-01-19 WO PCT/US2019/014385 patent/WO2019152228A1/en active Application Filing
- 2019-01-22 TW TW108102414A patent/TWI799501B/zh active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060023503A1 (en) * | 2004-07-28 | 2006-02-02 | Aplus Flash Technology, Inc. | Novel NVRAM memory cell architecture that integrates conventional SRAM and flash cells |
US20080253180A1 (en) * | 2005-07-05 | 2008-10-16 | Michel Nicolaidis | Hardened Memory Cell |
US20130107615A1 (en) * | 2007-02-12 | 2013-05-02 | Avalanche Technology, Inc. | Memory sensing circuit |
US20090059657A1 (en) * | 2007-08-27 | 2009-03-05 | Cannon Ethan H | Cmos storage devices configurable in high performance mode or radiation tolerant mode |
US20100027321A1 (en) * | 2007-11-30 | 2010-02-04 | Bin Li | Non-Volatile Single-Event Upset Tolerant Latch Circuit |
US20130308373A1 (en) * | 2012-05-18 | 2013-11-21 | Alexander Mikhailovich Shukh | Nonvolatile Latch Circuit |
US20150340090A1 (en) * | 2013-12-06 | 2015-11-26 | Empire Technology Development Llc | Non-volatile sram with multiple storage states |
Also Published As
Publication number | Publication date |
---|---|
US20190237139A1 (en) | 2019-08-01 |
DE112019000653T5 (de) | 2020-10-15 |
TW201935483A (zh) | 2019-09-01 |
CN111656449B (zh) | 2023-09-05 |
CN111656449A (zh) | 2020-09-11 |
US10714180B2 (en) | 2020-07-14 |
WO2019152228A1 (en) | 2019-08-08 |
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