TWI778175B - 用於形成鐵電場效電晶體之方法 - Google Patents

用於形成鐵電場效電晶體之方法 Download PDF

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TWI778175B
TWI778175B TW107140260A TW107140260A TWI778175B TW I778175 B TWI778175 B TW I778175B TW 107140260 A TW107140260 A TW 107140260A TW 107140260 A TW107140260 A TW 107140260A TW I778175 B TWI778175 B TW I778175B
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浩德 傑 凡
翰斯 克里斯多夫 亞德曼
林瀚中
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比利時商愛美科公司
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Abstract

根據本發明概念之一態樣，提供一種用於形成一FeFET裝置之方法，該方法包括： 使一層堆疊形成於一閘極結構上，該層堆疊包含一鐵電層及一犧牲應力源層，其中該犧牲應力源層在形成該鐵電層之後形成， 使該層堆疊經受一熱處理以引起該鐵電層中之一相變， 在該熱處理之後，由一二維材料通道層替換該犧牲應力源層，及 形成與該2D材料通道層接觸之一源極接點及一汲極接點。

Description

用於形成鐵電場效電晶體之方法
本發明概念係關於一種用於形成一鐵電場效電晶體之方法。
一鐵電場效電晶體(FeFET)係提高各種應用中(例如記憶體技術中)之關注之一裝置類型。替代或除閘極與通道之間的習知閘極介電層之外，一FeFET包含一鐵電層。
一種新興裝置技術係採用一二維(2D)材料層作為一通道之電晶體。2D材料展示作為甚至更快、更功率有效及更小電子裝置之一致能器之前景。石墨烯及過渡金屬二硫屬化物材料(TMDC)係2D材料之顯著實例。
本發明概念之一目的係提供一種達成形成具有一2D材料通道層之一FeFET裝置之方法。可自以下理解進一步及替代目的。
根據本發明概念之一態樣，提供一種用於形成一FeFET裝置之方法，該方法包括：使一層堆疊形成於一閘極結構上，該層堆疊包含一鐵電層及一犧牲 應力源層，其中該犧牲應力源層在形成該鐵電層之後形成，使該層堆疊經受一熱處理以引起該鐵電層中之一相變，在該熱處理之後，由一二維材料通道層替換該犧牲應力源層，及形成與該2D材料通道層接觸之一源極接點及一汲極接點。
本發明基於以下洞察：在製造具有一二維(2D)材料層中之一通道之一FeFET裝置時，一犧牲應力源層之存在可在該熱處理期間提供該鐵電層中之該相變之改良控制。更具體而言，該犧牲應力源層可(與該熱處理組合)誘發該鐵電層中之一鐵電相或鐵電狀態，即，引起該鐵電層中至一鐵電相或鐵電狀態之一相變。該犧牲應力源層可藉由誘發該鐵電層中之應力而促成該相變。
由於該犧牲應力源層而非該2D材料通道層在該熱處理期間存在，因此該2D材料通道層不需要曝露於該熱處理之(可能高)熱預算。無論如何，在該熱處理期間，該2D材料通道層將不能夠相對於該鐵電層提供任何顯著應力誘發功能。
另外，由於當將該犧牲應力源層用該2D材料通道層替換時該閘極結構可已在適當位置中，因此，可進一步減少該2D材料通道層曝露於不良程序條件中。作為一繪示性實例，使得該閘極結構替代地在該2D材料通道層之後沈積(例如沈積於該2D材料通道層之頂部上)，該閘極結構之沈積可引起對該2D材料通道層之損壞及應力。
鑑於上文，可理解方法提供以下優點：在不受限於可由該2D材料忍受之該熱預算之情況下提供對該鐵電層之鐵電性質之有利控制。
如可自上文理解，就「一鐵電層」而言，特此意謂一材料 之一層，其具有其中該層呈現鐵電性(至少當保持在低於形成該鐵電層之該材料之居里溫度之一溫度下時)之一相或一狀態。該鐵電層可但不需要在該熱處理之前展現鐵電性。在任何情況中，該鐵電層可在該熱處理之後展現鐵電性(即，在已冷卻至低於居里溫度之一溫度之後)。
在該鐵電層已在該熱處理之前展現鐵電性之一程度之情況中，該鐵電層可在該熱處理之後展現鐵電性之一增加程度。
該熱處理可使得該鐵電層之至少一部分(較佳地至少一主要部分)在該熱處理之後處於一鐵電狀態中(即，展現鐵電性)。
該熱處理可包含將該鐵電層加熱至超過形成該鐵電層之該材料之居里溫度之一溫度。
該鐵電層可經受在300℃至1200℃、較佳地500℃至1000℃、更佳地600℃至900℃之範圍內之一溫度。
方法可進一步包括在該熱處理之後，允許鐵電層在用該2D材料通道層替換該犧牲應力源層之前冷卻。可藉此減少該2D材料通道層上之熱誘發應力。
該犧牲應力源層可包含一金屬層。該犧牲應力源層可為一金屬層。在該熱處理期間，基於金屬之應力源可在該鐵電層中誘發有利量之應力。一金屬層亦可耐受高熱預算程序步驟。
該金屬層可包含氮化鈦。該金屬層可為氮化鈦層。在該熱處理期間，氮化鈦層可包含該鐵電層中之有利量之應力。再者，存在用於移除對該鐵電層具有一相對高選擇性之一金屬層之程序。替代地，該金屬層可包含氮化鉭或氮化鉭鈦或可為一層氮化鉭或氮化鉭鈦。
該鐵電層可經形成具有在2nm至20nm、較佳地在2nm至 8nm之範圍內之一厚度。此範圍內且在後述更窄範圍內之一甚至更大程度之一厚度使得該鐵電層能夠經形成具有期望鐵電性質，同時仍允許一足夠閘極至通道電容。
使該犧牲應力源層由該二維材料通道層替換可包括自該層堆疊移除該犧牲應力源層且之後形成該二維材料通道層。該犧牲應力源層可藉由將該犧牲應力源層選擇性地蝕刻至該層堆疊之其他層而移除。
該鐵電層可包含氧化鉿、氧化鋯、鈦酸鉿或氧化鋯鉿。此等氧化物可呈現有利鐵電性質以及達成一低洩漏電流密度(即使在相對小厚度下)。該鐵電層可視情況經形成以包含摻雜劑。摻雜劑可促進該鐵電層材料至一鐵電相之轉變。
該2D通道材料層可包含一或多個單層之一過渡金屬二硫屬化物(TMDC)材料或一或多個單層之石墨烯。
該2D通道材料層可包含一或多個單層之WS2、WSe2、MoS2、MoSe2、WTe2或MoTe2。此等TMDC材料使得電晶體裝置具有有利電性質。
本發明方法可與一垂直層堆疊組態以及橫向層堆疊組態兩者相容。
因此，根據一實施例，該閘極結構配置於一基板上且呈現沿平行於該基板之一主表面之一平面延伸之一上表面，且其中該層堆疊形成於該上表面上，其中該鐵電層形成於該閘極結構上且該犧牲應力源層形成於該鐵電層上。
根據一替代實施例，該閘極結構配置於一基板上，該基板具有自該基板垂直延伸之一半導體結構，該半導體結構具有該閘極結構配 置於其上之一側壁表面。
該閘極結構可為一虛設閘極結構，其中方法可進一步包括使該虛設閘極結構由一替換閘極結構進行替換。此對於上文所提及之橫向組態可係尤其有利。
替代地，該閘極結構可為一閘極電極(即，具諸如金屬之一導電材料)。
該層堆疊可進一步包含在形成該鐵電層之後形成之一高K值介電層。可藉此增加該閘極與該通道之間的一有效電容耦合。該高K值介電層可在形成該犧牲應力源層之前形成。藉此，可避免該熱處理之鐵電層之曝露於該高K值形成程序條件。
100:鐵電場效電晶體(FeFET)裝置
102:閘極結構
104:鐵電層
106:高K值介電層
108:犧牲應力源層
110:層堆疊
112:二維(2D)材料通道層
114:源極接點
116:汲極接點
200:鐵電場效電晶體(FeFET)裝置
210:層堆疊
220:基板
222:絕緣層
224:導電互連結構
310:層堆疊
314:源極電極
316:汲極電極
320:基板
321:垂直半導體結構
321a:側壁表面
H:熱處理
S:方向
將參考附圖透過以下繪示性及非限制性詳細描述更佳理解本發明概念之以上以及額外目的、特徵及優點。在圖式中，除非另有所示，否則相同元件符號將用於相同元件。
圖1至圖5示意性地繪示用於形成一FeFET裝置之一方法。
圖6係一種裝置之示意繪示圖。
圖7a及7b係另一種裝置之示意繪示圖。
現將參考圖1至圖5描述用於形成一FeFET裝置100之一方法。
圖1示意性地展示一閘極結構102。在圖2中，一層堆疊110已形成於閘極結構102上。層堆疊包含一鐵電層104及一犧牲應力源層 108。圖2中所展示之方向S指示層堆疊110之層已形成之順序(即，堆疊方向S)。因此，犧牲應力源層108在形成鐵電層104之後形成。取決於裝置之幾何形狀，堆疊方向S可相對於一下伏基板(圖中未展示)之一主表面定向為平行於該主表面之一法線方向或定向為平行於該主表面(方向S之至少一主要分量可平行於該法線方向或該主表面)。視情況，層堆疊110之形成可進一步包括在形成鐵電層104之後形成一高K值介電層106。因此，在形成犧牲應力源層108之後，高K值介電層106可夾置於鐵電層104與犧牲應力源層108之間。
圖3示意性地展示經受一熱處理H之層堆疊110。在熱處理H期間，在鐵電層104中引起一相變。藉此，鐵電層104可獲得一鐵電狀態。
在圖4中，在熱處理之後，犧牲應力源層108已自層堆疊110移除。在圖5中，一2D材料通道層112已形成於層堆疊110中，因此替換犧牲應力源層108。一源極接點114及一汲極接點116已形成於2D材料通道層112上。因此，已形成一FeFET裝置100。
閘極結構102可為由一導電材料形成之一閘極電極。該導電材料可為一金屬(例如TiN、TaN或TiTaN)。進一步實例包含TiC、TaC、Ru、W、TiW或Pt。閘極結構102亦可由若干層前述金屬材料或其等之合金形成。然而，如熟習技術者所知，進一步閘極導體材料亦係可行的。替代地，閘極結構102可為(例如)多晶矽或一些其他習知虛設閘極材料之一虛設閘極結構。接著，可移除閘極結構102且將其用一替換閘極結構(即，如上文所描述之一閘極電極)替換。
鐵電層104形成於閘極結構102上。鐵電層104可直接形成 於閘極結構102上(即，在鐵電層104及閘極結構102中間無層)。鐵電層104可為氧化鉿層(HfO2)、氧化鋯層(ZrO2)、鈦酸鉿層(即，氧化鈦鉿HfxTi1-xO2)或一層氧化鋯鉿(HfxZr1-xO2)。鐵電層104亦可形成為前述層之兩者或兩者以上之一複合層。鐵電層104可藉由原子層沈積(ALD)形成。鐵電層104可經形成具有在2nm至20nm、較佳地在2nm至8nm之範圍內之一厚度，其考量洩漏電流密度要求及閘極電容。為促進獲得足夠強鐵電性質，可摻雜(例如)HrO2或ZrO2之一鐵電層104。可能摻雜劑包含Si、Ge、Al、Ga、Ba、Sr、Y、Sc或任何鑭系元素。在陽離子中，一摻雜濃度可有利地為7%或7%以下。例如，鐵電層104可在其沈積期間摻雜。然而，一鐵電層之其他組合物亦係可行的，例如(Pb,Zr)TiO3或SrBi2Ta2O9，具有(例如)在10nm至200nm之範圍內(取決於(尤其)待形成之電晶體裝置中所需之閘極電容之量)之一層厚度。
高K值介電層106可直接形成於鐵電層104上。高K值介電層106可由一高K值介電材料層形成。高K值介電層106可為HfO2層、ZrO2層、HfTiO4層。高K值介電層106可藉由ALD或一些其他適合習知氣相沈積程序形成。
犧牲應力源層108(下文係應力源層108)形成於鐵電層104上。應力源層108可直接形成於鐵電層104上。然而，若高K值介電層106存在於層堆疊110中，則應力源層108可形成於鐵電層104上，其中高K值介電層106作為一中間層。在後者之情況中，應力源層108可直接形成於高K值介電層106上。
應力源層108可由一金屬層形成。金屬層可為連同閘極電極提及之金屬材料之任何者之一層(諸如TiN、TaN或TiTaN)。金屬層可藉 由ALD、CVD或物理氣相沈積(PVD)形成。作為一非限制性實例，應力源層108可經形成具有在2nm至40nm之範圍內之一厚度。
熱處理H可包括將鐵電層104及應力源層108加熱至在300℃至1200℃、較佳地500℃至1000℃、更佳地600℃至900℃之一範圍內之一溫度。例如，層堆疊110可在具有在上文所提及之範圍內之一周圍腔室溫度之一烘箱中加熱。替代地，鐵電層104可藉由使一加熱器元件與層堆疊110相接而加熱至上述範圍中之一溫度。熱處理H可具有大約1分鐘之一持續時間。然而，較短及較長持續時間兩者亦係可行的，取決於(尤其)鐵電層104之厚度。熱處理亦可呈所謂之尖波退火(具有大約1秒之一典型持續時間)之形式。替代地，可採用具有次秒持續時間(例如毫秒下至次微秒)非常快速技術(諸如雷射退火)。不管熱處理之形式，熱處理可經調適以供應一足夠熱預算至鐵電層104使得鐵電層(即，形成鐵電層104之材料)可(例如)藉由結晶為鐵電狀態而轉變至一鐵電狀態。鐵電層104可藉此具有所要鐵電性質(至少在允許鐵電層104呈現低於鐵電材料之居里溫度之一溫度之後)。對應於鐵電相之一鐵電材料之特定結構可取決於鐵電材料之類型。舉實例而言，HfO2及ZrO2之鐵電相對應於(例如)一斜方晶相。
作為一非限制性實例，包含HfO2之8nm厚鐵電層104及TiN之10nm厚應力源層108之一層堆疊110可加熱(例如在一烘箱中)至大約800℃達1分鐘之一持續時間。作為另一非限制性實例，具有一類似層組態之一層堆疊110可藉由將鐵電層104雷射退火加熱至大約950℃達數毫秒之一持續時間而經受熱處理。
在熱處理H之後，應力源層108可藉由將應力源層108選擇性地蝕刻至鐵電層104(及高K值介電層106(若存在))而自層堆疊110移 除。可使用如本身係本技術中已知之一適合濕式蝕刻移除一金屬應力源層108。替代地，一乾式蝕刻程序(諸如一反應離子蝕刻(RIE))可用於移除一金屬應力源層108。
在移除應力源層108之後，2D材料通道層112(下文中係通道層112)形成於鐵電層104上。通道層112可直接形成於鐵電層104上。然而，若高K值介電層106存在於層堆疊110中，通道層112可形成於鐵電層104上，其中高K值介電層106作為一中間層。在該情況中，通道層112可直接形成於高K值介電層106上。
通道層112可由一或多個單層之石墨烯形成。可採用用於使一石墨烯通道層112形成於鐵電層104上之技術方法之任何狀態。例如，一或多個單層之石墨烯之一石墨烯層可生長於一模板基板上且隨後使用一層轉移程序轉移至層堆疊110。替代地，一或多個單層之石墨烯之石墨烯片可藉由剝蝕形成，其中一石墨烯片可轉移至層堆疊110。
替代地，通道層112可由一或多個單層之一TMDC材料(單晶或多晶)形成。一TMDC單層(亦指定為MX2)由夾置於兩層X原子之間一層M原子組成，其中M指定一過渡金屬元素且X指定一硫族元素。一TMDC層可由堆疊於彼此之上之若干TMDC單層形成。通道層112可由一或多個單層之WS2、WSe2、MoS2、MoSe2、WTe2或MoTe2之形成。可採用用於使一TMDC通道層112形成於鐵電層104上之技術方法之任何狀態。例如，TMDC片可藉由剝蝕形成，其中一TMDC片可轉移至層堆疊110。用於產生TMDC層之其他替代方案包含ALD、化學氣相沈積(CVD)、物理氣相沈積(PVD)、脈衝雷射沈積(PLD)及固態源分子束磊晶(MBE)。
源極接點114及汲極接點116可形成為在通道層112中之一通道區域之相對側處與通道層112接觸。接點114及116可由一導電材料形成。導電材料可為一金屬(例如Ti、TiN、TiAl或WN)。然而，W、Co、Ni、Ru或其等之合金亦係可能接點材料以及矽化物及鍺化物。接點材料可藉由ALD、CVD或PVD形成。一遮罩層可經形成以覆蓋通道層112且在接點材料之沈積之前，在接點114、116之期望位置處打開。在已形成接點之後，可移除遮罩層。
圖6展示包含具有一垂直層堆疊組態或由下而上組態之一層堆疊210之一FeFET裝置200。裝置200包含一層堆疊210，其已依參考圖1至圖5提出之方式形成。
層堆疊210包含呈一閘極電極之形式之一閘極結構102。閘極結構210配置於一基板220(諸如一半導體基板，例如一Si基板、一Ge基板、一SiGe基板、一絕緣體上覆矽基板(SOI))上。(例如)一習知介電材料之一絕緣層222形成於基板220之一主表面上以使閘極結構102與基板220電絕緣。閘極結構102之一上表面(鐵電層104形成於其上)沿平行於基板220之主表面之一(水平)平面延伸。一鐵電層104及一通道層112形成於閘極結構102上，如在一垂直方向上所見(即，垂直於基板220之主表面)。在由通道層112替換之前，一應力源層(對應於應力源層108)亦已形成於閘極結構102上及鐵電層104上。
一源極電極114及一汲極電極116形成為與通道層112電接觸。一遮罩層可形成於層堆疊210及基板220上。開口可界定於遮罩層中(例如在一微影程序中)以曝露其中待形成源極電極114及汲極電極116之通道層112之區域。隨後，一導電材料可沈積於開口中。經沈積之導電材料 可為(例如)連同圖1至圖5之閘極結構102所討論之一金屬。在藉由化學機械拋光(CMP)及/或回蝕而移除過載導電材料之後，可移除遮罩層，將源極電極114及汲極電極116留在通道層112上。
一導電互連結構224形成於絕緣層222上以經由可存取於鄰近於層堆疊210之一區域中之一接點提供對閘極結構102之電存取。互連結構224可藉由在形成閘極結構102之前在(例如)一金屬鑲嵌程序中沈積一導電材料(諸如Al、Cu或W)而形成。
圖7a展示具有一橫向堆疊組態之一層堆疊310。層堆疊310包含形成於自一基板320延伸或突出之一垂直半導體結構321之一側壁表面321a上之一閘極結構102。結構321可(例如)呈一半導體散熱片之形式。閘極結構102呈現背離側壁表面321a且沿平行於半導體結構321之側壁表面321a之一(垂直)平面延伸之一主表面。一鐵電層104形成於閘極結構102之主表面上。一應力源層108形成於鐵電層104上。因此，如沿側壁表面321a之一法線方向查看，應力源層108橫向形成於鐵電層104外部。層堆疊310之層可依序沈積作為覆蓋基板320及結構321之各自保形層。在沈積之後，沈積於水平表面上之層部分可藉由垂直蝕刻移除，藉此達到圖7a中所展示之組態，其中層堆疊形成於結構321之側壁表面上。
在圖7b中，應力源層108已(隨後執行如上文所描述之一熱處理H)由一2D材料通道層112替換。通道層112可沈積為覆蓋基板320、鐵電層104及結構321之一保形層(例如由ALD)。在沈積之後，沈積於水平表面上(諸如結構321之一頂面上)之通道層部分可藉由垂直蝕刻移除，同時視情況遮蔽所保留之通道層112之部分。此後，源極電極314及汲極電極316可形成為與通道層112電接觸。源極電極314及汲極電極316可依對應 於圖6中所展示之源極電極114及汲極電極116之一方式形成。
在上文中，已主要參考有限數目個實例描述本發明概念。然而，如熟習技術者所易於瞭解，除上文所揭示之實例之外之其他實例在如由隨附申請專利範圍界定之本發明概念之範疇內同樣可行。
100‧‧‧鐵電場效電晶體(FeFET)裝置
102‧‧‧閘極結構
104‧‧‧鐵電層
106‧‧‧高K值介電層
110‧‧‧層堆疊
112‧‧‧二維(2D)材料通道層
114‧‧‧源極接點
116‧‧‧汲極接點

Claims (12)

  1. 一種用於形成一鐵電場效電晶體(FeFET)裝置之方法，該方法包括：使一層堆疊形成於一閘極結構上，該層堆疊包含一鐵電層及一犧牲應力源層，其中該犧牲應力源層在形成該鐵電層之後形成，使該層堆疊經受一熱處理以引起該鐵電層中之一相變，在該熱處理之後，由一二維材料通道層替換該犧牲應力源層，及形成與該二維材料通道層接觸之一源極接點及一汲極接點。
  2. 如請求項1之方法，其中該犧牲應力源層包含一金屬層。
  3. 如請求項2之方法，其中該金屬層包含氮化鈦、氮化鉭或氮化鉭鈦。
  4. 如請求項1至3中任一項之方法，其中該鐵電層包含氧化鉿、氧化鋯、鈦酸鉿或氧化鋯鉿。
  5. 如請求項1至3中任一項之方法，其中該二維材料通道層包含一或多個單層之一過渡金屬二硫屬化物材料或一或多個單層之石墨烯。
  6. 如請求項5之方法，其中該二維材料通道層包含一或多個單層之WS2、WSe2、MoS2、MoSe2、WTe2或MoTe2。
  7. 如請求項1至3中任一項之方法，其中熱處理包括將該鐵電層加熱至 在300℃至1200℃之一範圍內之一溫度。
  8. 如請求項1至3中任一項之方法，其中該閘極結構配置於一基板上且呈現沿平行於該基板之一主表面之一平面延伸之一上表面，且其中該層堆疊形成於該上表面上。
  9. 如請求項1至3中任一項之方法，其中該閘極結構配置於一基板上，該基板具有自該基板垂直延伸之一半導體結構，該半導體結構具有該閘極結構配置於其上之一側壁表面。
  10. 如請求項1至3中任一項之方法，其中該閘極結構係一虛設閘極結構，且該方法進一步包括使該虛設閘極結構由一替換閘極結構進行替換。
  11. 如請求項1至3中任一項之方法，其中該閘極結構係一閘極電極。
  12. 如請求項1至3中任一項之方法，其中該層堆疊進一步包含在形成該鐵電層之後形成之一高K值介電層。
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