TW201909253A - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

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TW201909253A
TW201909253A TW106123732A TW106123732A TW201909253A TW 201909253 A TW201909253 A TW 201909253A TW 106123732 A TW106123732 A TW 106123732A TW 106123732 A TW106123732 A TW 106123732A TW 201909253 A TW201909253 A TW 201909253A
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semiconductor device
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蔡世鴻
謝柏光
曾于庭
郭承平
曾冠豪
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聯華電子股份有限公司
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Priority to US15/678,125 priority patent/US10211313B2/en
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Abstract

本發明揭露一種製作半導體元件的方法。首先形成一閘極結構於一基底上，然後形成一層間介電層於閘極結構周圍，去除閘極結構以形成一第一凹槽，形成一鐵電層於第一凹槽內，形成一壓縮應力層於鐵電層上，進行一熱處理製程，去除該壓縮應力層，以及形成一功函數金屬層於第一凹槽內。

Description

半導體元件及其製作方法
本發明是關於一種半導體元件，尤指一種包含鐵電(ferroelectric, FE)材料的半導體元件。
半導體元件，係指可藉由使用半導體特性而作用之任何元件。舉例來說，光電元件(electro-optical device)、半導體電路(semiconductor circuit)、及電子元件(electronic device)等皆可以是半導體裝置。是以，半導體元件常被使用於各種電子應用中，例如個人電腦、手機、數位相機、及其他電子裝置等。
一般來說，半導體元件之製造通常為依序沉積絕緣層或介電層、導電層、及半導體層於半導體基底上，並以微影製程圖案化各材料層並於其上形成電路元件。隨著半導體材料與設計技術的進步，係使電路越來越小也越來越複雜，且單位面積上可互連的元件數量越來越多。然而，當最小元件的尺寸縮小時，許多挑戰隨之而生。當特徵變得更靠近時，漏電流變得更加顯著；信號變得更容易跨越(crossover)；而功率的使用變得更加重要。一般而言，當金屬氧化半導體場效電晶體(metal-oxide-semiconductor field effect transistor，MOS FET)元件的閘極電壓小於臨界電壓時，其汲極電流理論上應為零。然而，在實際的應用上，此汲極電流並不為零，而這個不為零的電流即為次臨界電流(subthreshold current)，並且因次臨界電流的存在，MOS FET元件並不能處於完全截止的狀態。熟習該項技藝之人士應知，次臨界電流與閘極電壓具有一線性關係，即次臨界擺幅(subthreshold swing，SS)。次臨界擺幅小時，表示閘極對於次臨界電流具有較大的控制能力、次臨界電流相對較小、而元件在操作時會有較小的漏電流存在。然而，根據現有半導體元件的物理極限，目前次臨界擺幅僅能降低至60 mV/dec。是以，如何能進一步降低次臨界擺幅仍然是業界致力之目標。
本發明一實施例揭露一種製作半導體元件的方法。首先形成一閘極結構於一基底上，然後形成一層間介電層於閘極結構周圍，去除閘極結構以形成一第一凹槽，形成一鐵電層於第一凹槽內，形成一壓縮應力層於鐵電層上，進行一熱處理製程，去除該壓縮應力層，以及形成一功函數金屬層於第一凹槽內。
本發明另一實施例揭露一種半導體元件，其主要包含：一金屬閘極設於一基底上；一多晶矽層設於金屬閘極上；一硬遮罩設於多晶矽層上以及一源極/汲極區域設於金屬閘極兩側。
請參照第1圖至第9圖，第1圖至第9圖為本發明較佳實施例製作一半導體元件之方法示意圖。如第1圖所示，首先提供一基底12，例如一矽基底或矽覆絕緣(SOI)基板，其上可定義有一電晶體區，例如一PMOS電晶體區或一NMOS電晶體區。基底12上具有至少一鰭狀結構14及一絕緣層(圖未示)，其中鰭狀結構14之底部係被絕緣層，例如氧化矽所包覆而形成淺溝隔離。需注意的是，本實施例雖以製作非平面型場效電晶體(non-planar)例如鰭狀結構場效電晶體為例，但不侷限於此，本發明又可應用至一般平面型(planar)場效電晶體，此實施例也屬本發明所涵蓋的範圍。
依據本發明一實施例，鰭狀結構14較佳透過側壁圖案轉移(sidewall image transfer, SIT)技術製得，其程序大致包括：提供一佈局圖案至電腦系統，並經過適當地運算以將相對應之圖案定義於光罩中。後續可透過光微影及蝕刻製程，以形成多個等距且等寬之圖案化犧牲層於基底上，使其個別外觀呈現條狀。之後依序施行沉積及蝕刻製程，以於圖案化犧牲層之各側壁形成側壁子。繼以去除圖案化犧牲層，並在側壁子的覆蓋下施行蝕刻製程，使得側壁子所構成之圖案被轉移至基底內，再伴隨鰭狀結構切割製程(fin cut)而獲得所需的圖案化結構，例如條狀圖案化鰭狀結構。
除此之外，鰭狀結構14之形成方式又可包含先形成一圖案化遮罩(圖未示)於基底12上，再經過一蝕刻製程，將圖案化遮罩之圖案轉移至基底12中以形成鰭狀結構。另外，鰭狀結構之形成方式也可以先形成一圖案化硬遮罩層(圖未示)於基底12上，並利用磊晶製程於暴露出於圖案化硬遮罩層之基底12上成長出例如包含矽鍺的半導體層，而此半導體層即可作為相對應的鰭狀結構。這些形成鰭狀結構的實施例均屬本發明所涵蓋的範圍。
接著可於基底12上形成至少一閘極結構16或虛置閘極。在本實施例中，閘極結構16之製作方式可依據製程需求以先閘極(gate first)製程、後閘極(gate last)製程之先高介電常數介電層(high-k first)製程以及後閘極製程之後高介電常數介電層(high-k last)製程等方式製作完成。以本實施例之後高介電常數介電層製程為例，可先依序形成一閘極介電層或介質層、一由多晶矽所構成之閘極材料層以及一選擇性硬遮罩於基底12上，並利用一圖案化光阻(圖未示)當作遮罩進行一圖案轉移製程，以單次蝕刻或逐次蝕刻步驟，去除部分閘極材料層與部分閘極介電層，然後剝除圖案化光阻，以於基底12上形成由圖案化之閘極介電層18與圖案化之閘極材料層20所構成的閘極結構16。
然後在閘極結構16側壁形成至少一側壁子22，接著於側壁子22兩側的鰭狀結構14以及/或基底12中形成一源極/汲極區域24及/或磊晶層(圖未示)，並選擇性於源極/汲極區域24及/或磊晶層的表面形成一金屬矽化物(圖未示)。在本實施例中，側壁子22可為單一側壁子或複合式側壁子，例如可細部包含一偏位側壁子26以及一主側壁子28。其中偏位側壁子26與主側壁子28可包含相同或不同材料，且兩者均可選自由氧化矽、氮化矽、氮氧化矽以及氮碳化矽所構成的群組。源極/汲極區域24可依據所置備電晶體的導電型式而包含不同摻質，例如可包含P型摻質或N型摻質。
接著如第2圖所示，先形成一接觸洞蝕刻停止層30於基底12表面與閘極結構16上，再形成一層間介電層32於接觸洞蝕刻停止層30上。然後進行一平坦化製程，例如利用化學機械研磨(chemical mechanical polishing, CMP)去除部分層間介電層32與部分接觸洞蝕刻停止層30並暴露出由多晶矽材料所構成的閘極材料層20，使閘極材料層20上表面與層間介電層32上表面齊平。
隨後進行一金屬閘極置換製程將閘極結構16轉換為金屬閘極。舉例來說，可先進行一選擇性之乾蝕刻或濕蝕刻製程，例如利用氨水(ammonium hydroxide, NH4 OH)或氫氧化四甲銨(Tetramethylammonium Hydroxide, TMAH)等蝕刻溶液來去除閘極結構16中的閘極材料層20甚至閘極介電層18，以於層間介電層32中形成凹槽34並暴露出鰭狀結構14表面。
然後如第3圖所示，可先選擇性形成另一介質層36或閘極介電層於凹槽34底部，然後形成一鐵電層38於凹槽34內，形成一壓縮應力層40於鐵電層38上，並進行一熱處理製程，例如一快速升溫退火(rapid thermal anneal, RTA)製程或金屬後退火(post metal anneal, PMA)製程，使鐵電層38產生具有負電容效應的結晶型態。一般而言，在初始階段所沉積的鐵電層38較佳具有三種晶格型態或晶相(phase)，包括斜方晶相(orthohombic phase)、正方晶相(tetragonal phase)以及單協晶相(monoclinic phase)，其中斜方晶相為主要具有鐵電效應的型態，正方晶相為具有反鐵電效應的型態，而單協晶相則為不具有鐵電效應也不具有反鐵電效應的型態。在本實施例中，若依據上述製程於沉積鐵電層38後覆蓋壓縮應力層40並搭配進行熱處理製程即可使鐵電層38的晶格中產生較多的斜方晶相，進而使鐵電層38具有負電容的效果。
另外需注意的是，本實施例雖在鐵電層38形成前先形成一介質層36於凹槽34內的鰭狀結構14表面，但不侷限於此，又可依據製程需求省略形成介質層36的步驟，例如於凹槽34形成後直接形成鐵電層38於凹槽34內並使鐵電層38直接接觸鰭狀結構14表面，之後再形成壓縮應力層40於鐵電層38上並進行熱處理製程，此實施例也屬本發明所涵蓋的範圍。
在本實施例中，鐵電層38較佳包含二氧化鋯鉿(HfZrO2 )，但依據本發明其他實施例又可包含一選自於由下列成分組成之群組中的材料：鋯鈦酸鉛(lead zirconate titanate，PbZrTiO3 ，PZT)、鋯鈦酸鉛鑭(lead lanthanum zirconate titanate，PbLa(TiZr)O3 ，PLZT)、鉭酸鉍鍶(strontium bismuth tantalate，SrBiTa2 O9 ，SBT)、鈦酸鑭鉍 (bismuth lanthanum titanate，(BiLa)4 Ti3 O12 ，BLT)及鈦酸鍶鋇(barium strontium titanate，BaSrTiO3 ，BST)。壓縮應力層40則較佳包含一具有壓縮應力之導電層，例如可包含氮化鈦之材料，但不侷限於此。
如第4圖所示，接著利用蝕刻製程完全去除壓縮應力層40暴露出下面的鐵電層38，再選擇性形成一底部阻隔金屬(bottom barrier metal, BBM)層42於鐵電層表面。在本實施例中，底部阻隔金屬層42較佳包含不具有應力的導電層，其可包含氮化鈦(TiN)或氮化鉭(TaN)，但不侷限於此。
隨後如第5圖所示，依序形成一功函數金屬層44以及一低阻抗金屬層46於凹槽34內的底部阻隔金屬層42上並填滿凹槽34，再進行一平坦化製程，例如以CMP去除部分低阻抗金屬層46、部分功函數金屬層44、部分底部阻隔金屬層42以及部分鐵電層38以形成金屬閘極48。以本實施例利用後高介電常數介電層製程所製作的閘極結構或金屬閘極48為例，金屬閘極48較佳包含一介質層36或閘極介電層、一U型鐵電層38、一U型底部阻隔金屬層42、一U型功函數金屬層44以及低阻抗金屬層46。值得注意的是，本實施例雖於形成功函數金屬層44之前先形成底部阻隔金屬層42於鐵電層38表面，但不侷限於此，本發明一實施例又可選擇省略形成底部阻隔金屬層42的步驟，亦即於第4圖去除壓縮應力層40後直接形成功函數金屬層44於鐵電層38表面，此實施例也屬本發明所涵蓋的範圍。
在本實施例中，功函數金屬層44較佳用以調整形成金屬閘極之功函數，使其適用於N型電晶體(NMOS)或P型電晶體(PMOS)。若電晶體為N型電晶體，功函數金屬層44可選用功函數為3.9電子伏特(eV)～4.3 eV的金屬材料，如鋁化鈦(TiAl)、鋁化鋯(ZrAl)、鋁化鎢(WAl)、鋁化鉭(TaAl)、鋁化鉿(HfAl)或TiAlC (碳化鈦鋁)等，但不以此為限；若電晶體為P型電晶體，功函數金屬層44可選用功函數為4.8 eV～5.2 eV的金屬材料，如氮化鈦(TiN)、氮化鉭(TaN)或碳化鉭(TaC)等，但不以此為限。功函數金屬層44與低阻抗金屬層46之間可包含另一阻障層(圖未示)，其中阻障層的材料可包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等材料。低阻抗金屬層46則可選自銅(Cu)、鋁(Al)、鎢(W)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等低電阻材料或其組合。至此即完成本發明一實施例之半導體元件的製作。
迨完成金屬閘極之後，依據本發明一實施例，如第6圖所示，可在不使用圖案化遮罩或使用圖案化遮罩的情況下進行一蝕刻製程去除部分金屬閘極48，使剩餘的金屬閘極48頂部略低於層間介電層32上表面以形成另一凹槽50。
如第7圖所示，之後再形成一多晶矽層52填滿凹槽50並設於該層間介電層32上。在本實施例中，多晶矽層較佳為一包含N型摻質之N型多晶矽層，但不侷限於此。
如第8圖所示，接著進行一平坦化製程，例如利用CMP去除部分多晶矽層52表面，使剩餘的多晶矽層52表面約略切齊層間介電層32上表面。隨後再進行一蝕刻製程，例如利用乾蝕刻去除部分多晶矽層52，使剩餘的多晶矽層52上表面略低於層間介電層32上表面以形成另一凹槽54。
需注意的是，本實施例在去除部分多晶矽層52的時候可選擇在形成圖案化遮罩或不形成圖案化遮罩的情況下來去除部分多晶矽層52，其中剩餘的多晶矽層52可依據蝕刻參數的調整以及/或圖案化遮罩所設置的位置呈現U型剖面或一字型剖面結構。以本實施例中多晶矽層52具有U型剖面為例，多晶矽層52的U字型頂部可如圖中所示略低於周圍層間介電層32上表面，或可切齊層間介電層32上表面，這兩個態樣均屬本發明所涵蓋的範圍。
如第9圖所示，然後形成一硬遮罩56於多晶矽層52與層間介電層32上，再進行一平坦化製程，例如利用CMP去除部分硬遮罩56，使剩餘的硬遮罩56上表面約略切齊層間介電層32上表面。在本實施例中，硬遮罩56較佳包含氮化矽，但又可依據製程需求選用其他介電材料，例如氧化矽、氮氧化矽、氮碳化矽或其組合。之後可依據製程需求進行接觸插塞製程，例如可於層間介電層32中形成接觸插塞(圖未示)電連接側壁子22兩側的源極/汲極區域24。至此即完成本發明又一實施例之半導體元件的製作。
請再參照第10圖，第10圖為本發明一實施例之半導體元件之結構示意圖。如第10圖所示，本發明可於第3圖形成鐵電層38之前先依序形成一高介電常數介電層58以及一底部阻隔金屬層60於凹槽34內，然後形成鐵電層38於底部阻隔金屬層60上，形成一壓縮應力層(圖未示)於鐵電層38上，並進行一熱處理製程，例如一快速升溫退火(rapid thermal anneal, RTA)製程或金屬後退火(post metal anneal, PMA)製程，使鐵電層38產生具有負電容效應的結晶型態。此外，依據本發明一實施例，又可於形成高介電常數介電層58後省略形成底部阻隔金屬層60的步驟，直接將鐵電層38設置並接觸高介電常數介電層60表面，此實施例也屬本發明所涵蓋的範圍。
接著進行前述第4圖至第5圖的製程，例如先利用蝕刻製程完全去除壓縮應力層暴露出下面的鐵電層38，然後選擇性形成一底部阻隔金屬(bottom barrier metal, BBM)層42於鐵電層38上，依序形成一功函數金屬層44以及一低阻抗金屬層46於凹槽34內的底部阻隔金屬層42上並填滿凹槽34，再進行一平坦化製程，例如以CMP去除部分低阻抗金屬層46、部分功函數金屬層44、部分底部阻隔金屬層42、部分鐵電層38、部分底部阻隔金屬層60以及部分高介電常數介電層58以形成金屬閘極48。
如同前述實施例，本實施例雖於形成功函數金屬層44之前先形成底部阻隔金屬層42於鐵電層38表面，但不侷限於此，本發明一實施例又可選擇省略形成底部阻隔金屬層42的步驟，亦即於去除壓縮應力層40後直接形成功函數金屬層44於鐵電層38表面，此實施例也屬本發明所涵蓋的範圍。此外依據本發明又一實施例，功函數金屬層44與低阻抗金屬層46之間可包含另一阻障層(圖未示)，其中阻障層的材料可包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等材料。
在本實施例中，高介電常數介電層58包含介電常數大於4的介電材料，例如選自氧化鉿(hafnium oxide，HfO2 )、矽酸鉿氧化合物(hafnium silicon oxide, HfSiO4 )、矽酸鉿氮氧化合物(hafnium silicon oxynitride, HfSiON)、氧化鋁(aluminum oxide, Al2 O3 )、氧化鑭(lanthanum oxide, La2 O3 )、氧化鉭(tantalum oxide, Ta2 O5 )、氧化釔(yttrium oxide, Y2 O3 )、氧化鋯(zirconium oxide, ZrO2 )、鈦酸鍶（strontium titanate oxide, SrTiO3 ）、矽酸鋯氧化合物(zirconium silicon oxide, ZrSiO4 )、鋯酸鉿(hafnium zirconium oxide, HfZrO4 )、鍶鉍鉭氧化物(strontium bismuth tantalate, SrBi2 Ta2 O9 , SBT)、鋯鈦酸鉛(lead zirconate titanate, PbZrx Ti1-x O3 , PZT)、鈦酸鋇鍶(barium strontium titanate, Bax Sr1-x TiO3 , BST)、或其組合所組成之群組。底部阻隔金屬層60與底部阻隔金屬層42可包含相同或不同材料，其中底部阻隔金屬層60與底部阻隔金屬層42均較佳包含不具有應力的導電材料，例如可包含氮化鈦(TiN)或氮化鉭(TaN)，但不侷限於此。
請再參照第11圖，第11圖為本發明一實施例之半導體元件之結構示意圖。如第11圖所示，本發明可結合第10圖的結構與第6圖至第9的製程，例如可先去除部分金屬閘極48形成凹槽、形成多晶矽層52於凹槽內以及層間介電層32上，利用平坦化製程並搭配蝕刻去除部分多晶矽層52，最後再形成硬遮罩56於多晶矽層52上。如同前述實施例，多晶矽層52可依據製程或產品需求具有U型剖面或一字型剖面，且當多晶矽層52具有U型剖面時，多晶矽層52的U字型頂部可略低於周圍層間介電層32上表面，或可切齊層間介電層32上表面，這些態樣均屬本發明所涵蓋的範圍。
綜上所述，本發明主要在金屬閘極製程掏空虛置閘極且形成凹槽後依序形成鐵電層與壓縮應力層於凹槽內，再利用熱處理製程使鐵電層產生具有負電容效應的結晶型態，除了可藉此有效地改善次臨界擺幅又可降低漏電流並節省不必要的功率消耗。此外，本發明進行上述熱處理製程使鐵電層產生較多具有負電容效應的結晶型態後又再利用蝕刻完全去除壓縮應力層，如此即可替後續所填入的材料層，包括例如功函數金屬層與低阻抗金屬層等提供更多的填洞空間。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
12‧‧‧基底
14‧‧‧鰭狀結構
16‧‧‧閘極結構
18‧‧‧閘極介電層
20‧‧‧閘極材料層
22‧‧‧側壁子
24‧‧‧源極/汲極區域
26‧‧‧偏位側壁子
28‧‧‧主側壁子
30‧‧‧接觸洞蝕刻停止層
32‧‧‧層間介電層
34‧‧‧凹槽
36‧‧‧介質層
38‧‧‧鐵電層
40‧‧‧壓縮應力層
42‧‧‧底部阻隔金屬層
44‧‧‧功函數金屬層
46‧‧‧低阻抗金屬層
48‧‧‧金屬閘極
50‧‧‧凹槽
52‧‧‧多晶矽層
54‧‧‧凹槽
56‧‧‧硬遮罩
58‧‧‧高介電常數介電層
60‧‧‧底部阻隔金屬層
第1圖至第9圖為本發明較佳實施例製作一半導體元件之方法示意圖。 第10圖為本發明一實施例之半導體元件之結構示意圖。 第11圖為本發明一實施例之半導體元件之結構示意圖。

Claims (20)

  1. 一種製作半導體元件的方法，包含： 形成一閘極結構於一基底上； 形成一層間介電層於該閘極結構周圍； 去除該閘極結構以形成一第一凹槽； 形成一鐵電層於該第一凹槽內； 形成一壓縮應力層於該鐵電層上； 進行一熱處理製程； 去除該壓縮應力層；以及 形成一功函數金屬層於該第一凹槽內。
  2. 如申請專利範圍第1項所述之方法，另包含： 形成一鰭狀結構於該基底上；以及 形成該閘極結構於該鰭狀結構上，其中該鰭狀結構包含鍺化矽。
  3. 如申請專利範圍第1項所述之方法，另包含： 形成一低阻抗金屬層於該功函數金屬層上；以及 進行一平坦化製程以形成一金屬閘極。
  4. 如申請專利範圍第3項所述之方法，另包含： 去除部分該金屬閘極以形成一第二凹槽；以及 形成一多晶矽層於該第二凹槽內以及該層間介電層上。
  5. 如申請專利範圍第4項所述之方法，另包含： 去除部分該多晶矽層以形成一第三凹槽；以及 形成一硬遮罩於該多晶矽層上。
  6. 如申請專利範圍第4項所述之方法，其中該多晶矽層包含一N型多晶矽層。
  7. 如申請專利範圍第4項所述之方法，其中該多晶矽層係為U型。
  8. 如申請專利範圍第1項所述之方法，另包含： 形成一高介電常數介電層於該第一凹槽內；以及 於形成該鐵電層之前形成一底部阻隔金屬層於該高介電常數介電層上。
  9. 如申請專利範圍第1項所述之方法，其中該鐵電層包含二氧化鋯鉿(HfZrO2 )。
  10. 如申請專利範圍第1項所述之方法，其中該壓縮應力層包含氮化鈦。
  11. 一種半導體元件，包含： 一金屬閘極設於一基底上； 一多晶矽層設於該金屬閘極上； 一硬遮罩設於該多晶矽層上；以及 一源極/汲極區域設於該金屬閘極兩側。
  12. 如申請專利範圍第11項所述之半導體元件，另包含： 一鰭狀結構設於該基底上；以及 該金屬閘極設於該鰭狀結構上，其中該鰭狀結構包含鍺化矽。
  13. 如申請專利範圍第11項所述之半導體元件，其中該金屬閘極包含： 一鐵電層設於該基底上； 一功函數金屬層設於該鐵電層上；以及 一低阻抗金屬層設於該功函數金屬層上。
  14. 如申請專利範圍第13項所述之半導體元件，其中該鐵電層包含二氧化鋯鉿(HfZrO2 )。
  15. 如申請專利範圍第13項所述之半導體元件，其中該鐵電層以及該功函數金屬層係為U型。
  16. 如申請專利範圍第13項所述之半導體元件，另包含： 一高介電常數介電層設於該第一凹槽內；以及 一底部阻隔金屬層設於該高介電常數介電層及該鐵電層之間。
  17. 如申請專利範圍第11項所述之半導體元件，其中該多晶矽層包含一N型多晶矽層。
  18. 如申請專利範圍第11項所述之半導體元件，其中該多晶矽層係為U型。
  19. 如申請專利範圍第11項所述之半導體元件，另包含一層間介電層環繞該金屬閘極，其中該層間介電層上表面切齊該硬遮罩上表面。
  20. 如申請專利範圍第11項所述之半導體元件，其中該硬遮罩包含氮化矽。
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