TWI772520B - 半導體製程用片材及半導體封裝之製造方法 - Google Patents

半導體製程用片材及半導體封裝之製造方法 Download PDF

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Publication number
TWI772520B
TWI772520B TW107132378A TW107132378A TWI772520B TW I772520 B TWI772520 B TW I772520B TW 107132378 A TW107132378 A TW 107132378A TW 107132378 A TW107132378 A TW 107132378A TW I772520 B TWI772520 B TW I772520B
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Taiwan
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semiconductor
adhesive
sheet
mentioned
layer
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TW107132378A
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English (en)
Chinese (zh)
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TW201923995A (zh
Inventor
志賀豪士
佐藤慧
高本尚英
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日商日東電工股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B27/00—Layered products comprising a layer of synthetic resin
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J7/00—Adhesives in the form of films or foils
    • C09J7/30—Adhesives in the form of films or foils characterised by the adhesive composition
    • C09J7/38—Pressure-sensitive adhesives [PSA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/214—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Adhesive Tapes (AREA)
  • Dicing (AREA)
  • Laminated Bodies (AREA)
  • Die Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Control And Other Processes For Unpacking Of Materials (AREA)
TW107132378A 2017-11-16 2018-09-14 半導體製程用片材及半導體封裝之製造方法 TWI772520B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017-220856 2017-11-16
JP2017220856A JP7095978B2 (ja) 2017-11-16 2017-11-16 半導体プロセスシートおよび半導体パッケージ製造方法

Publications (2)

Publication Number Publication Date
TW201923995A TW201923995A (zh) 2019-06-16
TWI772520B true TWI772520B (zh) 2022-08-01

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TW107132378A TWI772520B (zh) 2017-11-16 2018-09-14 半導體製程用片材及半導體封裝之製造方法

Country Status (5)

Country Link
JP (1) JP7095978B2 (ja)
KR (1) KR102600254B1 (ja)
CN (1) CN111344845A (ja)
TW (1) TWI772520B (ja)
WO (1) WO2019097819A1 (ja)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11538787B2 (en) * 2020-10-30 2022-12-27 Advanced Semiconductor Engineering, Inc. Method and system for manufacturing a semiconductor package structure
JP7447035B2 (ja) * 2021-02-25 2024-03-11 日東電工株式会社 光半導体素子封止用シート
JP2022170157A (ja) 2021-04-28 2022-11-10 日東電工株式会社 熱硬化性樹脂組成物、熱硬化性シート、及び、半導体チップ被覆部材

Citations (4)

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JP2005028734A (ja) * 2003-07-11 2005-02-03 Nitto Denko Corp 積層シート
TW201441354A (zh) * 2013-03-27 2014-11-01 Furukawa Electric Co Ltd 有機電子裝置用元件密封用樹脂組成物、有機電子裝置用元件密封用樹脂薄片、有機電致發光元件、及畫面顯示裝置
TW201531549A (zh) * 2013-10-30 2015-08-16 Lintec Corp 半導體接合用接著片及半導體裝置的製造方法
JP2017092335A (ja) * 2015-11-13 2017-05-25 日東電工株式会社 半導体パッケージの製造方法

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JP2001313350A (ja) * 2000-04-28 2001-11-09 Sony Corp チップ状電子部品及びその製造方法、並びにその製造に用いる疑似ウエーハ及びその製造方法
JP4155999B2 (ja) * 2006-06-02 2008-09-24 株式会社ソニー・コンピュータエンタテインメント 半導体装置および半導体装置の製造方法
US8258624B2 (en) 2007-08-10 2012-09-04 Intel Mobile Communications GmbH Method for fabricating a semiconductor and semiconductor package
JP5224111B2 (ja) 2008-08-29 2013-07-03 日立化成株式会社 半導体ウェハ加工用接着フィルム
US20110198762A1 (en) 2010-02-16 2011-08-18 Deca Technologies Inc. Panelized packaging with transferred dielectric
JP2012227441A (ja) 2011-04-21 2012-11-15 Sumitomo Bakelite Co Ltd 半導体装置の製造方法および半導体装置
JP2013074184A (ja) * 2011-09-28 2013-04-22 Nitto Denko Corp 半導体装置の製造方法
JP5837381B2 (ja) * 2011-09-28 2015-12-24 日東電工株式会社 半導体装置の製造方法
CN103137501A (zh) * 2011-11-28 2013-06-05 日东电工株式会社 半导体装置的制造方法
JP2013157470A (ja) 2012-01-30 2013-08-15 Sekisui Chem Co Ltd 半導体部品の製造方法
KR20130103950A (ko) * 2012-03-12 2013-09-25 닛토덴코 가부시키가이샤 반도체 장치 제조용 내열성 점착 테이프 및 그 테이프를 사용한 반도체 장치의 제조 방법
KR20130103947A (ko) * 2012-03-12 2013-09-25 닛토덴코 가부시키가이샤 반도체 장치 제조용 내열성 점착 테이프 및 그 테이프를 사용한 반도체 장치의 제조 방법
JP6167612B2 (ja) 2013-03-29 2017-07-26 住友ベークライト株式会社 接着シートおよび電子部品
KR102344987B1 (ko) * 2013-12-24 2021-12-30 닛토덴코 가부시키가이샤 다이싱·다이 본드 필름, 반도체 장치의 제조 방법 및 반도체 장치
JP2015126124A (ja) 2013-12-26 2015-07-06 日東電工株式会社 半導体パッケージの製造方法
JP6530213B2 (ja) * 2014-07-22 2019-06-12 日東電工株式会社 シート状樹脂組成物、裏面研削用テープ一体型シート状樹脂組成物、及び、半導体装置の製造方法
US20160035667A1 (en) 2014-07-30 2016-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of Packaging Semiconductor Devices and Packaged Semiconductor Devices
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JP2017088782A (ja) 2015-11-13 2017-05-25 日東電工株式会社 積層体および合同体・組み合わせの回収方法・半導体装置の製造方法

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JP2005028734A (ja) * 2003-07-11 2005-02-03 Nitto Denko Corp 積層シート
TW201441354A (zh) * 2013-03-27 2014-11-01 Furukawa Electric Co Ltd 有機電子裝置用元件密封用樹脂組成物、有機電子裝置用元件密封用樹脂薄片、有機電致發光元件、及畫面顯示裝置
TW201531549A (zh) * 2013-10-30 2015-08-16 Lintec Corp 半導體接合用接著片及半導體裝置的製造方法
JP2017092335A (ja) * 2015-11-13 2017-05-25 日東電工株式会社 半導体パッケージの製造方法

Also Published As

Publication number Publication date
WO2019097819A1 (ja) 2019-05-23
JP7095978B2 (ja) 2022-07-05
TW201923995A (zh) 2019-06-16
JP2019091845A (ja) 2019-06-13
KR102600254B1 (ko) 2023-11-08
KR20200085842A (ko) 2020-07-15
CN111344845A (zh) 2020-06-26

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