TWI744358B - 三維半導體裝置及其製造方法 - Google Patents
三維半導體裝置及其製造方法 Download PDFInfo
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- TWI744358B TWI744358B TW106124085A TW106124085A TWI744358B TW I744358 B TWI744358 B TW I744358B TW 106124085 A TW106124085 A TW 106124085A TW 106124085 A TW106124085 A TW 106124085A TW I744358 B TWI744358 B TW I744358B
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H10B—ELECTRONIC MEMORY DEVICES
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
- H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
- H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
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- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0193—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices the components including FinFETs
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D88/00—Three-dimensional [3D] integrated devices
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0167—Manufacturing their channels
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201662363973P | 2016-07-19 | 2016-07-19 | |
| US62/363,973 | 2016-07-19 | ||
| US201662372106P | 2016-08-08 | 2016-08-08 | |
| US62/372,106 | 2016-08-08 | ||
| US201662373164P | 2016-08-10 | 2016-08-10 | |
| US62/373,164 | 2016-08-10 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201813055A TW201813055A (zh) | 2018-04-01 |
| TWI744358B true TWI744358B (zh) | 2021-11-01 |
Family
ID=60988140
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW106124085A TWI744358B (zh) | 2016-07-19 | 2017-07-19 | 三維半導體裝置及其製造方法 |
Country Status (6)
| Country | Link |
|---|---|
| US (3) | US10453850B2 (enExample) |
| JP (1) | JP7046049B2 (enExample) |
| KR (1) | KR102228497B1 (enExample) |
| CN (1) | CN109643715B (enExample) |
| TW (1) | TWI744358B (enExample) |
| WO (1) | WO2018017677A1 (enExample) |
Families Citing this family (54)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10453752B2 (en) * | 2017-09-18 | 2019-10-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing a gate-all-around semiconductor device |
| US10833078B2 (en) | 2017-12-04 | 2020-11-10 | Tokyo Electron Limited | Semiconductor apparatus having stacked gates and method of manufacture thereof |
| KR102449389B1 (ko) | 2018-03-19 | 2022-09-29 | 도쿄엘렉트론가부시키가이샤 | 3차원 소자 및 이를 형성하는 방법 |
| US10381273B1 (en) | 2018-04-11 | 2019-08-13 | International Business Machines Corporation | Vertically stacked multi-channel transistor structure |
| JP7351307B2 (ja) | 2018-09-25 | 2023-09-27 | 株式会社ソシオネクスト | 半導体装置及びその製造方法 |
| US10872818B2 (en) | 2018-10-26 | 2020-12-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Buried power rail and method forming same |
| EP3671825A1 (en) | 2018-12-20 | 2020-06-24 | IMEC vzw | Method for connecting a buried interconnect rail and a semiconductor fin in an integrated circuit chip |
| US10985103B2 (en) | 2019-03-01 | 2021-04-20 | Samsung Electronics Co., Ltd | Apparatus and method of forming backside buried conductor in integrated circuit |
| US10818674B2 (en) * | 2019-03-07 | 2020-10-27 | Globalfoundries Inc. | Structures and SRAM bit cells integrating complementary field-effect transistors |
| CN113224079B (zh) * | 2019-03-29 | 2023-07-21 | 长江存储科技有限责任公司 | 3d存储器件及其制造方法 |
| WO2020217400A1 (ja) | 2019-04-25 | 2020-10-29 | 株式会社ソシオネクスト | 半導体装置 |
| WO2020217396A1 (ja) | 2019-04-25 | 2020-10-29 | 株式会社ソシオネクスト | 半導体装置 |
| WO2020230666A1 (ja) * | 2019-05-13 | 2020-11-19 | 株式会社ソシオネクスト | 半導体記憶装置 |
| US11335599B2 (en) * | 2019-05-24 | 2022-05-17 | Tokyo Electron Limited | Self-aligned contacts for 3D logic and memory |
| WO2020255801A1 (ja) | 2019-06-17 | 2020-12-24 | 株式会社ソシオネクスト | 半導体記憶装置 |
| WO2020262248A1 (ja) | 2019-06-28 | 2020-12-30 | 株式会社ソシオネクスト | 半導体記憶装置 |
| US11222964B2 (en) * | 2019-07-08 | 2022-01-11 | Tokyo Electron Limited | Multiple planes of transistors with different transistor architectures to enhance 3D logic and memory circuits |
| KR102705854B1 (ko) * | 2019-07-23 | 2024-09-11 | 에스케이하이닉스 주식회사 | 반도체 소자의 분석 시스템 및 방법 |
| US11488947B2 (en) | 2019-07-29 | 2022-11-01 | Tokyo Electron Limited | Highly regular logic design for efficient 3D integration |
| CN114467175B (zh) | 2019-10-02 | 2025-04-29 | 株式会社索思未来 | 半导体集成电路装置及半导体集成电路装置的制造方法 |
| US11581338B2 (en) | 2019-10-04 | 2023-02-14 | Samsung Electronics Co., Ltd. | Optimization of semiconductor cell of vertical field effect transistor (VFET) |
| CN112614837A (zh) | 2019-10-04 | 2021-04-06 | 三星电子株式会社 | 垂直场效应晶体管半导体单元的优化 |
| JP7640861B2 (ja) * | 2019-10-18 | 2025-03-06 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| US11735525B2 (en) * | 2019-10-21 | 2023-08-22 | Tokyo Electron Limited | Power delivery network for CFET with buried power rails |
| US11495540B2 (en) * | 2019-10-22 | 2022-11-08 | Tokyo Electron Limited | Semiconductor apparatus having stacked devices and method of manufacture thereof |
| US11251080B2 (en) | 2019-12-02 | 2022-02-15 | Tokyo Electron Limited | Method of making 3D circuits with integrated stacked 3D metal lines for high density circuits |
| KR102819048B1 (ko) | 2019-12-31 | 2025-06-10 | 도쿄엘렉트론가부시키가이샤 | 3개의 적층된 디바이스 데크를 갖는 cfet sram 비트 셀 |
| JP7730024B2 (ja) | 2020-01-27 | 2025-08-27 | 株式会社ソシオネクスト | 半導体記憶装置 |
| DE102020125647A1 (de) | 2020-01-31 | 2021-08-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Halbleitervorrichtung mit Komplementärfeldeffekttransistor des Typs mit vergrabenenen Logikleitern, Layout-Diagramm-Herstellungsverfahren und System dafür |
| US11362090B2 (en) * | 2020-01-31 | 2022-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having buried logic conductor type of complementary field effect transistor, method of generating layout diagram and system for same |
| US10971505B1 (en) * | 2020-02-10 | 2021-04-06 | Taiwan Semiconductor Manufacturing Company Limited | Memory devices and methods of manufacturing thereof |
| US11469321B2 (en) * | 2020-02-27 | 2022-10-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device |
| JP2021150501A (ja) * | 2020-03-19 | 2021-09-27 | キオクシア株式会社 | 半導体記憶装置 |
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- 2017-07-19 CN CN201780051097.0A patent/CN109643715B/zh active Active
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| JP7046049B2 (ja) | 2022-04-01 |
| WO2018017677A1 (en) | 2018-01-25 |
| US20190326301A1 (en) | 2019-10-24 |
| US10453850B2 (en) | 2019-10-22 |
| KR20190026018A (ko) | 2019-03-12 |
| CN109643715B (zh) | 2023-05-12 |
| KR102228497B1 (ko) | 2021-03-15 |
| US10964706B2 (en) | 2021-03-30 |
| US20180026042A1 (en) | 2018-01-25 |
| US20180240802A1 (en) | 2018-08-23 |
| JP2019523553A (ja) | 2019-08-22 |
| CN109643715A (zh) | 2019-04-16 |
| TW201813055A (zh) | 2018-04-01 |
| US10573655B2 (en) | 2020-02-25 |
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