JP7046049B2 - 三次元半導体デバイス及び製造方法 - Google Patents

三次元半導体デバイス及び製造方法 Download PDF

Info

Publication number
JP7046049B2
JP7046049B2 JP2019502069A JP2019502069A JP7046049B2 JP 7046049 B2 JP7046049 B2 JP 7046049B2 JP 2019502069 A JP2019502069 A JP 2019502069A JP 2019502069 A JP2019502069 A JP 2019502069A JP 7046049 B2 JP7046049 B2 JP 7046049B2
Authority
JP
Japan
Prior art keywords
electrode
nanowire
fet
semiconductor device
nanowires
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2019502069A
Other languages
English (en)
Japanese (ja)
Other versions
JP2019523553A5 (enExample
JP2019523553A (ja
Inventor
スミス，ジェフリー
デヴィリアーズ，アントン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of JP2019523553A publication Critical patent/JP2019523553A/ja
Publication of JP2019523553A5 publication Critical patent/JP2019523553A5/ja
Application granted granted Critical
Publication of JP7046049B2 publication Critical patent/JP7046049B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0193—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices the components including FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
JP2019502069A 2016-07-19 2017-07-19 三次元半導体デバイス及び製造方法 Active JP7046049B2 (ja)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US201662363973P 2016-07-19 2016-07-19
US62/363,973 2016-07-19
US201662372106P 2016-08-08 2016-08-08
US62/372,106 2016-08-08
US201662373164P 2016-08-10 2016-08-10
US62/373,164 2016-08-10
PCT/US2017/042802 WO2018017677A1 (en) 2016-07-19 2017-07-19 Three-dimensional semiconductor device and method of fabrication

Publications (3)

Publication Number Publication Date
JP2019523553A JP2019523553A (ja) 2019-08-22
JP2019523553A5 JP2019523553A5 (enExample) 2020-06-25
JP7046049B2 true JP7046049B2 (ja) 2022-04-01

Family

ID=60988140

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019502069A Active JP7046049B2 (ja) 2016-07-19 2017-07-19 三次元半導体デバイス及び製造方法

Country Status (6)

Country Link
US (3) US10453850B2 (enExample)
JP (1) JP7046049B2 (enExample)
KR (1) KR102228497B1 (enExample)
CN (1) CN109643715B (enExample)
TW (1) TWI744358B (enExample)
WO (1) WO2018017677A1 (enExample)

Families Citing this family (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10453752B2 (en) * 2017-09-18 2019-10-22 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a gate-all-around semiconductor device
US10833078B2 (en) 2017-12-04 2020-11-10 Tokyo Electron Limited Semiconductor apparatus having stacked gates and method of manufacture thereof
KR102449389B1 (ko) 2018-03-19 2022-09-29 도쿄엘렉트론가부시키가이샤 3차원 소자 및 이를 형성하는 방법
US10381273B1 (en) 2018-04-11 2019-08-13 International Business Machines Corporation Vertically stacked multi-channel transistor structure
JP7351307B2 (ja) 2018-09-25 2023-09-27 株式会社ソシオネクスト 半導体装置及びその製造方法
US10872818B2 (en) 2018-10-26 2020-12-22 Taiwan Semiconductor Manufacturing Company, Ltd. Buried power rail and method forming same
EP3671825A1 (en) 2018-12-20 2020-06-24 IMEC vzw Method for connecting a buried interconnect rail and a semiconductor fin in an integrated circuit chip
US10985103B2 (en) 2019-03-01 2021-04-20 Samsung Electronics Co., Ltd Apparatus and method of forming backside buried conductor in integrated circuit
US10818674B2 (en) * 2019-03-07 2020-10-27 Globalfoundries Inc. Structures and SRAM bit cells integrating complementary field-effect transistors
CN113224079B (zh) * 2019-03-29 2023-07-21 长江存储科技有限责任公司 3d存储器件及其制造方法
WO2020217400A1 (ja) 2019-04-25 2020-10-29 株式会社ソシオネクスト 半導体装置
WO2020217396A1 (ja) 2019-04-25 2020-10-29 株式会社ソシオネクスト 半導体装置
WO2020230666A1 (ja) * 2019-05-13 2020-11-19 株式会社ソシオネクスト 半導体記憶装置
US11335599B2 (en) * 2019-05-24 2022-05-17 Tokyo Electron Limited Self-aligned contacts for 3D logic and memory
WO2020255801A1 (ja) 2019-06-17 2020-12-24 株式会社ソシオネクスト 半導体記憶装置
WO2020262248A1 (ja) 2019-06-28 2020-12-30 株式会社ソシオネクスト 半導体記憶装置
US11222964B2 (en) * 2019-07-08 2022-01-11 Tokyo Electron Limited Multiple planes of transistors with different transistor architectures to enhance 3D logic and memory circuits
KR102705854B1 (ko) * 2019-07-23 2024-09-11 에스케이하이닉스 주식회사 반도체 소자의 분석 시스템 및 방법
US11488947B2 (en) 2019-07-29 2022-11-01 Tokyo Electron Limited Highly regular logic design for efficient 3D integration
CN114467175B (zh) 2019-10-02 2025-04-29 株式会社索思未来 半导体集成电路装置及半导体集成电路装置的制造方法
US11581338B2 (en) 2019-10-04 2023-02-14 Samsung Electronics Co., Ltd. Optimization of semiconductor cell of vertical field effect transistor (VFET)
CN112614837A (zh) 2019-10-04 2021-04-06 三星电子株式会社 垂直场效应晶体管半导体单元的优化
JP7640861B2 (ja) * 2019-10-18 2025-03-06 株式会社ソシオネクスト 半導体集積回路装置
US11735525B2 (en) * 2019-10-21 2023-08-22 Tokyo Electron Limited Power delivery network for CFET with buried power rails
US11495540B2 (en) * 2019-10-22 2022-11-08 Tokyo Electron Limited Semiconductor apparatus having stacked devices and method of manufacture thereof
US11251080B2 (en) 2019-12-02 2022-02-15 Tokyo Electron Limited Method of making 3D circuits with integrated stacked 3D metal lines for high density circuits
KR102819048B1 (ko) 2019-12-31 2025-06-10 도쿄엘렉트론가부시키가이샤 3개의 적층된 디바이스 데크를 갖는 cfet sram 비트 셀
JP7730024B2 (ja) 2020-01-27 2025-08-27 株式会社ソシオネクスト 半導体記憶装置
DE102020125647A1 (de) 2020-01-31 2021-08-05 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung mit Komplementärfeldeffekttransistor des Typs mit vergrabenenen Logikleitern, Layout-Diagramm-Herstellungsverfahren und System dafür
US11362090B2 (en) * 2020-01-31 2022-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having buried logic conductor type of complementary field effect transistor, method of generating layout diagram and system for same
US10971505B1 (en) * 2020-02-10 2021-04-06 Taiwan Semiconductor Manufacturing Company Limited Memory devices and methods of manufacturing thereof
US11469321B2 (en) * 2020-02-27 2022-10-11 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device
JP2021150501A (ja) * 2020-03-19 2021-09-27 キオクシア株式会社 半導体記憶装置
US11915984B2 (en) 2020-07-17 2024-02-27 Synopsys, Inc. Forming a wrap-around contact to connect a source or drain epitaxial growth of a complimentary field effect transistor (CFET) to a buried power rail (BPR) of the CFET
US11742247B2 (en) 2020-07-17 2023-08-29 Synopsys, Inc. Epitaxial growth of source and drain materials in a complementary field effect transistor (CFET)
US12080608B2 (en) * 2020-07-17 2024-09-03 Synopsys, Inc. Self-limiting manufacturing techniques to prevent electrical shorts in a complementary field effect transistor (CFET)
US11710634B2 (en) 2020-07-17 2023-07-25 Synopsys, Inc. Fabrication technique for forming ultra-high density integrated circuit components
US12237333B2 (en) 2020-09-01 2025-02-25 Tokyo Electron Limited Power wall integration for multiple stacked devices
US11665878B2 (en) 2020-09-30 2023-05-30 Tokyo Electron Limited CFET SRAM bit cell with two stacked device decks
US11621332B2 (en) 2021-01-14 2023-04-04 International Business Machines Corporation Wraparound contact to a buried power rail
US11723187B2 (en) * 2021-03-16 2023-08-08 Tokyo Electron Limited Three-dimensional memory cell structure
US12087770B2 (en) 2021-08-05 2024-09-10 International Business Machines Corporation Complementary field effect transistor devices
US12002850B2 (en) 2021-08-31 2024-06-04 International Business Machines Corporation Nanosheet-based semiconductor structure with dielectric pillar
US11804436B2 (en) 2021-09-03 2023-10-31 International Business Machines Corporation Self-aligned buried power rail cap for semiconductor devices
US12426338B2 (en) 2021-10-27 2025-09-23 International Business Machines Corporation Buried power rail with robust connection to a wrap around contact
US12279452B2 (en) 2021-12-15 2025-04-15 International Business Machines Corporation Stacked complementary transistor structure for three-dimensional integration
US12349406B2 (en) 2021-12-17 2025-07-01 International Business Machines Corporation Hybrid gate cut for stacked transistors
US11665877B1 (en) 2021-12-29 2023-05-30 International Business Machines Corporation Stacked FET SRAM design
US12349457B2 (en) 2022-04-14 2025-07-01 International Business Machines Corporation Stacked transistors having bottom contact with replacement spacer
US12200920B2 (en) 2022-04-28 2025-01-14 Samsung Electronics Co., Ltd. Integrated circuit devices including a power distribution network and methods of forming the same
US12272648B2 (en) 2022-06-15 2025-04-08 International Business Machines Corporation Semiconductor device having a backside power rail
US12262552B2 (en) 2022-07-22 2025-03-25 International Business Machines Corporation Source/drain epitaxy process in stacked FET
US12394462B2 (en) 2022-09-28 2025-08-19 International Business Machines Corporation Stacked FET with three-terminal SOT MRAM
CN118431184A (zh) * 2024-07-05 2024-08-02 芯梦达半导体科技(济南)有限公司 存储装置、半导体器件及存储器系统

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011060838A (ja) 2009-09-07 2011-03-24 Toshiba Corp 不揮発性半導体記憶装置、及びその製造方法
CN102623322A (zh) 2012-03-31 2012-08-01 上海华力微电子有限公司 基于体硅的纵向堆叠式SiNWFET制备方法
US20140097502A1 (en) 2012-10-10 2014-04-10 Seoul National University R & Db Foundation Semiconductor device and fabricating method thereof

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5631863A (en) * 1995-02-14 1997-05-20 Honeywell Inc. Random access memory cell resistant to radiation induced upsets
US7315466B2 (en) * 2004-08-04 2008-01-01 Samsung Electronics Co., Ltd. Semiconductor memory device and method for arranging and manufacturing the same
KR100653699B1 (ko) * 2004-08-04 2006-12-04 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 배치방법
US7598544B2 (en) * 2005-01-14 2009-10-06 Nanotero, Inc. Hybrid carbon nanotude FET(CNFET)-FET static RAM (SRAM) and method of making same
JP4496094B2 (ja) 2005-01-14 2010-07-07 シャープ株式会社 半導体装置及び半導体集積回路
KR100707212B1 (ko) 2006-03-08 2007-04-13 삼성전자주식회사 나노 와이어 메모리 소자 및 그 제조 방법
KR100718159B1 (ko) * 2006-05-18 2007-05-14 삼성전자주식회사 와이어-타입 반도체 소자 및 그 제조 방법
GB2458907A (en) * 2008-04-01 2009-10-07 Sharp Kk Device interconnects
US8338292B2 (en) * 2009-02-18 2012-12-25 International Business Machines Corporation Body contacts for FET in SOI SRAM array
US8084308B2 (en) 2009-05-21 2011-12-27 International Business Machines Corporation Single gate inverter nanowire mesh
US8183104B2 (en) 2010-07-07 2012-05-22 Hobbs Christopher C Method for dual-channel nanowire FET device
US8753942B2 (en) 2010-12-01 2014-06-17 Intel Corporation Silicon and silicon germanium nanowire structures
WO2013095341A1 (en) 2011-12-19 2013-06-27 Intel Corporation Cmos implementation of germanium and iii-v nanowires and nanoribbons in gate-all-around architecture
US9012284B2 (en) 2011-12-23 2015-04-21 Intel Corporation Nanowire transistor devices and forming techniques
CN106653694B (zh) 2011-12-23 2019-10-18 英特尔公司 Cmos纳米线结构
US9224809B2 (en) * 2012-05-17 2015-12-29 The Board Of Trustees Of The University Of Illinois Field effect transistor structure comprising a stack of vertically separated channel nanowires
US9484447B2 (en) * 2012-06-29 2016-11-01 Intel Corporation Integration methods to fabricate internal spacers for nanowire devices
US9000530B2 (en) 2013-04-23 2015-04-07 International Business Machines Corporation 6T SRAM architecture for gate-all-around nanowire devices
US9595525B2 (en) 2014-02-10 2017-03-14 International Business Machines Corporation Semiconductor device including nanowire transistors with hybrid channels
US9449820B2 (en) * 2014-12-22 2016-09-20 International Business Machines Corporation Epitaxial growth techniques for reducing nanowire dimension and pitch
US9583490B2 (en) * 2015-01-20 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Inverters and manufacturing methods thereof
EP3127862B1 (en) 2015-08-06 2018-04-18 IMEC vzw A method of manufacturing a gate-all-around nanowire device comprising two different nanowires
US9947591B2 (en) 2015-12-22 2018-04-17 Imec Vzw Method for manufacturing a Si-based high-mobility CMOS device with stacked channel layers, and resulting devices
US10043796B2 (en) * 2016-02-01 2018-08-07 Qualcomm Incorporated Vertically stacked nanowire field effect transistors

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011060838A (ja) 2009-09-07 2011-03-24 Toshiba Corp 不揮発性半導体記憶装置、及びその製造方法
CN102623322A (zh) 2012-03-31 2012-08-01 上海华力微电子有限公司 基于体硅的纵向堆叠式SiNWFET制备方法
US20140097502A1 (en) 2012-10-10 2014-04-10 Seoul National University R & Db Foundation Semiconductor device and fabricating method thereof

Also Published As

Publication number Publication date
TWI744358B (zh) 2021-11-01
WO2018017677A1 (en) 2018-01-25
US20190326301A1 (en) 2019-10-24
US10453850B2 (en) 2019-10-22
KR20190026018A (ko) 2019-03-12
CN109643715B (zh) 2023-05-12
KR102228497B1 (ko) 2021-03-15
US10964706B2 (en) 2021-03-30
US20180026042A1 (en) 2018-01-25
US20180240802A1 (en) 2018-08-23
JP2019523553A (ja) 2019-08-22
CN109643715A (zh) 2019-04-16
TW201813055A (zh) 2018-04-01
US10573655B2 (en) 2020-02-25

Similar Documents

Publication Publication Date Title
JP7046049B2 (ja) 三次元半導体デバイス及び製造方法
JP7049316B2 (ja) 三次元半導体デバイス及び製造方法
JP7631440B2 (ja) 階段貫通コンタクトを有する三次元メモリデバイス
US11903185B2 (en) Vertical memory device
JP7074968B2 (ja) ３次元デバイス及びそれを形成する方法
CN103325418B (zh) 用于rom单元的器件
TWI697105B (zh) 一種三維有接面半導體記憶體元件及其製造方法
US9312265B2 (en) Apparatus for high speed ROM cells
KR102850920B1 (ko) 다수의 적층된 디바이스를 위한 전력 벽 집적
CN111223863B (zh) 动态随机存取存储器结构
US20220399340A1 (en) Semiconductor memory device
CN114975616A (zh) 存储单元和具有该存储单元的半导体存储器件
US10720363B2 (en) Method of forming vertical transistor device
US8426903B2 (en) Semiconductor device and method of manufacturing same
WO2022093352A1 (en) Method for designing three dimensional metal lines for enhanced device performance
JP7618910B2 (ja) 半導体構造体およびそれを製造するための方法
US12009355B2 (en) 3D stacked DRAM with 3D vertical circuit design
TWI900644B (zh) 用於複數堆疊裝置的電力牆整合
US11626329B2 (en) Metal connections and routing for advanced 3D layout designs
US20250098174A1 (en) Nanosheet 3d transistor for advanced memory elements

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200518

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20200518

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20210209

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20210914

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20211115

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20220112

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20220222

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20220322

R150 Certificate of patent or registration of utility model

Ref document number: 7046049

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250