JP7074968B2 - 3次元デバイス及びそれを形成する方法 - Google Patents
3次元デバイス及びそれを形成する方法 Download PDFInfo
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- JP7074968B2 JP7074968B2 JP2020547388A JP2020547388A JP7074968B2 JP 7074968 B2 JP7074968 B2 JP 7074968B2 JP 2020547388 A JP2020547388 A JP 2020547388A JP 2020547388 A JP2020547388 A JP 2020547388A JP 7074968 B2 JP7074968 B2 JP 7074968B2
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Description
本出願は、2018年3月19日に出願された米国仮特許出願第62/645,102号明細書の利益を主張するものであり、この仮特許出願の内容全体が参照により本明細書に組み込まれる。
Claims (20)
- 半導体デバイスであって、
複数の第1のソース/ドレイン(S/D)コンタクト及び複数の第1のソース/ドレインであって、前記複数の第1のS/Dコンタクトの各々は、それぞれの第1のソース/ドレインの上に形成され、上部部分、底部部分及び側部部分を有するバー形状を有し、前記複数の第1のソース/ドレイン(S/D)コンタクトの各々の前記底部部分は、前記それぞれの第1のソース/ドレインを覆う、複数の第1のソース/ドレイン(S/D)コンタクト及び複数の第1のソース/ドレインと、
前記複数の第1のS/Dコンタクトの上に形成された複数の第1の誘電体キャップであって、前記複数の第1の誘電体キャップの各々は、それぞれの第1のS/Dコンタクトの上に配置され、前記それぞれの第1のS/Dコンタクトの前記上部部分及び前記側部部分の少なくとも一部を覆う、複数の第1の誘電体キャップと、
前記複数の第1のS/Dコンタクトの上に配置された複数の第2のS/Dコンタクト及び複数の第2のソース/ドレインであって、前記複数の第2のS/Dコンタクトの各々は、それぞれの第2のS/Dの上に形成され、上部部分、底部部分及び側部部分を有するバー形状を有し、前記複数の第2のソース/ドレイン(S/D)コンタクトの各々の前記底部部分は、前記それぞれの第2のソース/ドレインを覆い、前記複数の第2のS/Dコンタクトは、前記複数の第1のS/Dコンタクトの上に互い違いに配置されて階段状構成を形成する、複数の第2のS/Dコンタクト及び複数の第2のソース/ドレインと、
前記複数の第2のS/Dコンタクトの上に形成された複数の第2の誘電体キャップであって、前記複数の第2の誘電体キャップの各々は、それぞれの第2のS/Dコンタクトの上に配置され、前記それぞれの第2のS/Dコンタクトの前記上部部分及び前記側部部分の少なくとも一部を覆う、複数の第2の誘電体キャップと、
を含む半導体デバイス。 - 前記複数の第1の誘電体キャップの各々は、前記それぞれの第1のS/Dコンタクトの前記側部部分を完全に覆う、請求項1に記載の半導体デバイス。
- 前記複数の第2の誘電体キャップの各々は、前記それぞれの第2のS/Dコンタクトの前記側部部分を完全に覆う、請求項1に記載の半導体デバイス。
- 前記複数の第1の誘電体キャップの各々は、前記それぞれの第1のS/Dコンタクトの前記上部部分上に配置された底部層と、前記それぞれの第1のS/Dコンタクトの前記上部部分及び前記側部部分を覆うように前記底部層上に形成された上部層とを含む、請求項1に記載の半導体デバイス。
- 前記複数の第2の誘電体キャップの各々は、前記それぞれの第2のS/Dコンタクトの前記上部部分上に配置された底部層と、前記それぞれの第2のS/Dコンタクトの前記上部部分及び前記側部部分を覆うように前記底部層上に形成された上部層とを含む、請求項1に記載の半導体デバイス。
- 基板に埋め込まれ、階段状構成を形成するように前記複数の第1のS/Dコンタクトの下に配置された、複数のパワーレールを更に含み、
前記複数の第1のS/Dコンタクトの少なくとも1つは、第1のビア・トゥ・レール構造を通して前記複数のパワーレールの第1のパワーレールに接続され、及び
前記複数の第2のS/Dコンタクトの少なくとも1つは、第2のビア・トゥ・レール構造を通して前記複数のパワーレールの第2のパワーレールに接続される、請求項1に記載の半導体デバイス。 - 前記複数のパワーレールの上に形成された複数の第3の誘電体キャップを更に含み、前記複数の第3の誘電体キャップの各々は、それぞれのパワーレールの上に形成され、前記第1のビア・トゥ・レール構造は、前記第1のパワーレール上に形成された、前記第3の誘電体キャップの1つを通過し、前記第2のビア・トゥ・レール構造は、前記第2のパワーレール上に形成された、前記第3の誘電体キャップの別の1つを通過する、請求項6に記載の半導体デバイス。
- 更に、
複数のビア・トゥ・ドレイン構造であって、前記複数の第1のS/Dコンタクト及び前記複数の第2のS/Dコンタクトは、階段状であり、前記複数のビア・トゥ・ドレイン構造の少なくとも1つは、第1の誘電体キャップを通過して前記複数の第1のS/Dコンタクトの1つに接続し、前記複数のビア・トゥ・ドレイン構造の少なくとも別の1つは、第2の誘電体キャップを通過して前記複数の第2のS/Dコンタクトの1つに接続する、複数のビア・トゥ・ドレイン構造と、
複数の金属線であって、前記複数のビア・トゥ・ドレイン構造と電気的に結合される、複数の金属線と、
を有する、請求項6に記載の半導体デバイス。 - 前記複数の第1の誘電体キャップの各々は、前記それぞれの第1のS/Dコンタクトを、隣接する第1のS/Dコンタクト、隣接するビア・トゥ・ドレイン構造、隣接する第1のビア・トゥ・レール構造及び隣接する第2のビア・トゥ・レール構造の少なくとも1つから分離するように構成される、請求項8に記載の半導体デバイス。
- 前記複数の第2の誘電体キャップの各々は、前記それぞれの第2のS/Dコンタクトを、隣接する第2のS/Dコンタクト、隣接するビア・トゥ・ドレイン構造及び隣接する第2のビア・トゥ・レール構造の少なくとも1つから分離するように構成される、請求項8に記載の半導体デバイス。
- 更に、
前記パワーレールの一つの長さ方向に沿って形成された第1のチャネル構造と、
前記パワーレールの前記一つの前記長さ方向に沿って形成された第2のチャネル構造と、
複数のゲート構造と、
を含み、
前記複数のゲート構造は、前記第1のチャネル構造及び前記第2のチャネル構造を取り囲み、
前記複数の第1のソース/ドレインは、前記第1のチャネル構造を取り囲み、
前記複数の第2のソース/ドレインは、前記第2のチャネル構造を取り囲み、
前記複数のゲート構造及び前記複数の第1のソース/ドレインは、複数の低Kスペーサーによって互いから離間され、交互に配置され、
前記複数のゲート構造及び前記複数の第2のソース/ドレインは、前記複数の低Kスペーサーによって互いから離間され、交互に配置される、請求項6に記載の半導体デバイス。 - 半導体デバイスを製造するための方法であって、
半導体構造を形成するステップであって、前記半導体構造は、第1のチャネル構造、第2のチャネル構造、及び基板内に埋め込まれた複数のパワーレールを含み、該複数のパワーレールは、前記第1のチャネル構造の下に配置されて階段状構成を形成し、前記第2のチャネル構造は、前記第1のチャネル構造の上に形成され、前記第1及び第2のチャネル構造は、前記複数のパワーレールの長さ方向に沿って延びる、ステップと、
複数の第1のソース/ドレインを形成するステップであって、前記複数の第1のソース/ドレインは、前記第1のチャネル構造を取り囲み、第1の誘電体層内に埋め込まれる、ステップと、
複数の第1のソース/ドレイン(S/D)コンタクトを形成するステップであって、前記複数の第1のS/Dコンタクトの各々は、それぞれの第1のソース/ドレインの上に形成され、上部部分、底部部分及び側部部分を有するバー形状を有し、前記複数の第1のソース/ドレイン(S/D)コンタクトの各々の前記底部部分は、前記それぞれの第1のソース/ドレインを覆う、ステップと、
前記複数の第1のS/Dコンタクトの上に複数の第1の誘電体キャップを形成するステップであって、前記複数の第1の誘電体キャップの各々は、それぞれの第1のS/Dコンタクトの上に配置されて、前記それぞれの第1のS/Dコンタクトの前記上部部分及び前記側部部分の少なくとも一部を覆う、ステップと、
複数の第2のソース/ドレインを形成するステップであって、前記複数の第2のソース/ドレインは、前記複数の第1のソース/ドレインの上に配置され、前記第2のチャネル構造を取り囲み、第2の誘電体層内に埋め込まれる、ステップと、
複数の第2のソース/ドレイン(S/D)コンタクトを形成するステップであって、前記複数の第2のS/Dコンタクトの各々は、それぞれの第2のソース/ドレインの上に形成され、上部部分、底部部分及び側部部分を有するバー形状を有し、前記複数の第2のソース/ドレイン(S/D)コンタクトの各々の前記底部部分は、前記それぞれの第2のソース/ドレインを覆い、前記複数の第2のS/Dコンタクトは、前記複数の第1のS/Dコンタクトの上に互い違いに配置されて階段状構成を形成する、ステップと、
前記複数の第2のS/Dコンタクトの上に複数の第2の誘電体キャップを形成するステップであって、前記複数の第2の誘電体キャップの各々は、それぞれの第2のS/Dコンタクトの上に配置されて、前記それぞれの第2のS/Dコンタクトの前記上部部分及び前記側部部分の少なくとも一部を覆う、ステップと、
を含む方法。 - 前記複数の第1のソース/ドレイン(S/D)コンタクトを形成するステップは、更に、
前記第1の誘電体層内に複数の第1のデュアルダマシン開口部を形成して、前記複数の第1のソース/ドレインと、前記複数のパワーレールの少なくとも1つとを露出させるステップと、
前記第1のデュアルダマシン開口部に、前記複数の第1のS/Dコンタクト及び少なくとも第1のビア・トゥ・レール構造を形成するステップであって、前記複数の第1のS/Dコンタクトの各々は、それぞれの第1のソース/ドレインの上に形成され、上部部分、底部部分及び側部部分を有するバー形状を有し、前記複数の第1のソース/ドレイン(S/D)コンタクトの各々の前記底部部分は、前記それぞれの第1のソース/ドレインを覆い、前記複数の第1のS/Dコンタクトの少なくとも1つは、前記第1のビア・トゥ・レール構造を通して複数のパワーレールの1つに接続される、ステップと、
を含む、請求項12に記載の方法。 - 前記複数の第1のS/Dコンタクトの上に前記複数の第1の誘電体キャップを形成するステップは、更に、
前記複数の第1のS/Dコンタクトの前記上部部分の上に複数の底部誘電体層を形成するステップであって、前記複数の底部誘電体層の各々は、それぞれの第1のS/Dコンタクトの前記上部部分上に配置される、ステップと、
前記複数の第1のデュアルダマシン開口部を第3の誘電体層で充填するステップと、
前記第1の誘電体層及び前記第3の誘電体層をくぼませて、前記複数の第1のS/Dコンタクトの前記上部部分及び側部部分を露出させるステップと、
前記複数の底部誘電体層の上に複数の上部誘電体層を形成するステップであって、前記複数の上部誘電体層の各々は、それぞれの底部誘電体層の上に配置されて、前記それぞれの第1のS/Dコンタクトの前記上部部分及び前記側部部分を覆う、ステップと、
を含む、請求項13に記載の方法。 - 前記複数の第2のソース/ドレイン(S/D)コンタクトを形成するステップは、更に、
前記第2の誘電体層に複数の第2のデュアルダマシン開口部を形成して、前記複数の第2のソース/ドレイン及び前記複数のパワーレールの少なくとも1つを露出させるステップと、
前記第2のデュアルダマシン開口部に前記複数の第2のS/Dコンタクト及び少なくとも第2のビア・トゥ・レール構造を形成するステップであって、前記複数の第2のS/Dコンタクトの各々は、それぞれの第2のソース/ドレインの上に形成され、上部部分、底部部分及び側部部分を有するバー形状を有し、前記複数の第2のソース/ドレイン(S/D)コンタクトの各々の前記底部部分は、前記それぞれの第2のソース/ドレインを覆い、前記複数の第2のS/Dコンタクトの少なくとも1つは、前記第2のビア・トゥ・レール構造を通して複数のパワーレールの1つに接続される、ステップと、
を含む、請求項12に記載の方法。 - 前記複数の第2のS/Dコンタクトの上に前記複数の第2の誘電体キャップを形成するステップは、更に、
前記複数の第2のS/Dコンタクトの前記上部部分の上に複数の底部誘電体層を形成するステップであって、前記複数の底部誘電体層の各々は、それぞれの第2のS/Dコンタクトの前記上部部分上に配置される、ステップと、
前記第2の誘電体層をくぼませて、前記複数の第2のS/Dコンタクトの前記側部部分を露出させるステップと、
前記複数の底部誘電体層の上に複数の上部誘電体層を形成するステップであって、前記複数の上部誘電体層の各々は、それぞれの底部層の上に配置されて、前記それぞれの第2のS/Dコンタクトの前記上部部分及び前記側部部分を覆う、ステップと、
を含む、請求項15に記載の方法。 - 更に、
複数のゲート構造を形成するステップを含み、
前記複数のゲート構造は、前記第1のチャネル構造及び前記第2のチャネル構造を取り囲み、
前記複数のゲート構造及び前記複数の第1のソース/ドレインは、複数の低Kスペーサーによって互いから離間され、交互に配置され、
前記複数のゲート構造及び前記複数の第2のソース/ドレインは、前記複数の低Kスペーサーによって互いから離間され、交互に配置される、請求項12に記載の方法。 - 半導体デバイスであって、
基板と、
前記基板内に埋め込まれた複数のパワーレールと、
階段状構成を形成するように前記複数のパワーレールの上に形成された複数の第1のソース/ドレインと、
前記複数の第1のソース/ドレインの上に形成された複数の第1のソース/ドレイン(S/D)コンタクトであって、前記複数の第1のS/Dコンタクトの各々は、それぞれの第1のソース/ドレインの上に形成され、上部部分、底部部分及び側部部分を有するバー形状を有し、前記複数の第1のソース/ドレイン(S/D)コンタクトの各々の前記底部部分は、前記それぞれの第1のソース/ドレインを覆う、複数の第1のソース/ドレイン(S/D)コンタクトと、
前記複数の第1のS/Dコンタクトの上に形成された複数の第1の誘電体キャップであって、前記複数の第1の誘電体キャップの各々は、それぞれの第1のS/Dコンタクトの上に配置されて、前記それぞれの第1のS/Dコンタクトを、隣接する第1のS/Dコンタクト、隣接するビア・トゥ・ドレイン構造、隣接する第1のビア・トゥ・レール構造及び隣接する第2のビア・トゥ・レール構造の少なくとも1つから分離するように、前記それぞれの第1のS/Dコンタクトの前記上部部分及び前記側部部分の少なくとも一部を覆う、複数の第1の誘電体キャップと、
階段状構成を形成するように、前記複数の第1のソース/ドレインの上に形成された複数の第2のソース/ドレインと、
前記複数の第2のソース/ドレインの上に形成された複数の第2のソース/ドレイン(S/D)コンタクトであって、前記複数の第2のS/Dコンタクトの各々は、それぞれの第2のソース/ドレインの上に形成され、上部部分、底部部分及び側部部分を有するバー形状を有し、前記複数の第2のソース/ドレイン(S/D)コンタクトの各々の前記底部部分は、前記それぞれの第2のソース/ドレインを覆い、前記複数の第2のS/Dコンタクトは、前記複数の第1のS/Dコンタクトの上に互い違いに配置されて階段状構成を形成する、複数の第2のソース/ドレイン(S/D)コンタクトと、
前記複数の第2のS/Dコンタクトの上に形成された複数の第2の誘電体キャップであって、前記複数の第2の誘電体キャップの各々は、それぞれの第2のS/Dコンタクトの上に配置されて、前記それぞれの第2のS/Dコンタクトを、隣接する第2のS/Dコンタクト、隣接するビア・トゥ・ドレイン構造及び隣接する第2のビア・トゥ・レール構造の少なくとも1つから分離するように、前記それぞれの第2のS/Dコンタクトの前記上部部分及び前記側部部分の少なくとも一部を覆う、複数の第2の誘電体キャップと、
を含み、
前記複数の第1のS/Dコンタクトの少なくとも1つは、第1のビア・トゥ・レール構造を通して前記複数のパワーレールの第1のパワーレールに接続され、前記複数の第2のS/Dコンタクトの少なくとも1つは、第2のビア・トゥ・レール構造を通して前記複数のパワーレールの第2のパワーレールに接続される、半導体デバイス。 - 更に、
複数のビア・トゥ・ドレイン構造であって、前記複数の第1のS/Dコンタクト及び前記複数の第2のS/Dコンタクトは、階段状であり、前記複数のビア・トゥ・ドレイン構造の少なくとも1つは、前記第1の誘電体キャップの1つを通過して前記複数の第1のS/Dコンタクトの1つに接続し、前記複数のビア・トゥ・ドレイン構造の少なくとも別の1つは、前記第2の誘電体キャップを通過して前記複数の第2のS/Dコンタクトの1つに接続する、複数のビア・トゥ・ドレイン構造と、
複数の金属線であって、前記複数のビア・トゥ・ドレイン構造と電気的に結合される、複数の金属線と
を含む、請求項18に記載の半導体デバイス。 - 更に、
前記パワーレールの一つの長さ方向に沿って形成された第1のチャネル構造と、
前記パワーレールの前記一つの前記長さ方向に沿って形成された第2のチャネル構造と、
複数のゲート構造と、
を含み、
前記複数のゲート構造は、前記第1のチャネル構造及び前記第2のチャネル構造を取り囲み、
前記複数の第1のソース/ドレインは、前記第1のチャネル構造を取り囲み、
前記複数の第2のソース/ドレインは、前記第2のチャネル構造を取り囲み、
前記複数のゲート構造及び前記複数の第1のソース/ドレインは、複数の低Kスペーサーによって互いから離間され、交互に配置され、
前記複数のゲート構造及び前記複数の第2のソース/ドレインは、前記複数の低Kスペーサーによって互いから離間され、交互に配置される、請求項18に記載の半導体デバイス。
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