JP2019523553A5 - - Google Patents
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- Publication number
- JP2019523553A5 JP2019523553A5 JP2019502069A JP2019502069A JP2019523553A5 JP 2019523553 A5 JP2019523553 A5 JP 2019523553A5 JP 2019502069 A JP2019502069 A JP 2019502069A JP 2019502069 A JP2019502069 A JP 2019502069A JP 2019523553 A5 JP2019523553 A5 JP 2019523553A5
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- nanowire
- fet
- semiconductor device
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 239000002070 nanowire Substances 0.000 claims 41
- 239000004065 semiconductor Substances 0.000 claims 19
- 238000000034 method Methods 0.000 claims 10
- 239000000758 substrate Substances 0.000 claims 10
- 239000000463 material Substances 0.000 claims 6
- 230000005669 field effect Effects 0.000 claims 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims 2
- 238000000151 deposition Methods 0.000 claims 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims 1
- 230000004888 barrier function Effects 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 230000000295 complement effect Effects 0.000 claims 1
- 230000008021 deposition Effects 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 238000002955 isolation Methods 0.000 claims 1
Applications Claiming Priority (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201662363973P | 2016-07-19 | 2016-07-19 | |
| US62/363,973 | 2016-07-19 | ||
| US201662372106P | 2016-08-08 | 2016-08-08 | |
| US62/372,106 | 2016-08-08 | ||
| US201662373164P | 2016-08-10 | 2016-08-10 | |
| US62/373,164 | 2016-08-10 | ||
| PCT/US2017/042802 WO2018017677A1 (en) | 2016-07-19 | 2017-07-19 | Three-dimensional semiconductor device and method of fabrication |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2019523553A JP2019523553A (ja) | 2019-08-22 |
| JP2019523553A5 true JP2019523553A5 (enExample) | 2020-06-25 |
| JP7046049B2 JP7046049B2 (ja) | 2022-04-01 |
Family
ID=60988140
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2019502069A Active JP7046049B2 (ja) | 2016-07-19 | 2017-07-19 | 三次元半導体デバイス及び製造方法 |
Country Status (6)
| Country | Link |
|---|---|
| US (3) | US10453850B2 (enExample) |
| JP (1) | JP7046049B2 (enExample) |
| KR (1) | KR102228497B1 (enExample) |
| CN (1) | CN109643715B (enExample) |
| TW (1) | TWI744358B (enExample) |
| WO (1) | WO2018017677A1 (enExample) |
Families Citing this family (54)
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| KR102449389B1 (ko) | 2018-03-19 | 2022-09-29 | 도쿄엘렉트론가부시키가이샤 | 3차원 소자 및 이를 형성하는 방법 |
| US10381273B1 (en) | 2018-04-11 | 2019-08-13 | International Business Machines Corporation | Vertically stacked multi-channel transistor structure |
| JP7351307B2 (ja) | 2018-09-25 | 2023-09-27 | 株式会社ソシオネクスト | 半導体装置及びその製造方法 |
| US10872818B2 (en) | 2018-10-26 | 2020-12-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Buried power rail and method forming same |
| EP3671825A1 (en) | 2018-12-20 | 2020-06-24 | IMEC vzw | Method for connecting a buried interconnect rail and a semiconductor fin in an integrated circuit chip |
| US10985103B2 (en) | 2019-03-01 | 2021-04-20 | Samsung Electronics Co., Ltd | Apparatus and method of forming backside buried conductor in integrated circuit |
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| CN113224079B (zh) * | 2019-03-29 | 2023-07-21 | 长江存储科技有限责任公司 | 3d存储器件及其制造方法 |
| WO2020217400A1 (ja) | 2019-04-25 | 2020-10-29 | 株式会社ソシオネクスト | 半導体装置 |
| WO2020217396A1 (ja) | 2019-04-25 | 2020-10-29 | 株式会社ソシオネクスト | 半導体装置 |
| WO2020230666A1 (ja) * | 2019-05-13 | 2020-11-19 | 株式会社ソシオネクスト | 半導体記憶装置 |
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| WO2020255801A1 (ja) | 2019-06-17 | 2020-12-24 | 株式会社ソシオネクスト | 半導体記憶装置 |
| WO2020262248A1 (ja) | 2019-06-28 | 2020-12-30 | 株式会社ソシオネクスト | 半導体記憶装置 |
| US11222964B2 (en) * | 2019-07-08 | 2022-01-11 | Tokyo Electron Limited | Multiple planes of transistors with different transistor architectures to enhance 3D logic and memory circuits |
| KR102705854B1 (ko) * | 2019-07-23 | 2024-09-11 | 에스케이하이닉스 주식회사 | 반도체 소자의 분석 시스템 및 방법 |
| US11488947B2 (en) | 2019-07-29 | 2022-11-01 | Tokyo Electron Limited | Highly regular logic design for efficient 3D integration |
| CN114467175B (zh) | 2019-10-02 | 2025-04-29 | 株式会社索思未来 | 半导体集成电路装置及半导体集成电路装置的制造方法 |
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| CN112614837A (zh) | 2019-10-04 | 2021-04-06 | 三星电子株式会社 | 垂直场效应晶体管半导体单元的优化 |
| JP7640861B2 (ja) * | 2019-10-18 | 2025-03-06 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| US11735525B2 (en) * | 2019-10-21 | 2023-08-22 | Tokyo Electron Limited | Power delivery network for CFET with buried power rails |
| US11495540B2 (en) * | 2019-10-22 | 2022-11-08 | Tokyo Electron Limited | Semiconductor apparatus having stacked devices and method of manufacture thereof |
| US11251080B2 (en) | 2019-12-02 | 2022-02-15 | Tokyo Electron Limited | Method of making 3D circuits with integrated stacked 3D metal lines for high density circuits |
| KR102819048B1 (ko) | 2019-12-31 | 2025-06-10 | 도쿄엘렉트론가부시키가이샤 | 3개의 적층된 디바이스 데크를 갖는 cfet sram 비트 셀 |
| JP7730024B2 (ja) | 2020-01-27 | 2025-08-27 | 株式会社ソシオネクスト | 半導体記憶装置 |
| DE102020125647A1 (de) | 2020-01-31 | 2021-08-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Halbleitervorrichtung mit Komplementärfeldeffekttransistor des Typs mit vergrabenenen Logikleitern, Layout-Diagramm-Herstellungsverfahren und System dafür |
| US11362090B2 (en) * | 2020-01-31 | 2022-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having buried logic conductor type of complementary field effect transistor, method of generating layout diagram and system for same |
| US10971505B1 (en) * | 2020-02-10 | 2021-04-06 | Taiwan Semiconductor Manufacturing Company Limited | Memory devices and methods of manufacturing thereof |
| US11469321B2 (en) * | 2020-02-27 | 2022-10-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device |
| JP2021150501A (ja) * | 2020-03-19 | 2021-09-27 | キオクシア株式会社 | 半導体記憶装置 |
| US11915984B2 (en) | 2020-07-17 | 2024-02-27 | Synopsys, Inc. | Forming a wrap-around contact to connect a source or drain epitaxial growth of a complimentary field effect transistor (CFET) to a buried power rail (BPR) of the CFET |
| US11742247B2 (en) | 2020-07-17 | 2023-08-29 | Synopsys, Inc. | Epitaxial growth of source and drain materials in a complementary field effect transistor (CFET) |
| US12080608B2 (en) * | 2020-07-17 | 2024-09-03 | Synopsys, Inc. | Self-limiting manufacturing techniques to prevent electrical shorts in a complementary field effect transistor (CFET) |
| US11710634B2 (en) | 2020-07-17 | 2023-07-25 | Synopsys, Inc. | Fabrication technique for forming ultra-high density integrated circuit components |
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| US11665878B2 (en) | 2020-09-30 | 2023-05-30 | Tokyo Electron Limited | CFET SRAM bit cell with two stacked device decks |
| US11621332B2 (en) | 2021-01-14 | 2023-04-04 | International Business Machines Corporation | Wraparound contact to a buried power rail |
| US11723187B2 (en) * | 2021-03-16 | 2023-08-08 | Tokyo Electron Limited | Three-dimensional memory cell structure |
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| US12002850B2 (en) | 2021-08-31 | 2024-06-04 | International Business Machines Corporation | Nanosheet-based semiconductor structure with dielectric pillar |
| US11804436B2 (en) | 2021-09-03 | 2023-10-31 | International Business Machines Corporation | Self-aligned buried power rail cap for semiconductor devices |
| US12426338B2 (en) | 2021-10-27 | 2025-09-23 | International Business Machines Corporation | Buried power rail with robust connection to a wrap around contact |
| US12279452B2 (en) | 2021-12-15 | 2025-04-15 | International Business Machines Corporation | Stacked complementary transistor structure for three-dimensional integration |
| US12349406B2 (en) | 2021-12-17 | 2025-07-01 | International Business Machines Corporation | Hybrid gate cut for stacked transistors |
| US11665877B1 (en) | 2021-12-29 | 2023-05-30 | International Business Machines Corporation | Stacked FET SRAM design |
| US12349457B2 (en) | 2022-04-14 | 2025-07-01 | International Business Machines Corporation | Stacked transistors having bottom contact with replacement spacer |
| US12200920B2 (en) | 2022-04-28 | 2025-01-14 | Samsung Electronics Co., Ltd. | Integrated circuit devices including a power distribution network and methods of forming the same |
| US12272648B2 (en) | 2022-06-15 | 2025-04-08 | International Business Machines Corporation | Semiconductor device having a backside power rail |
| US12262552B2 (en) | 2022-07-22 | 2025-03-25 | International Business Machines Corporation | Source/drain epitaxy process in stacked FET |
| US12394462B2 (en) | 2022-09-28 | 2025-08-19 | International Business Machines Corporation | Stacked FET with three-terminal SOT MRAM |
| CN118431184A (zh) * | 2024-07-05 | 2024-08-02 | 芯梦达半导体科技(济南)有限公司 | 存储装置、半导体器件及存储器系统 |
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| US8183104B2 (en) | 2010-07-07 | 2012-05-22 | Hobbs Christopher C | Method for dual-channel nanowire FET device |
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| WO2013095341A1 (en) | 2011-12-19 | 2013-06-27 | Intel Corporation | Cmos implementation of germanium and iii-v nanowires and nanoribbons in gate-all-around architecture |
| US9012284B2 (en) | 2011-12-23 | 2015-04-21 | Intel Corporation | Nanowire transistor devices and forming techniques |
| CN106653694B (zh) | 2011-12-23 | 2019-10-18 | 英特尔公司 | Cmos纳米线结构 |
| CN102623322B (zh) | 2012-03-31 | 2014-07-16 | 上海华力微电子有限公司 | 基于体硅的纵向堆叠式SiNWFET制备方法 |
| US9224809B2 (en) * | 2012-05-17 | 2015-12-29 | The Board Of Trustees Of The University Of Illinois | Field effect transistor structure comprising a stack of vertically separated channel nanowires |
| US9484447B2 (en) * | 2012-06-29 | 2016-11-01 | Intel Corporation | Integration methods to fabricate internal spacers for nanowire devices |
| KR102002380B1 (ko) | 2012-10-10 | 2019-07-23 | 삼성전자 주식회사 | 반도체 장치 및 그 제조 방법 |
| US9000530B2 (en) | 2013-04-23 | 2015-04-07 | International Business Machines Corporation | 6T SRAM architecture for gate-all-around nanowire devices |
| US9595525B2 (en) | 2014-02-10 | 2017-03-14 | International Business Machines Corporation | Semiconductor device including nanowire transistors with hybrid channels |
| US9449820B2 (en) * | 2014-12-22 | 2016-09-20 | International Business Machines Corporation | Epitaxial growth techniques for reducing nanowire dimension and pitch |
| US9583490B2 (en) * | 2015-01-20 | 2017-02-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Inverters and manufacturing methods thereof |
| EP3127862B1 (en) | 2015-08-06 | 2018-04-18 | IMEC vzw | A method of manufacturing a gate-all-around nanowire device comprising two different nanowires |
| US9947591B2 (en) | 2015-12-22 | 2018-04-17 | Imec Vzw | Method for manufacturing a Si-based high-mobility CMOS device with stacked channel layers, and resulting devices |
| US10043796B2 (en) * | 2016-02-01 | 2018-08-07 | Qualcomm Incorporated | Vertically stacked nanowire field effect transistors |
-
2017
- 2017-07-19 TW TW106124085A patent/TWI744358B/zh active
- 2017-07-19 JP JP2019502069A patent/JP7046049B2/ja active Active
- 2017-07-19 KR KR1020197003970A patent/KR102228497B1/ko active Active
- 2017-07-19 CN CN201780051097.0A patent/CN109643715B/zh active Active
- 2017-07-19 US US15/654,327 patent/US10453850B2/en active Active
- 2017-07-19 WO PCT/US2017/042802 patent/WO2018017677A1/en not_active Ceased
-
2018
- 2018-04-26 US US15/963,766 patent/US10573655B2/en active Active
-
2019
- 2019-06-24 US US16/450,550 patent/US10964706B2/en active Active
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