TWI743351B - 具有阻劑孔的扇出晶圓級封裝 - Google Patents
具有阻劑孔的扇出晶圓級封裝 Download PDFInfo
- Publication number
- TWI743351B TWI743351B TW107112587A TW107112587A TWI743351B TW I743351 B TWI743351 B TW I743351B TW 107112587 A TW107112587 A TW 107112587A TW 107112587 A TW107112587 A TW 107112587A TW I743351 B TWI743351 B TW I743351B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
- H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P54/00—Cutting or separating of wafers, substrates or parts of devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
- H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/0198—Manufacture or treatment batch processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
- H10W74/019—Manufacture or treatment using temporary auxiliary substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
- H10P72/7424—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
- H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/099—Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/941—Dispositions of bond pads
- H10W72/9413—Dispositions of bond pads on encapsulations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
- H10W74/014—Manufacture or treatment using batch processing
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201762484974P | 2017-04-13 | 2017-04-13 | |
| US62/484,974 | 2017-04-13 | ||
| US15/873,218 | 2018-01-17 | ||
| US15/873,218 US10593563B2 (en) | 2017-04-13 | 2018-01-17 | Fan-out wafer level package with resist vias |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201842643A TW201842643A (zh) | 2018-12-01 |
| TWI743351B true TWI743351B (zh) | 2021-10-21 |
Family
ID=63790230
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW107112587A TWI743351B (zh) | 2017-04-13 | 2018-04-12 | 具有阻劑孔的扇出晶圓級封裝 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US10593563B2 (https=) |
| JP (1) | JP6972171B2 (https=) |
| TW (1) | TWI743351B (https=) |
| WO (1) | WO2018191380A1 (https=) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11735570B2 (en) * | 2018-04-04 | 2023-08-22 | Intel Corporation | Fan out packaging pop mechanical attach method |
| US10748831B2 (en) * | 2018-05-30 | 2020-08-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor packages having thermal through vias (TTV) |
| KR102762976B1 (ko) | 2020-01-03 | 2025-02-07 | 삼성전자주식회사 | 반도체 패키지 |
| JP7574747B2 (ja) | 2021-06-04 | 2024-10-29 | 株式会社デンソー | 半導体装置およびその製造方法 |
| KR102933959B1 (ko) * | 2022-03-31 | 2026-03-03 | 삼성전자주식회사 | 집적회로 소자의 제조 방법 |
| CN115223973A (zh) * | 2022-09-20 | 2022-10-21 | 盛合晶微半导体(江阴)有限公司 | 一种扇出型芯片封装结构及封装方法 |
| CN117080087B (zh) * | 2023-10-13 | 2024-02-13 | 季华实验室 | 一种扇出型板级封装方法及扇出型板级封装结构 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5250843A (en) * | 1991-03-27 | 1993-10-05 | Integrated System Assemblies Corp. | Multichip integrated circuit modules |
| US20110084382A1 (en) * | 2009-10-07 | 2011-04-14 | Wei-Ming Chen | Chip package and fabrication method thereof |
| US20140008809A1 (en) * | 2011-12-30 | 2014-01-09 | Deca Technologies, Inc. | Die up fully molded fan-out wafer level packaging |
| US8901725B2 (en) * | 2010-03-18 | 2014-12-02 | Shinko Electric Industries Co., Ltd. | Wiring board and method of manufacturing the same, and semiconductor device and method of manufacturing the same |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5300813A (en) * | 1992-02-26 | 1994-04-05 | International Business Machines Corporation | Refractory metal capped low resistivity metal conductor lines and vias |
| JP2006108211A (ja) | 2004-10-01 | 2006-04-20 | North:Kk | 配線板と、その配線板を用いた多層配線基板と、その多層配線基板の製造方法 |
| US8253230B2 (en) * | 2008-05-15 | 2012-08-28 | Micron Technology, Inc. | Disabling electrical connections using pass-through 3D interconnects and associated systems and methods |
| KR101059629B1 (ko) | 2009-12-29 | 2011-08-25 | 하나 마이크론(주) | 반도체 패키지 제조방법 |
| US20110221018A1 (en) * | 2010-03-15 | 2011-09-15 | Xunqing Shi | Electronic Device Package and Methods of Manufacturing an Electronic Device Package |
| KR101151258B1 (ko) | 2010-04-13 | 2012-06-14 | 앰코 테크놀로지 코리아 주식회사 | 기준점 인식용 다이를 이용한 반도체 패키지 및 그 제조 방법 |
| US8535980B2 (en) * | 2010-12-23 | 2013-09-17 | Stmicroelectronics Pte Ltd. | Method for producing vias in fan-out wafers using dry film and conductive paste, and a corresponding semiconductor package |
| CN102376672B (zh) | 2011-11-30 | 2014-10-29 | 江苏长电科技股份有限公司 | 无基岛球栅阵列封装结构及其制造方法 |
| US8557632B1 (en) * | 2012-04-09 | 2013-10-15 | Monolithic 3D Inc. | Method for fabrication of a semiconductor device and structure |
| US9368438B2 (en) | 2012-12-28 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package (PoP) bonding structures |
| KR20240013281A (ko) * | 2015-06-22 | 2024-01-30 | 타호 리서치 리미티드 | 인터커넥트들 및 비아들에 의한 mems 구조물들의 통합 |
| US9368450B1 (en) * | 2015-08-21 | 2016-06-14 | Qualcomm Incorporated | Integrated device package comprising bridge in litho-etchable layer |
| US10242968B2 (en) * | 2015-11-05 | 2019-03-26 | Massachusetts Institute Of Technology | Interconnect structure and semiconductor structures for assembly of cryogenic electronic packages |
| US10396012B2 (en) * | 2016-05-27 | 2019-08-27 | International Business Machines Corporation | Advanced through substrate via metallization in three dimensional semiconductor integration |
| WO2018063347A1 (en) * | 2016-09-30 | 2018-04-05 | Intel Corporation | Systems, methods, and apparatuses for implementing a high mobility low contact resistance semiconducting oxide in metal contact vias for thin film transistors |
| US10586909B2 (en) * | 2016-10-11 | 2020-03-10 | Massachusetts Institute Of Technology | Cryogenic electronic packages and assemblies |
| US10163802B2 (en) * | 2016-11-29 | 2018-12-25 | Taiwan Semicondcutor Manufacturing Company, Ltd. | Fan-out package having a main die and a dummy die, and method of forming |
-
2018
- 2018-01-17 US US15/873,218 patent/US10593563B2/en active Active
- 2018-04-11 WO PCT/US2018/027112 patent/WO2018191380A1/en not_active Ceased
- 2018-04-11 JP JP2019555587A patent/JP6972171B2/ja active Active
- 2018-04-12 TW TW107112587A patent/TWI743351B/zh active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5250843A (en) * | 1991-03-27 | 1993-10-05 | Integrated System Assemblies Corp. | Multichip integrated circuit modules |
| US20110084382A1 (en) * | 2009-10-07 | 2011-04-14 | Wei-Ming Chen | Chip package and fabrication method thereof |
| US8901725B2 (en) * | 2010-03-18 | 2014-12-02 | Shinko Electric Industries Co., Ltd. | Wiring board and method of manufacturing the same, and semiconductor device and method of manufacturing the same |
| US20140008809A1 (en) * | 2011-12-30 | 2014-01-09 | Deca Technologies, Inc. | Die up fully molded fan-out wafer level packaging |
Also Published As
| Publication number | Publication date |
|---|---|
| US20180301350A1 (en) | 2018-10-18 |
| TW201842643A (zh) | 2018-12-01 |
| JP6972171B2 (ja) | 2021-11-24 |
| JP2020517107A (ja) | 2020-06-11 |
| US10593563B2 (en) | 2020-03-17 |
| WO2018191380A1 (en) | 2018-10-18 |
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