TWI743136B - Engineered substrate structure for power and rf applications - Google Patents
Engineered substrate structure for power and rf applications Download PDFInfo
- Publication number
- TWI743136B TWI743136B TW106119602A TW106119602A TWI743136B TW I743136 B TWI743136 B TW I743136B TW 106119602 A TW106119602 A TW 106119602A TW 106119602 A TW106119602 A TW 106119602A TW I743136 B TWI743136 B TW I743136B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- shell
- adhesive
- single crystal
- epitaxial
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 130
- 230000004888 barrier function Effects 0.000 claims abstract description 56
- 239000000919 ceramic Substances 0.000 claims abstract description 32
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 239000010410 layer Substances 0.000 claims description 467
- 238000000034 method Methods 0.000 claims description 97
- 239000012790 adhesive layer Substances 0.000 claims description 83
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 81
- 230000008569 process Effects 0.000 claims description 55
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 52
- 229910052710 silicon Inorganic materials 0.000 claims description 50
- 239000010703 silicon Substances 0.000 claims description 50
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 45
- 239000000463 material Substances 0.000 claims description 45
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 31
- 229920005591 polysilicon Polymers 0.000 claims description 24
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 23
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 23
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 23
- 239000000853 adhesive Substances 0.000 claims description 17
- 230000001070 adhesive effect Effects 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 15
- 239000002356 single layer Substances 0.000 claims description 14
- 229910002601 GaN Inorganic materials 0.000 claims description 13
- 238000012546 transfer Methods 0.000 claims description 11
- 238000009499 grossing Methods 0.000 claims description 4
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims 3
- 239000012212 insulator Substances 0.000 claims 1
- 229910021419 crystalline silicon Inorganic materials 0.000 abstract 2
- 239000013078 crystal Substances 0.000 description 42
- 239000004065 semiconductor Substances 0.000 description 16
- 235000012431 wafers Nutrition 0.000 description 14
- 229910052782 aluminium Inorganic materials 0.000 description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 12
- 229910010293 ceramic material Inorganic materials 0.000 description 12
- 238000012986 modification Methods 0.000 description 12
- 230000004048 modification Effects 0.000 description 12
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 11
- 238000012545 processing Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- 238000006467 substitution reaction Methods 0.000 description 10
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 9
- 230000003746 surface roughness Effects 0.000 description 9
- 238000000137 annealing Methods 0.000 description 8
- 238000000151 deposition Methods 0.000 description 8
- 238000005538 encapsulation Methods 0.000 description 8
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 7
- 229910052796 boron Inorganic materials 0.000 description 7
- 239000004020 conductor Substances 0.000 description 7
- 238000005137 deposition process Methods 0.000 description 7
- 229910052739 hydrogen Inorganic materials 0.000 description 7
- 239000001257 hydrogen Substances 0.000 description 7
- 238000002513 implantation Methods 0.000 description 7
- 239000012535 impurity Substances 0.000 description 7
- 241000894007 species Species 0.000 description 7
- 229910052727 yttrium Inorganic materials 0.000 description 7
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 7
- OYPRJOBELJOOCE-UHFFFAOYSA-N Calcium Chemical compound [Ca] OYPRJOBELJOOCE-UHFFFAOYSA-N 0.000 description 6
- 229910052791 calcium Inorganic materials 0.000 description 6
- 239000011575 calcium Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 6
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 6
- 241000196324 Embryophyta Species 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 3
- 239000002253 acid Substances 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000004744 fabric Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 229910052594 sapphire Inorganic materials 0.000 description 3
- 239000010980 sapphire Substances 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 2
- 229910005191 Ga 2 O 3 Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 230000005693 optoelectronics Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000011573 trace mineral Substances 0.000 description 2
- 235000013619 trace mineral Nutrition 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000003750 conditioning effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000012792 core layer Substances 0.000 description 1
- 230000000875 corresponding effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000010943 off-gassing Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical class [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/14—Feed and outlet means for the gases; Modifying the flow of the reactive gases
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/18—Epitaxial-layer growth characterised by the substrate
- C30B25/183—Epitaxial-layer growth characterised by the substrate being provided with a buffer layer, e.g. a lattice matching layer
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02293—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/0242—Crystalline insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02491—Conductive materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02505—Layer structure consisting of more than two layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02595—Microstructure polycrystalline
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/3003—Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma
- H01L21/3006—Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma of AIIIBV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
- H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/16—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Inorganic Chemistry (AREA)
- Recrystallisation Techniques (AREA)
- Peptides Or Proteins (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
Description
本專利申請案主張於2016年6月14日提出申請、標題為「用於功率及RF應用的工程基板結構(ENGINEERED SUBSTRATE STRUCTURE FOR POWER AND RF APPLICATIONS)」的美國臨時專利申請案第62/350,084號及於2016年6月14日提出申請、標題為「工程基板結構及其製造方法(ENGINEERED SUBSTRATE STRUCTURE AND METHOD OF MANUFACTURE)」的美國臨時專利申請案第62/350,077號的優先權權益,為了所有的目的將該等申請案之揭示內容以引用方式全部併入本文中。 This patent application claims the U.S. Provisional Patent Application No. 62/350,084 filed on June 14, 2016, entitled "Engineered Substrate Structure for Power and RF Applications (ENGINEERED SUBSTRATE STRUCTURE FOR POWER AND RF APPLICATIONS)" And the priority rights of U.S. Provisional Patent Application No. 62/350,077, filed on June 14, 2016, entitled "Engineering Substance Structure and Method of Manufacturing", for all The purpose is to incorporate all the disclosures of these applications into this article by reference.
本發明大體而言係關於工程基板結構。更具體言之,本發明係關於適用於磊晶生長製程的方法和系統。 The present invention generally relates to engineering substrate structures. More specifically, the present invention relates to a method and system suitable for an epitaxial growth process.
發光二極體(LED)的結構通常是磊晶生長在藍寶石基板上。目前有許多產品使用LED元件,包括照明、電腦監視器及其他顯示裝置。 The structure of a light emitting diode (LED) is usually epitaxially grown on a sapphire substrate. Many products currently use LED components, including lighting, computer monitors and other display devices.
在藍寶石基板上生長氮化鎵系列LED結構是一種異質磊晶生長製程,因為基板和磊晶層是由不同的材料所組成。由於異質磊晶生長製程,磊晶生長的材料會表 現出各種不利的效果,包括降低均勻度及與磊晶層的電子/光學特性相關的度量降低。因此,所屬技術領域中需要有與磊晶生長製程和基板結構相關的改良方法和系統。 Growing a gallium nitride series LED structure on a sapphire substrate is a heterogeneous epitaxial growth process, because the substrate and the epitaxial layer are composed of different materials. Due to the heterogeneous epitaxial growth process, the material for epitaxial growth will show up Various undesirable effects have emerged, including reduced uniformity and reduced metrics related to the electronic/optical properties of the epitaxial layer. Therefore, there is a need for improved methods and systems related to the epitaxial growth process and substrate structure in the technical field.
本發明大體而言係關於工程基板結構。更具體言之,本發明係關於適用於磊晶生長製程的方法和系統。僅為舉例,本發明已被應用於提供適於磊晶生長的基板結構的方法和系統,該基板結構之特徵在於大體上與其上生長的磊晶層匹配的熱膨脹係數(CTE)。該等方法和技術可被應用於各式各樣的半導體處理操作。 The present invention generally relates to engineering substrate structures. More specifically, the present invention relates to a method and system suitable for an epitaxial growth process. For example only, the present invention has been applied to a method and system for providing a substrate structure suitable for epitaxial growth, the substrate structure being characterized by a coefficient of thermal expansion (CTE) substantially matching the epitaxial layer grown thereon. These methods and techniques can be applied to various semiconductor processing operations.
依據本發明之一實施例提供了一種基板。該基板包括支撐結構,該支撐結構包含:多晶陶瓷芯;耦接到該多晶陶瓷芯的第一黏合層;耦接到該第一黏合層的導電層;耦接到該導電層的第二黏合層;及耦接到該第二黏合層的阻障層。該基板還包括耦接到該支撐結構的氧化矽層、耦接到該氧化矽層的實質單晶矽層、以及耦接到該實質單晶矽層的磊晶III-V層。 According to an embodiment of the present invention, a substrate is provided. The substrate includes a support structure, the support structure including: a polycrystalline ceramic core; a first adhesive layer coupled to the polycrystalline ceramic core; a conductive layer coupled to the first adhesive layer; Two adhesive layers; and a barrier layer coupled to the second adhesive layer. The substrate further includes a silicon oxide layer coupled to the support structure, a substantial single crystal silicon layer coupled to the silicon oxide layer, and an epitaxial III-V layer coupled to the substantial single crystal silicon layer.
依據本發明之另一實施例提供了一種製造基板的方法。該方法包括藉由以下步驟形成支撐結構:提供多晶陶瓷芯;將該多晶陶瓷芯包封在第一黏合殼中;將該第一黏合殼包封在導電殼中;將該導電殼包封在第二黏合殼中;及將該第二黏合殼包封在阻障殼中。該方法還包括將結合層結合到該支撐結構、將實質單晶矽層結合到該結合層、藉由在該實質單晶矽層上磊晶生長而形成磊晶矽 層、以及藉由在該磊晶矽層上磊晶生長而形成磊晶III-V層。 According to another embodiment of the present invention, a method of manufacturing a substrate is provided. The method includes forming a supporting structure by the following steps: providing a polycrystalline ceramic core; encapsulating the polycrystalline ceramic core in a first adhesive shell; encapsulating the first adhesive shell in a conductive shell; encapsulating the conductive shell Sealed in a second adhesive shell; and encapsulated the second adhesive shell in a barrier shell. The method also includes bonding a bonding layer to the support structure, bonding a substantial single crystal silicon layer to the bonding layer, and forming epitaxial silicon by epitaxial growth on the substantial single crystal silicon layer And forming an epitaxial III-V layer by epitaxial growth on the epitaxial silicon layer.
依據本發明之一具體實施例提供了一種工程基板結構。該工程基板結構包括支撐結構、耦接到該支撐結構的結合層、耦接到該結合層的實質單晶矽層、以及耦接到該實質單晶矽層的磊晶單晶矽層。該支撐結構包括多晶陶瓷芯、耦接到該多晶陶瓷芯的第一黏合層、耦接到該第一黏合層的導電層、耦接到該導電層的第二黏合層、及耦接到該第二黏合層的阻障殼。 According to a specific embodiment of the present invention, an engineering substrate structure is provided. The engineering substrate structure includes a supporting structure, a bonding layer coupled to the supporting structure, a substantial single crystal silicon layer coupled to the bonding layer, and an epitaxial single crystal silicon layer coupled to the substantial single crystal silicon layer. The support structure includes a polycrystalline ceramic core, a first adhesive layer coupled to the polycrystalline ceramic core, a conductive layer coupled to the first adhesive layer, a second adhesive layer coupled to the conductive layer, and a coupling To the barrier shell of the second adhesive layer.
經由本發明實現了許多優於傳統技術的效益。例如,本發明的實施例提供CTE與適用於光學、電子及光電子應用的氮化鎵系列磊晶層匹配的工程基板結構。充當工程基板結構的組成部分的包封層阻止存在於基板中心部分內的雜質擴散到達使用工程基板的半導體處理環境。與基板材料相關的關鍵特性,包括熱膨脹係數、晶格不匹配、熱穩定性、及形狀控制被獨立設計用於改善(例如最佳化)與氮化鎵系列磊晶和元件層的匹配、以及與不同元件架構和效能目標的匹配。因為基板材料層在傳統的半導體製造製程中被整合在一起,所以簡化了製程整合。結合下文和附圖來更詳細地描述本發明的此等和其他實施例及其許多優點和特徵。 Through the present invention, many advantages over traditional technologies have been achieved. For example, the embodiment of the present invention provides an engineering substrate structure whose CTE is matched with a gallium nitride series epitaxial layer suitable for optical, electronic, and optoelectronic applications. The encapsulation layer, which serves as a component of the engineered substrate structure, prevents the impurities present in the central portion of the substrate from diffusing to reach the semiconductor processing environment in which the engineered substrate is used. The key characteristics related to the substrate material, including thermal expansion coefficient, lattice mismatch, thermal stability, and shape control are independently designed to improve (for example, optimize) the matching with the gallium nitride series epitaxial and component layers, and Matching with different component architectures and performance goals. Because the substrate material layers are integrated in the traditional semiconductor manufacturing process, the process integration is simplified. These and other embodiments of the present invention and its many advantages and features are described in more detail in conjunction with the following and the accompanying drawings.
100:工程基板 100: Engineering substrate
110:芯 110: core
112:第一黏合層 112: The first adhesive layer
114:導電層 114: conductive layer
116:第二黏合層 116: second adhesive layer
118:阻障層 118: Barrier Layer
120:結合層 120: Bonding layer
122:實質單晶矽層 122: Substantial single crystal silicon layer
130:磊晶材料 130: epitaxial material
300:工程基板 300: Engineering substrate
314:導電層 314: conductive layer
316:第二黏合層 316: second adhesive layer
317:平面 317: Plane
412:第一黏合層 412: first adhesive layer
414:導電層 414: conductive layer
416:第二黏合層 416: second adhesive layer
418:阻障層 418: Barrier Layer
500:方法 500: method
600:磊晶/工程基板結構 600: Epitaxy/engineered substrate structure
610:工程基板結構 610: Engineering substrate structure
620:矽磊晶層 620: silicon epitaxial layer
710:工程基板結構 710: Engineering substrate structure
720:III-V磊晶層 720: III-V epitaxial layer
724:通孔 724: Through hole
第1圖為圖示依據本發明之一實施例的工程基板結構之簡化示意圖。 FIG. 1 is a simplified schematic diagram illustrating the structure of an engineered substrate according to an embodiment of the present invention.
第2A圖為圖示依據本發明之一實施例工程結構的物種濃度為深度的函數之SIMS曲線。 Figure 2A is a SIMS curve illustrating the species concentration of an engineering structure as a function of depth according to an embodiment of the present invention.
第2B圖為圖示依據本發明之一實施例工程結構在退火之後的物種濃度為深度的函數之SIMS曲線。 Figure 2B is a SIMS curve illustrating the species concentration of an engineered structure as a function of depth after annealing according to an embodiment of the present invention.
第2C圖為圖示依據本發明之一實施例具有氮化矽層的工程結構在退火之後的物種濃度為深度的函數之SIMS曲線。 FIG. 2C is a SIMS curve illustrating the species concentration as a function of depth after annealing of an engineered structure with a silicon nitride layer according to an embodiment of the present invention.
第3圖為圖示依據本發明之另一實施例的工程基板結構之簡化示意圖。 FIG. 3 is a simplified schematic diagram illustrating the structure of an engineered substrate according to another embodiment of the present invention.
第4圖為圖示依據本發明之又另一實施例的工程基板結構之簡化示意圖。 FIG. 4 is a simplified schematic diagram illustrating the structure of an engineering substrate according to yet another embodiment of the present invention.
第5圖為圖示依據本發明之一實施例製造工程基板的方法之簡化流程圖。 FIG. 5 is a simplified flowchart illustrating a method of manufacturing an engineered substrate according to an embodiment of the present invention.
第6圖為圖示依據本發明之一實施例用於RF及功率應用的磊晶/工程基板結構之簡化示意圖。 FIG. 6 is a simplified schematic diagram illustrating an epitaxial/engineered substrate structure for RF and power applications according to an embodiment of the present invention.
第7圖為圖示依據本發明之一實施例在工程基板結構上的III-V磊晶層之簡化示意圖。 FIG. 7 is a simplified schematic diagram illustrating a III-V epitaxial layer on an engineering substrate structure according to an embodiment of the present invention.
第8圖為圖示依據本發明之另一實施例製造工程基板的方法之簡化流程圖。 FIG. 8 is a simplified flowchart illustrating a method of manufacturing an engineered substrate according to another embodiment of the present invention.
本發明之實施例係關於工程基板結構。更具體言之,本發明係關於適用於磊晶生長製程的方法和系統。僅為舉例,本發明已被應用於提供適於磊晶生長的基板結構的方法和系統,該基板結構之特徵在於大體上與其上生 長的磊晶層匹配的熱膨脹係數(CTE)。該等方法和技術可被應用於各式各樣的半導體處理操作。 The embodiment of the present invention relates to an engineered substrate structure. More specifically, the present invention relates to a method and system suitable for an epitaxial growth process. For example only, the present invention has been applied to a method and system for providing a substrate structure suitable for epitaxial growth. The substrate structure is The long epitaxial layer matches the coefficient of thermal expansion (CTE). These methods and techniques can be applied to various semiconductor processing operations.
第1圖為圖示依據本發明之一實施例的工程基板結構之簡化示意圖。第1圖圖示的工程基板100適用於各式各樣的電子和光學應用。工程基板包括芯110,芯110可以具有與將被生長在工程基板100上的磊晶材料之熱膨脹係數(CTE)大體上匹配的CTE。將磊晶材料130圖示為可選的,因為不需要磊晶材料130作為工程基板的元件,但磊晶材料130通常將生長在工程基板上。
FIG. 1 is a simplified schematic diagram illustrating the structure of an engineered substrate according to an embodiment of the present invention. The
對於包括氮化鎵(GaN)系列材料(包括GaN系列層的磊晶層)的生長的應用來說,芯110可以是多晶陶瓷材料,例如多晶氮化鋁(AlN),多晶氮化鋁(AlN)可以包括諸如氧化釔的結合材料。可以將其他材料用於芯110,包括多晶氮化鎵(GaN)、多晶氮化鎵鋁(AlGaN)、多晶碳化矽(SiC)、多晶氧化鋅(ZnO)、多晶三氧化鎵(Ga2O3)及類似物。
For applications including the growth of gallium nitride (GaN) series materials (including epitaxial layers of GaN series layers), the
芯的厚度可以在100μm至1,500μm的等級,例如725μm。芯110被包封在第一黏合層112中,可將第一黏合層112稱為殼或包封殼。在一實施例中,第一黏合層112包含厚度在1,000Å數量級的正矽酸四乙酯(TEOS)層。在其他實施例中,第一黏合層的厚度例如從100Å至2,000Å變化。儘管在一些實施例中將TEOS用於黏合層,但依據本發明之一實施例,可以利用其他材料在後續沉積層與下方層或材料(例如陶瓷,特別
是多晶陶瓷)之間提供黏合。例如,SiO2或其他矽氧化物(SixOy)良好地黏附於陶瓷材料,並提供用於後續沉積(例如導電材料)的適當表面。在一些實施例中,第一黏合層112完全包圍芯110以形成完全包封的芯,並且可以使用LPCVD製程形成第一黏合層112。第一黏合層112提供一個表面,後續層黏附於該表面上以形成工程基板結構的元件。
The thickness of the core may be on the order of 100 μm to 1,500 μm, for example, 725 μm. The
除了使用LPCVD製程、基於爐的製程等來形成包封的第一黏合層之外,依據本發明的實施例可以使用其他的半導體製程,包括CVD製程或類似的沉積製程。作為實例,可以使用塗覆芯的一部分的沉積製程、可以將芯翻轉、而且可以重複沉積製程來塗覆芯的其他部分。因此,儘管在一些實施例中使用LPCVD技術來提供完全包封的結構,但可以視特定應用使用其他的膜形成技術。 In addition to using LPCVD processes, furnace-based processes, etc., to form the encapsulated first adhesive layer, other semiconductor processes may be used according to embodiments of the present invention, including CVD processes or similar deposition processes. As an example, a deposition process that coats a part of the core can be used, the core can be turned over, and the deposition process can be repeated to coat other parts of the core. Therefore, although LPCVD technology is used in some embodiments to provide a fully encapsulated structure, other film formation technologies may be used depending on the specific application.
形成包圍黏合層112的導電層114。在一實施例中,導電層114是形成在第一黏合層112周圍的多晶矽(即多結晶矽)殼,因為多晶矽會對陶瓷材料表現出差的黏合。在其中導電層為多晶矽的實施例中,多晶矽層的厚度可以在500-5,000Å的數量級,例如2,500Å。在一些實施例中,可以將多晶矽層形成為完全包圍第一黏合層112(例如TEOS層)的殼,從而形成完全包封的第一黏合層,並且可以使用LPCVD製程形成。在其他實施例中,如以下所討論的,可以將導電材料形成在黏合層的一部分上,例如基板結構的下半部上。在一些實施例中,可
以將導電材料形成為完全包封層,並於隨後移除在基板結構的一側上的導電材料。
A
在一實施例中,導電層114可以是被摻雜以提供高導電材料的多晶矽層,例如摻雜硼以提供p型多晶矽層。在一些實施例中,用硼摻雜是在1×1019cm-3至1×1020cm-3的含量以提供高導電性。可以利用不同摻雜劑濃度的其他摻雜劑(例如,摻雜劑濃度範圍從1×1016cm-3至5×1018cm-3的磷、砷、鉍等)來提供適用於導電層的n型或p型半導體材料。所屬技術領域中具有通常知識者將認可許多的變化、修改及替代。
In one embodiment, the
在將工程基板靜電夾持於半導體處理工具(例如具有靜電夾盤(ESC)的工具)的過程中,導電層114的存在是有用的。在半導體處理工具中處理之後,導電層114能夠快速解除夾持。因此,本發明的實施例提供可被以傳統矽晶圓使用的方式處理的基板結構。所屬技術領域中具有通常知識者將認可許多的變化、修改及替代。
The presence of the
形成包圍導電層114的第二黏合層116(例如厚度在1000Å等級的TEOS層)。在一些實施例中,第二黏合層116完全包圍導電層114以形成完全包封的結構,並且可以使用LPCVD製程、CVD製程或任何其他適當的沉積製程形成,包括旋塗介電質的沉積。
A second adhesive layer 116 (for example, a TEOS layer with a thickness of 1000 Å) surrounding the
形成包圍第二黏合層116的阻障層118,例如氮化矽層。在一實施例中,阻障層118係厚度在2,000Å至5,000Å數量級的氮化矽層118。在一些實施例中,阻
障層118完全包圍第二黏合層116以形成完全包封的結構,並且可以使用LPCVD製程形成。除了氮化矽層之外,可以使用非晶形材料(包括SiCN、SiON、AlN、SiC等)作為阻障層。在一些實施方案中,阻障層118包含被建造以形成阻障層的數個子層。因此,用語阻障層無意表示單層或單一材料,而是涵括以複合方式分層的一種或更多種材料。所屬技術領域中具有通常知識者將認可許多的變化、修改及替代。
A
在一些實施例中,阻障層118(例如氮化矽層)防止存在於芯110內的元素(例如釔氧化物(即氧化釔)、氧、金屬雜質、其他微量元素等)擴散及/或出氣進入其中可能存在工程基板的半導體處理腔室的環境中,例如在高溫(例如1,000℃)磊晶生長製程期間。利用本文所述的包封層,可以在半導體製程流程和潔淨室環境中使用陶瓷材料,包括為非潔淨室環境設計的多晶AlN。 In some embodiments, the barrier layer 118 (such as a silicon nitride layer) prevents elements (such as yttrium oxide (ie, yttrium oxide), oxygen, metal impurities, other trace elements, etc.) present in the core 110 from diffusing and/or The outgas enters the environment of the semiconductor processing chamber where the engineered substrate may be present, for example, during a high temperature (for example, 1,000° C.) epitaxial growth process. With the encapsulation layer described herein, ceramic materials can be used in semiconductor manufacturing processes and clean room environments, including polycrystalline AlN designed for non-clean room environments.
第2A圖為圖示依據本發明之一實施例工程結構的物種濃度為深度的函數之二次離子質譜(SIMS)曲線。該工程結構不包括阻障層118。參照第2A圖,存在於陶瓷芯中的幾種物種(例如釔、鈣及鋁)在工程層120/122中降至可忽略的濃度。鈣、釔及鋁的濃度分別下降了三個、四個及六個數量級。
Figure 2A is a secondary ion mass spectrometry (SIMS) curve illustrating the species concentration of an engineering structure as a function of depth according to an embodiment of the present invention. The engineering structure does not include the
第2B圖為圖示依據本發明之一實施例沒有阻障層的工程結構在退火之後的物種濃度為深度的函數之SIMS曲線。如以上所討論的,在半導體處理操作期間, 例如在GaN系列層的磊晶生長期間,由本發明的實施例提供的工程基板結構可暴露於高溫(~1,100℃)幾個小時。 FIG. 2B is a SIMS curve illustrating the species concentration as a function of depth after annealing of an engineered structure without a barrier layer according to an embodiment of the present invention. As discussed above, during semiconductor processing operations, For example, during the epitaxial growth of a GaN series layer, the engineered substrate structure provided by the embodiment of the present invention can be exposed to a high temperature (~1,100° C.) for several hours.
對於第2B圖圖示的曲線來說,工程基板結構在1,100℃下退火4小時。如第2B圖所示,原始以低濃度存在於剛沉積好未經處理的樣品中的鈣、釔及鋁已經擴散到工程層中,達到與其它元素相似的濃度。 For the curve shown in Figure 2B, the engineered substrate structure was annealed at 1,100°C for 4 hours. As shown in Figure 2B, the calcium, yttrium, and aluminum originally present in the freshly deposited untreated sample at low concentrations have diffused into the engineering layer to reach concentrations similar to other elements.
第2C圖為圖示依據本發明之一實施例具有阻障層的工程結構在退火之後的物種濃度為深度的函數之SIMS曲線。將擴散阻障層118(例如氮化矽層)整合到工程基板結構中防止了當擴散阻障層不存在時會發生的鈣、釔及鋁在退火製程期間擴散到工程層中。如第2C圖所圖示,退火之後,存在於陶瓷芯中的鈣、釔及鋁在工程層中保持低濃度。因此,使用阻障層118(例如氮化矽層)可防止此等元素擴散通過擴散阻障層,從而防止此等元素釋放到工程基板周圍的環境中。類似地,塊體陶瓷材料中所含的任何其它雜質亦將被阻障層遏制。 FIG. 2C is a SIMS curve illustrating the species concentration as a function of depth after annealing of an engineered structure with a barrier layer according to an embodiment of the present invention. Integrating the diffusion barrier layer 118 (such as a silicon nitride layer) into the engineering substrate structure prevents calcium, yttrium, and aluminum, which would occur when the diffusion barrier layer is not present, from diffusing into the engineering layer during the annealing process. As shown in Figure 2C, after annealing, the calcium, yttrium, and aluminum present in the ceramic core remain low in the engineered layer. Therefore, the use of the barrier layer 118 (such as a silicon nitride layer) can prevent these elements from diffusing through the diffusion barrier layer, thereby preventing these elements from being released into the environment around the engineering substrate. Similarly, any other impurities contained in the bulk ceramic material will also be contained by the barrier layer.
通常,用於形成芯110的陶瓷材料係在1800℃範圍中的溫度下焙燒。可預期此製程將驅除存在於陶瓷材料中的大量雜質。此等雜質可以包括由於使用氧化釔作為燒結劑所生成的釔、鈣及其他元素和化合物。隨後,在800℃至1100℃範圍內的遠較低溫度下進行的磊晶生長製程期間,可預期此等雜質的後續擴散將是不明顯的。然而,與傳統的預期相反,本發明人確定的是,即使在遠
比陶瓷材料的焙燒溫度更低的溫度下的磊晶生長製程期間也會發生元素大量擴散通過工程基板的層。因此,本發明的實施例整合阻障層118(例如氮化矽層)來防止背景元素從多晶陶瓷材料(例如AlN)向外擴散到工程層120/122和磊晶層(例如可選的GaN層130)中。包封下方的層和材料的氮化矽層118提供期望的阻障層功能。
Generally, the ceramic material used to form the
如第2B圖所圖示,原始存在於芯110中的元素(包括釔)擴散進入並通過第一TEOS層112、多晶矽層114、及第二TEOS層116。然而,氮化矽層118的存在可防止此等元素擴散通過氮化矽層,從而防止此等元素釋放到工程基板周圍的環境中,如第2C圖所圖示。
As shown in FIG. 2B, elements (including yttrium) originally present in the
再次參照第1圖,在阻障層118的一部分(例如阻障層的頂部表面)上沉積結合層120(例如氧化矽層),並且隨後在實質單晶矽層122的結合過程中使用結合層120。在一些實施例中,結合層120的厚度可以為約1.5μm。
Referring again to FIG. 1, a bonding layer 120 (for example, a silicon oxide layer) is deposited on a part of the barrier layer 118 (for example, the top surface of the barrier layer), and then the bonding layer is used in the bonding process of the substantial single
實質單晶層122適用於在磊晶生長製程期間用作生長層,用於形成磊晶材料130。在一些實施例中,磊晶材料130包括厚度2μm至10μm的GaN層,GaN層可被用作光電子元件、RF元件、功率元件等使用的複數個層中的一個層。在一實施例中,實質單晶層122包括使用層轉移製程附接到氧化矽層118的實質單晶矽層。
The substantial
第3圖為圖示依據本發明之一實施例的工程基板結構之簡化示意圖。第3圖圖示的工程基板300適用
於各式各樣的電子和光學應用。工程基板包括芯110,芯110可以具有與將被生長在工程基板300上的磊晶材料130之熱膨脹係數(CTE)大體上匹配的CTE。將磊晶材料130圖示為可選的,因為不需要磊晶材料130作為工程基板的元件,但磊晶材料130通常將被生長在工程基板上。
FIG. 3 is a simplified schematic diagram illustrating the structure of an engineered substrate according to an embodiment of the present invention. The
對於包括氮化鎵(GaN)系列材料(包括GaN系列層的磊晶層)的生長的應用來說,芯110可以是多晶陶瓷材料,例如多晶氮化鋁(AlN)。芯的厚度可以在100μm至1,500μm的等級,例如725μm。芯110被包封在第一黏合層112中,可將第一黏合層112稱為殼或包封殼。在此實施方案中,第一黏合層112將芯完全包封,但此舉並非本發明要求的,如關於第4圖另外詳細討論的。
For applications including the growth of gallium nitride (GaN) series materials (including epitaxial layers of GaN series layers), the
在一實施例中,第一黏合層112包含厚度在1,000Å數量級的正矽酸四乙酯(TEOS)層。在其他實施例中,第一黏合層的厚度例如從100Å至2,000Å變化。儘管在一些實施例中將TEOS用於黏合層,但依據本發明之一實施例,可以利用其他材料在後續沉積層與下方層或材料之間提供黏合。例如,SiO2、SiON及類似物良好地黏附於陶瓷材料,並提供用於後續沉積(例如導電材料)的適當表面。在一些實施例中,第一黏合層112完全包圍芯110以形成完全包封的芯,並且可以使用
LPCVD製程形成第一黏合層112。黏合層提供一個表面,後續層黏附於該表面上以形成工程基板結構的元件。
In one embodiment, the
除了使用LPCVD製程、基於爐的製程等來形成包封的黏合層之外,依據本發明的實施例可以使用其他的半導體製程。作為實例,可以使用塗覆芯的一部分的沉積製程(例如CVD、PECVD、或類似製程)、可以將芯翻轉、而且可以重複沉積製程來塗覆芯的其他部分。 In addition to using an LPCVD process, a furnace-based process, etc., to form the encapsulated adhesive layer, other semiconductor processes can be used according to the embodiments of the present invention. As an example, a deposition process that coats a part of the core (such as CVD, PECVD, or similar processes) can be used, the core can be turned over, and the deposition process can be repeated to coat other parts of the core.
在第一黏合層112的至少一部分上形成導電層314。在一實施例中,導電層314包括藉由沉積製程形成在芯/黏合層結構之下部(例如下半部或背側)上的多晶矽(即多結晶矽)。在其中導電層為多晶矽的實施例中,多晶矽層的厚度可以在幾千埃的數量級,例如3,000Å。在一些實施例中,可以使用LPCVD製程形成多晶矽層。
A
在一實施例中,導電層314可以是被摻雜以提供高導電材料的多晶矽層,例如導電層314可被摻雜硼以提供p型多晶矽層。在一些實施例中,用硼摻雜是在範圍從約1×1019cm-3至1×1020cm-3的含量以提供高導電性。在將工程基板靜電夾持於半導體處理工具(例如具有靜電夾盤(ESC)的工具)的過程中,導電層的存在是有用的。在處理之後導電層314能夠快速解除夾持。因此,本發明的實施例提供可被以傳統矽晶圓使用的方式處理的基板結構。所屬技術領域中具有通常知識者將認可許多的變化、修改及替代。
In one embodiment, the
形成包圍導電層314(例如多晶矽層)的第二黏合層316(例如第二TEOS層)。第二黏合層316的厚度在1,000Å的數量級。在一些實施例中,第二黏合層316可以完全包圍導電層314以及第一黏合層112以形成完全包封的結構,並且可以使用LPCVD製程形成。在其他實施例中,第二黏合層316僅部分包圍導電層314,例如在平面317圖示的位置終止,平面317可對齊導電層314的頂部表面。在此實例中,導電層314的頂部表面將與阻障層118的一部分接觸。所屬技術領域中具有通常知識者將認可許多的變化、修改及替代。
A second adhesion layer 316 (for example, a second TEOS layer) surrounding the conductive layer 314 (for example, a polysilicon layer) is formed. The thickness of the second
形成包圍第二黏合層316的阻障層118(例如氮化矽層)。在一些實施例中,阻障層118的厚度在4,000Å至5,000Å的數量級。在一些實施例中,阻障層118完全包圍第二黏合層316以形成完全包封的結構,並且可以使用LPCVD製程形成。
A barrier layer 118 (such as a silicon nitride layer) surrounding the
在一些實施例中,使用氮化矽阻障層防止存在於芯110內的元素(例如釔氧化物(即氧化釔)、氧、金屬雜質、其他微量元素等)擴散及/或出氣進入其中可能存在工程基板的半導體處理腔室的環境中,例如在高溫(例如1,000℃)磊晶生長製程期間。利用本文所述的包封層,可以在半導體製程流程和潔淨室環境中使用陶瓷材料,包括為非潔淨室環境設計的多晶AlN。 In some embodiments, a silicon nitride barrier layer is used to prevent elements (such as yttrium oxide (ie, yttrium oxide), oxygen, metal impurities, other trace elements, etc.) present in the core 110 from diffusing and/or outgassing into it. Exist in the environment of the semiconductor processing chamber of the engineered substrate, for example, during the high temperature (for example, 1,000° C.) epitaxial growth process. With the encapsulation layer described herein, ceramic materials can be used in semiconductor manufacturing processes and clean room environments, including polycrystalline AlN designed for non-clean room environments.
第4圖為圖示依據本發明之另一實施例的工程基板結構之簡化示意圖。在第4圖圖示的實施例中,第
一黏合層412被形成在芯110的至少一部分上、但不包封芯110。在此實施方案中,第一黏合層412被形成在芯110的下表面(芯110的背側)上以增強隨後形成的導電層414的黏合,如以下更充分描述的。儘管第4圖僅將黏合層412圖示在芯110的下表面上,但將理解的是,將黏合層材料沉積在芯的其它部分上將不會不利地影響工程基板結構的效能,而且此類材料可以存在於各種實施例中。所屬技術領域中具有通常知識者將認可許多的變化、修改及替代。
FIG. 4 is a simplified schematic diagram illustrating the structure of an engineered substrate according to another embodiment of the present invention. In the embodiment illustrated in Figure 4, the first
An
導電層414不包封第一黏合層412和芯110,而是大體上與第一黏合層412對齊。儘管導電層414被圖示為沿著第一黏合層412的底部或背側延伸並沿著第一黏合層412的側面的一部分向上延伸,但沿著垂直側面延伸並非本發明要求的。因此,實施例可以利用基板結構一側上的沉積、基板結構一側的掩蔽等。導電層414可以被形成在第一黏合層412的一側(例如底部/背側)的一部分上。導電層414在工程基板結構的一側上提供電傳導,此舉在RF和高功率的應用中會是有利的。導電層可以包括關於第1圖中的導電層114討論的摻雜多晶矽。
The
芯110的一部分、第一黏合層412的多個部分、及導電層414被第二黏合層416覆蓋,以便增強阻障層418與下方材料的黏合。如以上所討論的,阻障層418形成包封結構以防止來自下方層的擴散。
A part of the
除了半導體系列導電層之外,在其他實施例中,導電層414為金屬層,例如500Å的鈦或類似物。
In addition to the semiconductor series conductive layer, in other embodiments, the
再次參照第4圖,視實施方案而定,可以移除一個或更多個層。例如,可以移除層412和414,僅留下單黏合殼416和阻障層418。在另一個實施例中,可以僅移除層414。在此實施例中,層412還可以平衡由沉積在層418的頂部上的層120引起的應力和晶圓彎曲。在芯110的頂側上具有絕緣層的基板結構(例如在芯110與層120之間僅有絕緣層)的建造將為功率/RF應用(其中需要高度絕緣的基板)提供益處。
Referring again to Figure 4, depending on the implementation, one or more layers may be removed. For example, the
在另一個實施例中,阻障層418可以直接包封芯110,隨後是導電層414和隨後的黏合層416。在此實施例中,層120可以從頂側直接沉積到黏合層416上。在又另一個實施例中,黏合層416可以沉積在芯110上,隨後是阻障層418,然後是導電層414和另一個黏合層412。
In another embodiment, the
儘管已經關於層討論了一些實施例,但用語層應被理解為使得層可以包括被建造以形成感興趣層的若干子層。因此,用語層無意表示由單一材料所組成的單層,而是涵括以複合方式分層以形成所需結構的一種或更多種材料。所屬技術領域中具有通常知識者將認可許多的變化、修改及替代。 Although some embodiments have been discussed with respect to layers, the term layer should be understood such that a layer may include several sublayers that are built to form a layer of interest. Therefore, the term layer is not intended to mean a single layer composed of a single material, but encompasses one or more materials layered in a composite manner to form a desired structure. Those with ordinary knowledge in the technical field will recognize many changes, modifications and substitutions.
第5圖為圖示依據本發明之一實施例製造工程基板的方法之簡化流程圖。該方法可用於製造與在基板
上生長的一個或更多個磊晶層CTE匹配的基板。方法500包括藉由提供多晶陶瓷芯(510)、將該多晶陶瓷芯包封在第一黏合層中而形成殼(例如正矽酸四乙酯(TEOS)殼)(512)、以及將該第一黏合層包封在導電殼(例如多晶矽殼)中(514)而形成支撐結構。可將該第一黏合層形成為TEOS的單層。可將該導電殼形成為多晶矽的單層。
FIG. 5 is a simplified flowchart illustrating a method of manufacturing an engineered substrate according to an embodiment of the present invention. This method can be used to manufacture
One or more epitaxial layers grown on a CTE-matched substrate. The
該方法還包括將該導電殼包封在第二黏合層(例如第二TEOS殼)中(516),並將第二黏合層包封在阻障層殼中(518)。可以將第二黏合層形成為TEOS的單層。可以將阻障層殼形成為氮化矽的單層。 The method further includes encapsulating the conductive shell in a second adhesive layer (for example, a second TEOS shell) (516), and encapsulating the second adhesive layer in a barrier layer shell (518). The second adhesive layer may be formed as a single layer of TEOS. The barrier layer shell can be formed as a single layer of silicon nitride.
一旦藉由製程510-518形成了支撐結構,該方法還包括將結合層(例如氧化矽層)結合於支撐結構(520),並將實質單晶層(例如實質單晶矽層)結合於氧化矽層(522)。依據本發明的實施例,可以使用其他的實質單晶層,包括SiC、藍寶石、GaN、AlN、SiGe、Ge、金剛石、Ga2O3、ZnO等。結合層的結合可以包括沉積結合材料,隨後執行如本文所述之平坦化製程。在如下所述的實施例中,將實質單晶層(例如實質單晶矽層)連接於結合層係使用層轉移製程,其中該實質單晶層係自矽晶圓轉移的單晶矽層。 Once the supporting structure is formed by the processes 510-518, the method further includes bonding a bonding layer (such as a silicon oxide layer) to the supporting structure (520), and bonding a substantial single crystal layer (such as a substantial single crystal silicon layer) to the oxide Silicon layer (522). According to the embodiment of the present invention, other substantial single crystal layers may be used, including SiC, sapphire, GaN, AlN, SiGe, Ge, diamond, Ga 2 O 3 , ZnO, etc. The bonding of the bonding layer may include depositing a bonding material, and then performing a planarization process as described herein. In the embodiments described below, a layer transfer process is used to connect the substantial single crystal layer (such as a substantial single crystal silicon layer) to the bonding layer, wherein the substantial single crystal layer is a single crystal silicon layer transferred from a silicon wafer.
參照第1圖,結合層120可以藉由沉積厚的(例如4μm厚)氧化物層隨後進行化學機械拋光(CMP)製程以將氧化物薄化至厚度約1.5μm來形成。厚的初始氧
化物用以填充存在於支撐結構上的空隙和表面特徵,該等空隙和表面特徵可能在製造多晶芯之後存在,並在形成第1圖圖示的包封層時繼續存在。CMP製程提供沒有空隙、顆粒或其他特徵的大體平坦表面,隨後可以在晶圓轉移製程期間使用該平坦表面來將實質單晶層122(例如實質單晶矽層)結合於結合層120。將理解的是,結合層120之特徵不必在於原子級平坦的表面,而是應提供將以期望的可靠度支撐結合實質單晶層(例如實質單晶矽層)的大體平坦表面。
Referring to FIG. 1, the
可以使用層轉移製程來將實質單晶矽層122結合於結合層120。在一些實施例中,矽晶圓(例如矽(111)晶圓)被佈植而形成分裂面。在晶圓結合之後,矽基板可與分裂面下方的單晶矽層部分一起被移出,從而產生第1圖圖示的剝離單晶矽層122。可以改變實質單晶層122的厚度來滿足各種應用的規格。此外,可以改變實質單晶層122的晶體方向來滿足應用的規格。另外,可以改變實質單晶層122中的摻雜水平和分佈來滿足特定應用的規格。
A layer transfer process can be used to bond the substantially single
第5圖圖示的方法還可以包括光滑化實質單晶層(524)。在一些實施例中,可以修改實質單晶層122的厚度和表面粗糙度獲得高品質的磊晶生長。關於實質單晶層122的厚度和表面光滑度,不同的元件應用可以具有略微不同的規格。分裂製程使實質單晶層122在佈植離子分佈的峰值處從塊體單晶矽晶圓分層。在分裂之後,實質
單晶層122可以在幾個方面進行調整或修改,然後用作其他材料(例如氮化鎵)的磊晶生長的生長表面。
The method illustrated in Figure 5 may further include smoothing the substantial single crystal layer (524). In some embodiments, the thickness and surface roughness of the substantial
第一,轉移的實質單晶層122可能含有少量的殘餘氫濃度,並且可能具有來自佈植物的一些晶體損傷。因此,移除轉移的實質單晶層122中晶格受損的薄部分可能是有益的。在一些實施例中,可以將佈植物的深度調整為大於實質單晶層122的期望最終厚度。額外的厚度允許移除轉移的實質單晶層被損壞的薄的部分,從而留下所需最終厚度的未損傷部分。
First, the transferred substantial
第二,可能需要調整實質單晶層122的總厚度。一般來說,可能希望使實質單晶層122足夠厚以提供高品質的晶格模板用於隨後生長一個或更多個磊晶層、但又足夠薄以具有高度順應性。當實質單晶層122相對較薄時,可以將實質單晶層122稱為「順應的」,使得實質單晶層122的物理性質較不受限並能夠模擬周圍材料的物理性質,且產生結晶缺陷的傾向較低。實質單晶層122的順應性可與實質單晶層122的厚度成反比。較高的順應性可在模板上生長的磊晶層中產生較低的缺陷密度,並能夠生長較厚的磊晶層。在一些實施例中,可以藉由在剝離的矽層上磊晶生長矽來增加實質單晶層122的厚度。
Second, the total thickness of the substantial
第三,提高實質單晶層122的光滑度可能是有益的。層的光滑度可能與總氫劑量、任何共佈植物種的存在、以及用以形成氫基分裂面的退火條件相關。從層轉移
(即分裂步驟)產生的初始粗糙度可以藉由熱氧化和氧化物剝除來減小,如以下所討論的。
Third, it may be beneficial to improve the smoothness of the substantial
在一些實施例中,移除損傷層並調整實質單晶層122的最終厚度可以透過熱氧化剝離矽層的頂部部分、隨後使用氟化氫(HF)酸進行氧化物層剝除來實現。例如,可以將初始厚度為0.5μm的剝離矽層熱氧化以產生約420nm厚的二氧化矽層。移除生長的熱氧化物之後,轉移層中剩餘的矽厚度可以為約53nm。在熱氧化期間,佈植的氫可能往表面遷移。因此,隨後的氧化物層剝除可以移除一些損傷。並且,熱氧化通常在1000℃或更高的溫度下進行。升高的溫度也可以修復晶格損傷。
In some embodiments, removing the damaged layer and adjusting the final thickness of the substantial
在熱氧化期間形成在實質單晶層的頂部部分上的氧化矽層可以使用HF酸蝕刻剝除。可以藉由調整HF溶液的溫度和濃度以及氧化矽的化學計量和密度來調整HF酸對氧化矽和矽(SiO2:Si)的蝕刻選擇率。蝕刻選擇率是指一種材料相對於另一種材料的蝕刻速率。HF溶液對於(SiO2:Si)的選擇率可以在約10:1至約100:1的範圍內。高的蝕刻選擇率可以藉由與初始表面粗糙度相似的因子來降低表面粗糙度。然而,所得實質單晶層122的表面粗糙度仍可能大於所需的。例如,在附加處理之前藉由2μm×2μm原子力顯微鏡(AFM)掃描測定,塊體Si(111)表面可能具有小於0.1nm的均方根(RMS)表面粗糙度。在一些實施例中,在Si(111)上磊晶生長氮化鎵材料所需的表面粗糙度可以例如為在
30μm×30μm的AFM掃描區域上小於1nm、小於0.5nm、或小於0.2nm。
The silicon oxide layer formed on the top portion of the substantial single crystal layer during thermal oxidation can be stripped off using HF acid etching. The etching selectivity of HF acid to silicon oxide and silicon (SiO 2 :Si) can be adjusted by adjusting the temperature and concentration of the HF solution and the stoichiometry and density of silicon oxide. Etching selectivity refers to the etch rate of one material relative to another. The selectivity of the HF solution to (SiO 2 :Si) may be in the range of about 10:1 to about 100:1. The high etching selectivity can reduce the surface roughness by a factor similar to the initial surface roughness. However, the resulting surface roughness of the substantial
假使實質單晶層122在熱氧化和氧化物層剝除之後的表面粗糙度超過所需的表面粗糙度,則可以進行另外的表面光滑化。有幾種將矽表面光滑化的方法。此等方法可以包括氫退火、雷射修整、電漿光滑化、及接觸拋光(例如化學機械拋光或CMP)。此等方法可能涉及優先侵蝕高深寬比的表面峰。因此,表面上的高深寬比特徵可以比低深寬比特徵更快被移除,從而產生更光滑的表面。
If the surface roughness of the substantial
應當理解的是,第5圖圖示的具體步驟提供了依據本發明之一實施例製造工程基板的特定方法。還可以依據替代實施例來執行其他的步驟順序。例如,本發明的替代實施例可以以不同的順序執行上述步驟。此外,第5圖圖示的各個步驟可以包括可以單個步驟適合的各種順序執行的多個子步驟。此外,可以視具體應用來添加或移除附加步驟。所屬技術領域中具有通常知識者將認可許多的變化、修改及替代。 It should be understood that the specific steps illustrated in FIG. 5 provide a specific method for manufacturing an engineered substrate according to an embodiment of the present invention. Other sequence of steps can also be performed according to alternative embodiments. For example, alternative embodiments of the present invention may perform the above steps in a different order. In addition, each step illustrated in FIG. 5 may include a plurality of sub-steps that can be executed in various orders where a single step fits. In addition, additional steps can be added or removed depending on the specific application. Those with ordinary knowledge in the technical field will recognize many changes, modifications and substitutions.
第6圖為圖示依據本發明之一實施例用於RF及功率應用的磊晶/工程基板結構之簡化示意圖。在一些LED應用中,工程基板結構提供能夠生長高品質GaN層的生長基板,而且隨後移出工程基板結構。然而,對於RF和功率元件的應用來說,工程基板結構形成完成元件 的某些部分,結果,工程基板結構或工程基板結構的元件的電、熱及其它特性對於特定應用是重要的。 FIG. 6 is a simplified schematic diagram illustrating an epitaxial/engineered substrate structure for RF and power applications according to an embodiment of the present invention. In some LED applications, the engineered substrate structure provides a growth substrate capable of growing high-quality GaN layers, and then the engineered substrate structure is removed. However, for the application of RF and power components, the engineered substrate structure forms a complete component As a result, the electrical, thermal, and other characteristics of the engineered substrate structure or the components of the engineered substrate structure are important for specific applications.
參照第1圖,單晶矽層122通常是利用佈植和剝離技術從矽施體晶圓分離的剝離層。典型的佈植物是氫和硼。對於功率和RF元件的應用來說,工程基板結構中的層和材料的電性質是重要的。例如,一些元件架構使用電阻大於103Ohm-cm的高絕緣矽層來減少或消除透過基板和界面層的洩漏。其他的應用利用包括具有預定厚度(例如1μm)的導電矽層的設計,以將元件的源極連接到其它元件。因此,在這些應用中,希望可控制單晶矽層的尺寸和效能。在其中於層轉移期間使用佈植和剝離技術的設計中,殘餘佈植原子(例如氫或硼)存在於矽層中,從而改變電特性。另外,利用例如佈植劑量的調整來控制薄矽層的厚度、導電性及其它特性會是困難的,佈植劑量的調整會影響導電性以及佈植物分佈的半高寬(FWHM)、表面粗糙度、及分裂面位置精度、以及可能影響層厚度的佈植深度。
Referring to FIG. 1, the single
依據本發明的實施例,利用在工程基板結構上的矽磊晶來實現單晶矽層適於特定元件設計的期望特性。 According to the embodiment of the present invention, the silicon epitaxy on the engineering substrate structure is used to realize the desired characteristics of the single crystal silicon layer suitable for specific device design.
參照第6圖,磊晶/工程基板結構600包括工程基板結構610和形成在工程基板結構610上的矽磊晶層620。工程基板結構610可以類似於第1圖、第3圖、及第4圖圖示的工程基板結構。通常,在層轉移之後,實質單晶矽層122在0.5μm的等級。在一些製程中,可以使用
表面調理製程來將單晶矽層122的厚度減小到約0.3μm。為了將單晶矽層的厚度增加到約1μm以用於製造例如可靠的歐姆接觸,使用磊晶製程在由層轉移製程形成的實質單晶矽層122上生長磊晶單晶矽層620。可以使用各種磊晶生長製程來生長磊晶單晶矽層620,包括CVD、ALD、MBE等。磊晶單晶矽層620的厚度可以在約0.1μm至約20μm的範圍內,例如介於0.1μm和10μm之間。
Referring to FIG. 6, the epitaxial/engineered
第7圖為圖示依據本發明之一實施例在工程基板結構上的III-V磊晶層之簡化示意圖。如下所述,可以將第7圖圖示的結構稱為雙磊晶結構。如第7圖所圖示,包括磊晶單晶矽層620的工程基板結構710具有形成在其上的III-V磊晶層720。在一實施例中,III-V磊晶層包含氮化鎵(GaN)。
FIG. 7 is a simplified schematic diagram illustrating a III-V epitaxial layer on an engineering substrate structure according to an embodiment of the present invention. As described below, the structure illustrated in Figure 7 can be referred to as a double epitaxial structure. As shown in FIG. 7, the
取決於所需的功能,III-V磊晶層720的期望厚度可以變化很大。在一些實施例中,III-V磊晶層720的厚度可以在0.5μm與100μm之間變化,例如厚度大於5μm。在III-V磊晶層720上製造的元件的所得崩潰電壓可以視III-V磊晶層720的厚度而改變。一些實施例提供至少100V、300V、600V、1.2kV、1.7kV、3.3kV、5.5kV、13kV、或20kV的崩潰電壓。
Depending on the desired function, the desired thickness of the III-
為了在可以包括多個子層的III-V磊晶層720的某些部分之間提供導電性,在此實例中形成從III-V磊晶層720的頂部表面通入磊晶單晶矽層620的
一組通孔724。通孔724可以襯有絕緣層(未圖示),使得通孔724與III-V磊晶層720絕緣。作為實例,可以藉由提供穿過通孔的歐姆接觸而使用此等通孔來將二極體或電晶體的電極連接到下方的矽層,從而緩和元件中的電荷積累。
In order to provide conductivity between certain portions of the III-
假使在單晶矽層122上生長III-V磊晶層,則穿過通孔獲得此類歐姆接觸會是困難的,因為在單晶矽層122中終止通孔蝕刻將是困難的:例如可靠地在整個晶圓上蝕穿5μm的GaN,並在0.3μm的矽層中終止蝕刻。利用本發明的實施例可以提供厚度幾微米的單晶矽層,此舉在使用佈植和剝離製程之下是困難的,因為實現大的佈植深度需要高的佈植能量。接著,厚的矽層致能諸如能夠實現各式各樣元件設計的所說明通孔的應用。
If a III-V epitaxial layer is grown on the single
除了藉由在單晶矽層122上磊晶生長單晶矽層620來增加矽「層」的厚度之外,可以對單晶矽層122的原始特性進行其它調整,包括導電性、結晶度等的修改。例如,假使在另外磊晶生長III-V層或其它材料之前需要在10μm數量級的矽層,則可以依據本發明的實施例生長此類厚層。
In addition to increasing the thickness of the silicon "layer" by epitaxially growing the single
因為佈植製程會影響單晶矽層122的性質,例如殘餘的硼/氫原子會影響矽的電性質,故本發明的實施例在磊晶生長單晶矽層620之前移除一部分的單晶矽層122。例如,可以將單晶矽層122薄化以形成厚度0.1μm或更薄的層,從而移除大部分或所有的殘餘硼/氫原子。
然後使用隨後生長的單晶矽層620來提供電及/或其它性質基本上與使用層轉移製程形成的層的相應性質無關的單晶材料。
Because the implantation process affects the properties of the single
除了增加耦接到工程基板結構的單晶矽材料的厚度之外,磊晶單晶矽層620的電性質(包括導電性)可以不同於單晶矽層122的電性質。在生長期間摻雜磊晶單晶矽層620可以藉由使用硼摻雜來產生p型矽,並藉由使用磷摻雜來產生n型矽。可以生長未摻雜的矽以提供在具有絕緣區域的元件中使用的高電阻率矽。尤其,可將絕緣層用於RF元件。
In addition to increasing the thickness of the single crystal silicon material coupled to the engineered substrate structure, the electrical properties (including conductivity) of the epitaxial single
可以在生長期間調整磊晶單晶矽層620的晶格常數以改變單晶矽層122的晶格常數而產生應變的磊晶材料。除了矽之外,還可以磊晶生長其它元素來提供層,包括含有矽鍺的應變層或類似物。例如,可以在單晶矽層122上、磊晶單晶矽層620上、或層之間生長緩衝層,以增強隨後的磊晶生長。此等緩衝層可以包括應變III-V層、矽鍺應變層等。另外,緩衝層和其它磊晶層可以以莫耳分率、摻雜劑、極性等分級。所屬技術領域中具有通常知識者將認可許多的變化、修改及替代。
The lattice constant of the epitaxial single
在一些實施例中,存在於單晶矽層122或磊晶單晶矽層620中的應變可以在後續磊晶層(包括III-V磊晶層)的生長期間被鬆弛。
In some embodiments, the strain existing in the single
第8圖為圖示依據本發明之另一實施例製造工程基板的方法之簡化流程圖。該方法包括藉由提供多晶 陶瓷芯(810)、形成耦接到該多晶陶瓷芯的至少一部分的第一黏合層(812)來形成支撐結構。該第一黏合層可以包括正矽酸四乙酯(TEOS)層。該方法還包括形成耦接到該第一黏合層的導電層(814)。導電層可以是多晶矽層。該第一黏合層可被形成為TEOS的單層。該導電層可被形成為多晶矽的單層。 FIG. 8 is a simplified flowchart illustrating a method of manufacturing an engineered substrate according to another embodiment of the present invention. The method includes by providing polycrystalline A ceramic core (810) and a first adhesive layer (812) coupled to at least a part of the polycrystalline ceramic core are formed to form a support structure. The first adhesive layer may include a tetraethyl orthosilicate (TEOS) layer. The method also includes forming a conductive layer coupled to the first adhesion layer (814). The conductive layer may be a polysilicon layer. The first adhesive layer may be formed as a single layer of TEOS. The conductive layer can be formed as a single layer of polysilicon.
該方法還包括形成耦接到導電層的至少一部分的第二黏合層(816)、以及形成阻障殼(818)。該第二黏合層可被形成為TEOS的單層。該阻障殼可被形成為氮化矽的單層或一系列形成阻障殼的子層。 The method also includes forming a second adhesion layer (816) coupled to at least a portion of the conductive layer, and forming a barrier shell (818). The second adhesive layer can be formed as a single layer of TEOS. The barrier shell can be formed as a single layer of silicon nitride or a series of sub-layers forming the barrier shell.
一旦藉由製程810-818形成了支撐結構,該方法還包括將結合層(例如氧化矽層)結合於支撐結構(820)並將實質單晶矽層或實質單晶層結合於氧化矽層(822)。結合層的結合可以包括如本文所述沉積結合材料,隨後進行平坦化製程。 Once the supporting structure is formed by the processes 810-818, the method further includes bonding a bonding layer (such as a silicon oxide layer) to the supporting structure (820) and bonding the substantial single crystal silicon layer or the substantial single crystal layer to the silicon oxide layer ( 822). The bonding of the bonding layer may include depositing a bonding material as described herein, followed by a planarization process.
可以使用層轉移製程來將實質單晶矽層122結合於結合層120。在一些實施例中,矽晶圓(例如矽(111)晶圓)被佈植而形成分裂面。在晶圓結合之後,矽基板可與分裂面下方的單晶矽層部分一起被移出,從而產生第1圖圖示的剝離單晶矽層122。可以改變實質單晶矽層122的厚度來滿足各種應用的規格。此外,可以改變實質單晶層122的晶體方向來滿足應用的規格。另外,可以改變實質單晶層122中的摻雜水平和分佈來滿足特定
應用的規格。在一些實施例中,可以將實質單晶矽層122光滑化,如上所述。
A layer transfer process can be used to bond the substantially single
第8圖圖示的方法還可以包括藉由在該實質單晶矽層上磊晶生長而形成磊晶矽層(824)、以及藉由在該磊晶矽層上磊晶生長而形成磊晶III-V層(826)。在一些實施例中,該磊晶III-V層可以包含氮化鎵(GaN)。 The method illustrated in FIG. 8 may further include forming an epitaxial silicon layer (824) by epitaxial growth on the substantial single crystal silicon layer, and forming an epitaxial silicon layer by epitaxial growth on the epitaxial silicon layer Layer III-V (826). In some embodiments, the epitaxial III-V layer may include gallium nitride (GaN).
應當理解的是,第8圖圖示的具體步驟提供了依據本發明之另一實施例製造工程基板的特定方法。還可以依據替代實施例來執行其他的步驟順序。例如,本發明的替代實施例可以以不同的順序執行上述步驟。此外,第8圖圖示的各個步驟可以包括可以以單個步驟適合的各種順序執行的多個子步驟。另外,可以視特定應用來添加或移除附加步驟。所屬技術領域中具有通常知識者將認可許多的變化、修改及替代。 It should be understood that the specific steps illustrated in FIG. 8 provide a specific method for manufacturing an engineered substrate according to another embodiment of the present invention. Other sequence of steps can also be performed according to alternative embodiments. For example, alternative embodiments of the present invention may perform the above steps in a different order. In addition, each step illustrated in FIG. 8 may include a plurality of sub-steps that can be executed in various orders suitable for a single step. In addition, additional steps can be added or removed depending on the specific application. Those with ordinary knowledge in the technical field will recognize many changes, modifications and substitutions.
還應當理解的是,本文描述的實例和實施例僅用於說明的目的,而且鑒於該等實例和實施例,各種修改或變化將是所屬技術領域中具有通常知識之人士可聯想到的,而且將被包括在本申請的精神和範圍及所附申請專利範圍的範疇內。 It should also be understood that the examples and embodiments described herein are for illustrative purposes only, and in view of these examples and embodiments, various modifications or changes will be imaginable by persons with ordinary knowledge in the technical field, and It will be included in the spirit and scope of this application and the scope of the attached patent application.
100‧‧‧工程基板 100‧‧‧Engineering substrate
110‧‧‧芯 110‧‧‧Core
112‧‧‧第一黏合層 112‧‧‧First adhesive layer
114‧‧‧導電層 114‧‧‧Conductive layer
116‧‧‧第二黏合層 116‧‧‧Second Adhesive Layer
118‧‧‧阻障層 118‧‧‧Barrier layer
120‧‧‧結合層 120‧‧‧Combination layer
122‧‧‧實質單晶矽層 122‧‧‧Substantial single crystal silicon layer
130‧‧‧磊晶材料 130‧‧‧Epitaxial material
Claims (40)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201662350084P | 2016-06-14 | 2016-06-14 | |
US201662350077P | 2016-06-14 | 2016-06-14 | |
US62/350,077 | 2016-06-14 | ||
US62/350,084 | 2016-06-14 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201807839A TW201807839A (en) | 2018-03-01 |
TWI743136B true TWI743136B (en) | 2021-10-21 |
Family
ID=60664230
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW112101490A TWI839076B (en) | 2016-06-14 | 2017-06-13 | Engineered substrate structure for power and rf applications |
TW113110045A TW202429726A (en) | 2016-06-14 | 2017-06-13 | Engineered substrate structure for power and rf applications |
TW110133509A TWI793755B (en) | 2016-06-14 | 2017-06-13 | Engineered substrate structure for power and rf applications |
TW106119602A TWI743136B (en) | 2016-06-14 | 2017-06-13 | Engineered substrate structure for power and rf applications |
Family Applications Before (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW112101490A TWI839076B (en) | 2016-06-14 | 2017-06-13 | Engineered substrate structure for power and rf applications |
TW113110045A TW202429726A (en) | 2016-06-14 | 2017-06-13 | Engineered substrate structure for power and rf applications |
TW110133509A TWI793755B (en) | 2016-06-14 | 2017-06-13 | Engineered substrate structure for power and rf applications |
Country Status (7)
Country | Link |
---|---|
EP (1) | EP3469119A4 (en) |
JP (4) | JP6626607B2 (en) |
KR (1) | KR102361057B1 (en) |
CN (2) | CN114256068A (en) |
SG (1) | SG11201810919UA (en) |
TW (4) | TWI839076B (en) |
WO (1) | WO2017218536A1 (en) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10297445B2 (en) | 2016-06-14 | 2019-05-21 | QROMIS, Inc. | Engineered substrate structure for power and RF applications |
KR102361057B1 (en) * | 2016-06-14 | 2022-02-08 | 큐로미스, 인크 | Engineered substrate structures for power and RF applications |
US10622468B2 (en) | 2017-02-21 | 2020-04-14 | QROMIS, Inc. | RF device integrated on an engineered substrate |
US10734303B2 (en) * | 2017-11-06 | 2020-08-04 | QROMIS, Inc. | Power and RF devices implemented using an engineered substrate structure |
US10586844B2 (en) * | 2018-01-23 | 2020-03-10 | Texas Instruments Incorporated | Integrated trench capacitor formed in an epitaxial layer |
TWI692869B (en) * | 2019-05-03 | 2020-05-01 | 世界先進積體電路股份有限公司 | Substrates and methods for forming the same |
CN111987140A (en) * | 2019-05-21 | 2020-11-24 | 世界先进积体电路股份有限公司 | Substrate and method for manufacturing the same |
JP7319227B2 (en) | 2020-05-11 | 2023-08-01 | 信越化学工業株式会社 | BASE SUBSTRATE FOR III-V COMPOUND CRYSTAL AND METHOD FOR MANUFACTURING THE SAME |
EP4163424A4 (en) | 2020-06-09 | 2024-06-12 | Shin-Etsu Chemical Co., Ltd. | Substrate for group-iii nitride epitaxial growth and method for producing the same |
JP2022012558A (en) | 2020-07-01 | 2022-01-17 | 信越化学工業株式会社 | Substrate for large-bore group iii nitride-based epitaxial growth, and production method thereof |
KR102446604B1 (en) * | 2021-01-04 | 2022-09-26 | 한국과학기술원 | Growth structure for strained channel, and methods for manufacturing strained channel and device using the same |
WO2022168572A1 (en) | 2021-02-05 | 2022-08-11 | 信越半導体株式会社 | Nitride semiconductor substrate and method for producing same |
JP7549549B2 (en) | 2021-02-26 | 2024-09-11 | 信越半導体株式会社 | Nitride semiconductor substrate and method for producing same |
EP4306689A1 (en) * | 2021-03-10 | 2024-01-17 | Shin-Etsu Chemical Co., Ltd. | Seed substrate for epitaxial growth use and method for manufacturing same, and semiconductor substrate and method for manufacturing same |
CN117413345A (en) | 2021-06-08 | 2024-01-16 | 信越半导体株式会社 | Nitride semiconductor substrate and method for manufacturing same |
JP2023025432A (en) * | 2021-08-10 | 2023-02-22 | 信越半導体株式会社 | Nitride semiconductor substrate and method for producing the same |
EP4407657A1 (en) * | 2021-09-21 | 2024-07-31 | Shin-Etsu Handotai Co., Ltd. | Nitride semiconductor substrate and method for producing same |
JP7533794B2 (en) * | 2021-10-15 | 2024-08-14 | 信越半導体株式会社 | Method for manufacturing nitride semiconductor substrate |
WO2023063046A1 (en) * | 2021-10-15 | 2023-04-20 | 信越半導体株式会社 | Nitride semiconductor substrate and manufacturing method therefor |
JP2023065227A (en) | 2021-10-27 | 2023-05-12 | 信越化学工業株式会社 | Epitaxial growth seed substrate, method for manufacturing the same, semiconductor substrate and method for manufacturing the same |
WO2023119916A1 (en) | 2021-12-21 | 2023-06-29 | 信越半導体株式会社 | Nitride semiconductor substrate and method for manufacturing nitride semiconductor substrate |
JP2023098137A (en) | 2021-12-28 | 2023-07-10 | 信越化学工業株式会社 | Substrate for high characteristic epitaxial growth and method for manufacturing the same |
JP2023138130A (en) | 2022-03-18 | 2023-09-29 | 信越化学工業株式会社 | High characteristic epitaxial seed substrate, method for manufacturing the same, semiconductor substrate and method for manufacturing the same |
JP2024070722A (en) * | 2022-11-11 | 2024-05-23 | 信越半導体株式会社 | Substrate for high-frequency device and manufacturing method for the same |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200520274A (en) * | 2003-07-28 | 2005-06-16 | Freescale Semiconductor Inc | A semiconductor device having an organic anti-reflective coating (arc) and method therefor |
TW200721452A (en) * | 2005-06-17 | 2007-06-01 | Northrop Grumman Corp | Novel method for intgegrating silicon CMOS and ALGaN/GaN wideband amplifiers on engineered substrates |
Family Cites Families (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4430149A (en) * | 1981-12-30 | 1984-02-07 | Rca Corporation | Chemical vapor deposition of epitaxial silicon |
US7238595B2 (en) * | 2003-03-13 | 2007-07-03 | Asm America, Inc. | Epitaxial semiconductor deposition methods and structures |
US20060284167A1 (en) * | 2005-06-17 | 2006-12-21 | Godfrey Augustine | Multilayered substrate obtained via wafer bonding for power applications |
CN100424878C (en) * | 2006-11-21 | 2008-10-08 | 华中科技大学 | Ferroelectric film capacity used for ferroelectric memorizer and its manufacturing method |
CN101192533B (en) * | 2006-11-28 | 2010-06-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof, and etch stop layer forming method |
FR2912552B1 (en) * | 2007-02-14 | 2009-05-22 | Soitec Silicon On Insulator | MULTILAYER STRUCTURE AND METHOD FOR MANUFACTURING THE SAME |
US7732301B1 (en) * | 2007-04-20 | 2010-06-08 | Pinnington Thomas Henry | Bonded intermediate substrate and method of making same |
CN101669193B (en) * | 2007-04-27 | 2012-02-15 | 株式会社半导体能源研究所 | Soi substrate and manufacturing method of the same, and semiconductor device |
US20090278233A1 (en) * | 2007-07-26 | 2009-11-12 | Pinnington Thomas Henry | Bonded intermediate substrate and method of making same |
CN101621005B (en) * | 2008-07-02 | 2012-08-22 | 中芯国际集成电路制造(上海)有限公司 | TFT MONOS or SONOS memory cell structure |
US7915645B2 (en) * | 2009-05-28 | 2011-03-29 | International Rectifier Corporation | Monolithic vertically integrated composite group III-V and group IV semiconductor device and method for fabricating same |
CN102044473B (en) * | 2009-10-13 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Formation method of semiconductor device |
US9012253B2 (en) * | 2009-12-16 | 2015-04-21 | Micron Technology, Inc. | Gallium nitride wafer substrate for solid state lighting devices, and associated systems and methods |
KR20120020526A (en) * | 2010-08-30 | 2012-03-08 | 삼성전자주식회사 | Substrate have buried conductive layer and formation method thereof, and fabricating method of semiconductor device using the same |
CN102456721A (en) * | 2010-10-17 | 2012-05-16 | 金木子 | Gallium nitride-based chip with ceramic substrate and manufacturing method |
US8546165B2 (en) * | 2010-11-02 | 2013-10-01 | Tsmc Solid State Lighting Ltd. | Forming light-emitting diodes using seed particles |
US8766274B2 (en) * | 2010-12-14 | 2014-07-01 | Hexatech, Inc. | Thermal expansion engineering for polycrystalline aluminum nitride sintered bodies |
JP2012142385A (en) * | 2010-12-28 | 2012-07-26 | Sumitomo Electric Ind Ltd | Semiconductor device manufacturing method |
US8916483B2 (en) | 2012-03-09 | 2014-12-23 | Soitec | Methods of forming semiconductor structures including III-V semiconductor material using substrates comprising molybdenum |
JP6152548B2 (en) | 2012-08-06 | 2017-06-28 | 並木精密宝石株式会社 | Gallium oxide substrate and manufacturing method thereof |
US9082692B2 (en) * | 2013-01-02 | 2015-07-14 | Micron Technology, Inc. | Engineered substrate assemblies with epitaxial templates and related systems, methods, and devices |
US9650723B1 (en) * | 2013-04-11 | 2017-05-16 | Soraa, Inc. | Large area seed crystal for ammonothermal crystal growth and method of making |
JP6176069B2 (en) * | 2013-11-13 | 2017-08-09 | 住友電気工業株式会社 | Group III nitride composite substrate and method for manufacturing the same, laminated group III nitride composite substrate, group III nitride semiconductor device and method for manufacturing the same |
JP6488917B2 (en) * | 2014-07-04 | 2019-03-27 | 三菱マテリアル株式会社 | Power module substrate with heat sink and power module |
JP2016058693A (en) * | 2014-09-12 | 2016-04-21 | 株式会社東芝 | Semiconductor device, semiconductor wafer, and method of manufacturing semiconductor device |
US9997391B2 (en) * | 2015-10-19 | 2018-06-12 | QROMIS, Inc. | Lift off process for chip scale package solid state devices on engineered substrate |
CN108541335B (en) * | 2015-12-04 | 2023-07-18 | 克罗米斯有限公司 | Wide bandgap device integrated circuit architecture on engineered substrate |
KR102361057B1 (en) * | 2016-06-14 | 2022-02-08 | 큐로미스, 인크 | Engineered substrate structures for power and RF applications |
JP6580267B2 (en) | 2016-07-26 | 2019-09-25 | 三菱電機株式会社 | Semiconductor device and manufacturing method of semiconductor device |
CN109671612B (en) | 2018-11-15 | 2020-07-03 | 中国科学院上海微系统与信息技术研究所 | Gallium oxide semiconductor structure and preparation method thereof |
-
2017
- 2017-06-13 KR KR1020197000184A patent/KR102361057B1/en active IP Right Grant
- 2017-06-13 TW TW112101490A patent/TWI839076B/en active
- 2017-06-13 JP JP2018565352A patent/JP6626607B2/en active Active
- 2017-06-13 TW TW113110045A patent/TW202429726A/en unknown
- 2017-06-13 TW TW110133509A patent/TWI793755B/en active
- 2017-06-13 SG SG11201810919UA patent/SG11201810919UA/en unknown
- 2017-06-13 EP EP17813933.3A patent/EP3469119A4/en active Pending
- 2017-06-13 WO PCT/US2017/037252 patent/WO2017218536A1/en unknown
- 2017-06-13 CN CN202111369484.3A patent/CN114256068A/en active Pending
- 2017-06-13 TW TW106119602A patent/TWI743136B/en active
- 2017-06-13 CN CN201780049691.6A patent/CN109844184B/en active Active
-
2019
- 2019-12-01 JP JP2019217661A patent/JP7001660B2/en active Active
-
2021
- 2021-12-24 JP JP2021210164A patent/JP7416556B2/en active Active
-
2023
- 2023-09-25 JP JP2023161626A patent/JP2023182643A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200520274A (en) * | 2003-07-28 | 2005-06-16 | Freescale Semiconductor Inc | A semiconductor device having an organic anti-reflective coating (arc) and method therefor |
TW200721452A (en) * | 2005-06-17 | 2007-06-01 | Northrop Grumman Corp | Novel method for intgegrating silicon CMOS and ALGaN/GaN wideband amplifiers on engineered substrates |
Also Published As
Publication number | Publication date |
---|---|
TW202322418A (en) | 2023-06-01 |
JP2019523994A (en) | 2019-08-29 |
EP3469119A1 (en) | 2019-04-17 |
JP2022058405A (en) | 2022-04-12 |
JP7001660B2 (en) | 2022-01-19 |
JP2023182643A (en) | 2023-12-26 |
SG11201810919UA (en) | 2019-01-30 |
KR102361057B1 (en) | 2022-02-08 |
TW202203473A (en) | 2022-01-16 |
CN109844184B (en) | 2021-11-30 |
KR20190019122A (en) | 2019-02-26 |
CN109844184A (en) | 2019-06-04 |
TWI839076B (en) | 2024-04-11 |
TW201807839A (en) | 2018-03-01 |
CN114256068A (en) | 2022-03-29 |
TWI793755B (en) | 2023-02-21 |
TW202429726A (en) | 2024-07-16 |
JP2020074399A (en) | 2020-05-14 |
WO2017218536A1 (en) | 2017-12-21 |
JP6626607B2 (en) | 2019-12-25 |
JP7416556B2 (en) | 2024-01-17 |
EP3469119A4 (en) | 2020-02-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI743136B (en) | Engineered substrate structure for power and rf applications | |
JP7565318B2 (en) | Gallium nitride epitaxial structures for power devices | |
TWI850134B (en) | Methods of fabricating engineered substrate structure | |
US12009205B2 (en) | Engineered substrate structures for power and RF applications | |
TWI801447B (en) | Power and rf devices implemented using an engineered substrate structure | |
TWI859810B (en) | Micro-electromechanical system (mems) device implemented using an engineered substrate structure |