CN114256068A - Engineered substrate structures for power and radio frequency applications - Google Patents

Engineered substrate structures for power and radio frequency applications Download PDF

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Publication number
CN114256068A
CN114256068A CN202111369484.3A CN202111369484A CN114256068A CN 114256068 A CN114256068 A CN 114256068A CN 202111369484 A CN202111369484 A CN 202111369484A CN 114256068 A CN114256068 A CN 114256068A
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layer
epitaxial
coupled
silicon
substrate
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弗拉基米尔·奥德诺博柳多夫
杰姆·巴斯切里
莎丽·法伦斯
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Qromis Inc
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Qromis Inc
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Abstract

The invention discloses an engineered substrate structure for power and radio frequency applications, the substrate comprising a support structure comprising: a polycrystalline ceramic core; a first adhesion layer coupled to the polycrystalline ceramic core; a conductive layer coupled to the first adhesion layer; a second adhesive layer coupled to the conductive layer; and a barrier layer coupled to the second adhesion layer. The substrate further comprises: a silicon oxide layer coupled to the support structure; a substantially single crystal silicon layer coupled to the silicon oxide layer; and an epitaxial III-V layer coupled to the substantially single crystal silicon layer.

Description

Engineered substrate structures for power and radio frequency applications
The present application is a divisional application of the chinese patent application having an application date of 2017, 6 and 13, and an application number of 2017800496916, and entitled "engineered substrate structures for power applications and radio frequency applications".
Cross reference to related applications
This application claims priority from united states provisional patent application serial No. 62/350,084 entitled "engineered substrate structures for power and radio frequency applications" filed on 2016, 6, 14, and united states provisional patent application serial No. 62/350,077 entitled "engineered substrate structures and methods of fabrication" filed on 2016, 6, 14. The entire contents of which are incorporated herein by reference for all purposes.
The following two U.S. patent applications are filed concurrently with this application and the entire disclosures of both applications are incorporated herein by reference for all purposes:
application No. 15/621,335 entitled "engineered substrate structures for power and radio frequency applications" (attorney docket No.098825-
Application No. 15/621,338 entitled "engineered substrate structures and methods of fabrication" filed on 13.6.2017 (attorney docket No. 098825-.
Background
Light Emitting Diode (LED) structures are typically epitaxially grown on a sapphire substrate. Many products currently use LED devices, including lighting, computer monitors, and other display devices.
Since the substrate and the epitaxial layer are composed of different materials, the growth of gallium nitride based LED structures on sapphire substrates is a heteroepitaxial growth process. Due to the heteroepitaxial growth process, the epitaxially grown material may exhibit various adverse effects, including a reduction in uniformity and a reduction in metrics associated with the electronic/optical properties of the epitaxial layers. Accordingly, there is a need in the art for improved methods and systems related to epitaxial growth processes and substrate structures.
Disclosure of Invention
The present invention relates generally to an engineered substrate structure. More particularly, the present invention relates to methods and systems suitable for use in epitaxial growth processes. By way of example only, the present invention has application in methods and systems for providing a substrate structure suitable for epitaxial growth that is characterized by having a Coefficient of Thermal Expansion (CTE) that substantially matches that of the epitaxial layers grown thereon. The methods and techniques may be applied to various semiconductor processing operations.
According to an embodiment of the present invention, a substrate is provided. The substrate includes a support structure comprising: a polycrystalline ceramic core; a first adhesion layer coupled to the polycrystalline ceramic core; a conductive layer coupled to the first adhesion layer; a second adhesive layer coupled to the conductive layer; and a barrier layer coupled to the second adhesion layer. The substrate further comprises: a silicon oxide layer coupled to the support structure; a substantially single crystal silicon layer coupled to the silicon oxide layer; and an epitaxial III-V layer coupled to the substantially single crystal silicon layer.
According to another embodiment of the present invention, a method of manufacturing a substrate is provided. The method includes forming a support structure by: providing a polycrystalline ceramic core; encapsulating the polycrystalline ceramic core in a first bond coat; encapsulating the first adherent shell in a conductive shell; encapsulating the conductive shell in a second adhesive shell; and encapsulating the second adhesive shell in a barrier shell. The method further comprises the following steps: bonding a bonding layer to the support structure; bonding a substantially single crystal silicon layer to the bonding layer, forming an epitaxial silicon layer by epitaxial growth on the substantially single crystal silicon layer; and forming an epitaxial III-V layer by epitaxial growth on the epitaxial silicon layer.
According to an embodiment of the present invention, an engineered substrate structure is provided. The engineered substrate structure comprises a support structure, a bonding layer coupled to the support structure, a substantially single crystal silicon layer coupled to the adhesion layer; and an epitaxial single crystal silicon layer coupled to the substantially single crystal silicon layer. The support structure includes: a polycrystalline ceramic core; a first adhesion layer coupled to the polycrystalline ceramic core; a conductive layer coupled to the first adhesion layer; a second adhesive layer coupled to the conductive layer; and a barrier shell coupled to the second adhesive layer.
Many benefits are realized by the present invention over conventional techniques. For example, embodiments of the present invention provide an engineered substrate structure that is CTE matched to gallium nitride based epitaxial layers suitable for optical, electronic, and optoelectronic applications. The encapsulation layer, which is used as a component of the engineered substrate structure, prevents impurities present in the central portion of the substrate from diffusing to the semiconductor processing environment in which the engineered substrate is used. The key properties associated with the substrate material, including coefficient of thermal expansion, lattice mismatch, thermal stability, and topography control, are independently engineered to improve (e.g., optimize) the matching to the gallium nitride-based epitaxial layers and device layers, as well as to different device architecture and performance goals. Process integration is simplified because the substrate material layers are integrated together in conventional semiconductor fabrication processes. These and other embodiments of the present invention and many of its advantages and features are described in more detail below and in the accompanying drawings.
Brief description of the drawings
Fig. 1 is a simplified schematic diagram illustrating an engineered substrate structure according to an embodiment of the invention.
FIG. 2A is a SIMS profile showing the concentration of species as a function of depth for an engineered structure according to an embodiment of the invention.
FIG. 2B is a SIMS profile showing the concentration of species as a function of depth for an engineered structure after annealing according to an embodiment of the invention.
Fig. 2C is a SIMS profile showing the concentration of species as a function of depth for an annealed engineered structure having a silicon nitride layer in accordance with an embodiment of the present invention.
Fig. 3 is a simplified schematic diagram illustrating an engineered substrate structure according to another embodiment of the invention.
Fig. 4 is a simplified schematic diagram illustrating an engineered substrate structure according to yet another embodiment of the invention.
FIG. 5 is a simplified flow diagram illustrating a method of fabricating an engineered substrate according to an embodiment of the invention.
Fig. 6 is a simplified schematic diagram illustrating an epitaxial/engineered substrate structure for RF applications and power applications according to an embodiment of the present invention.
Fig. 7 is a simplified schematic diagram illustrating a III-V epitaxial layer on an engineered substrate structure in accordance with an embodiment of the invention.
FIG. 8 is a simplified flow diagram illustrating a method of fabricating an engineered substrate according to another embodiment of the invention.
Detailed description of the embodiments
Embodiments of the invention relate to engineered substrate structures. More particularly, the present invention relates to methods and systems suitable for use in epitaxial growth processes. Merely by way of example, the present invention has application in methods and systems for providing a substrate structure suitable for epitaxial growth that is characterized by a Coefficient of Thermal Expansion (CTE) that is substantially matched to the epitaxial layers grown thereon. The methods and techniques may be applied to various semiconductor processing operations.
Fig. 1 is a simplified schematic diagram illustrating an engineered substrate structure according to an embodiment of the invention. The engineered substrate 100 shown in fig. 1 is suitable for use in a variety of electronic and optical applications. The engineered substrate includes a core 110, which may have a Coefficient of Thermal Expansion (CTE) that substantially matches the CTE of the epitaxial material to be grown on the engineered substrate 100. Epitaxial material 130 is shown as optional because it need not be an integral part of the engineered substrate, but will typically be grown on the engineered substrate.
For applications involving the growth of gallium nitride (GaN) -based materials, including epitaxial layers of GaN-based layers, the core 110 may be a polycrystalline ceramic material, e.g., polycrystalline aluminum nitride (AlN), which may include a bonding material such as yttria. Other materials may be used in the core 110, including polycrystalline gallium nitride (GaN), polycrystalline aluminum gallium nitride (AlGaN), polycrystalline silicon carbide (SiC), polycrystalline zinc oxide (ZnO), polycrystalline gallium trioxide (Ga)2O3) And the like.
The thickness of the core may be on the order of about 100 μm to 1,500 μm (e.g., 725 μm). The core 110 is encapsulated in a first adhesive layer 112, which first adhesive layer 112 may be referred to as a shell or an encapsulating shell. In one embodiment, the first adhesion layer 112 comprises a thickness of
Figure BDA0003355056440000031
A layer of Tetraethylorthosilicate (TEOS). In other embodiments, the thickness of the first adhesive layer varies, for example, from
Figure BDA0003355056440000032
Become to
Figure BDA0003355056440000033
Although TEOS is used for the adhesion layer in some embodiments, other materials that provide adhesion between a later deposited layer and an underlying layer or material (e.g., ceramic, particularly polycrystalline ceramic) may be used in accordance with embodiments of the present invention. For example, SiO2Or other silicon oxides (Si)xOy) Adhere well to ceramic materials and provide a suitable surface for subsequent deposition, such as deposition of conductive materials. In some embodiments, the first adhesive layer 112 completely surrounds the core 110 to form a completely encapsulated core, and may be formed using an LPCVD process. The first adhesion layer 112 provides a surface on which subsequent layers adhere to form an integral part of the engineered substrate structure.
In addition to forming the encapsulation first adhesion layer using an LPCVD process, a furnace-based process, or the like, other semiconductor processes may be used in accordance with embodiments of the present invention, including a CVD process or similar deposition process. As an example, a deposition process that coats a portion of the core may be utilized, the core may be flipped, and the deposition process may be repeated to coat additional portions of the core. Thus, while LPCVD techniques are utilized in some embodiments to provide a fully encapsulated structure, other film formation techniques may be used depending on the particular application.
A conductive layer 114 is formed around the adhesion layer 112. In one embodiment, conductive layer 114 is a shell of polysilicon (i.e., polysilicon) formed around first adhesion layer 112, as polysilicon may exhibit poor adhesion to ceramic materials. In embodiments where the conductive layer is polysilicon, the thickness of the polysilicon layer may be
Figure BDA0003355056440000041
(for example,
Figure BDA0003355056440000042
) Of the order of magnitude of (d). In some embodiments, the polysilicon layer may be formed as a shell to completely surround the first adhesion layer 112 (e.g., a TEOS layer) to form a fully encapsulated first adhesion layer, and it may be formed using an LPCVD process. In other embodiments, as described below, the conductive material may be formed on a portion of the adhesion layer, for example, the bottom half of the substrate structure. In some embodiments, the conductive material may be formed as a fully encapsulated layer and subsequently removed on one side of the substrate structure.
In one embodiment, conductive layer 114 may be a doped polysilicon layer to provide a highly conductive material, e.g., boron doped to provide a p-type polysilicon layer. In some embodiments, the boron doping is at 1 × 1019cm-3To 1X 1020cm-3To provide high conductivity. Other dopants of different dopant concentrations (e.g., dopant concentration in the range of 1 × 10)16cm-3To 5X 1018cm-3Phosphorus, arsenic, bismuth, etc.) may be used to provide n-type or p-type semiconductor materials suitable for use in the conductive layer. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.
The presence of the conductive layer 114 is useful during electrostatic chucking of the engineered substrate to a semiconductor processing tool, such as a tool having an electrostatic chuck (ESC). The conductive layer 114 is capable of rapid de-chucking after processing in a semiconductor processing tool. Thus, embodiments of the present invention provide substrate structures that can be processed in the manner used with conventional silicon wafers. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.
A second adhesion layer 116 (e.g., having a thickness of
Figure BDA0003355056440000043
A TEOS layer of magnitude) 116. In some embodiments, second adhesion layer 116 completely surrounds conductive layer 114 to form a fully encapsulated structure, and may be formed using an LPCVD process, a CVD process, or any other suitable deposition process, including depositing a spin-on dielectric.
A barrier layer 118, such as a silicon nitride layer, is formed around the second adhesion layer 116. In one embodiment, barrier layer 118 is a silicon nitride layer 118 having a thickness of
Figure BDA0003355056440000044
To
Figure BDA0003355056440000045
Magnitude. In some embodiments, the barrier layer 118 completely surrounds the second adhesion layer 116 to form a fully encapsulated structure, and may be formed using an LPCVD process. In addition to the silicon nitride layer, amorphous materials (including SiCN, SiON, AlN, SiC, etc.) may be used as the barrier layer. In some embodiments, the barrier layer 118 includes a plurality of sub-layers that are structured to form a barrier layer. Thus, the term barrier layer is not intended to mean a single layer or material, but rather encompasses one or more materials layered in a composite manner. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.
In some embodiments, the barrier layer 118 (e.g., a silicon nitride layer) prevents elements (e.g., yttria oxide (i.e., yttria), oxygen, metallic impurities, other trace elements, etc.) present in the core 110 from diffusing and/or outgassing into the environment of a semiconductor processing chamber in which the engineered substrate may be present, e.g., during high temperature (e.g., 1000 ℃) epitaxial growth processes. With the encapsulation layers described herein, ceramic materials including polycrystalline AlN designed for use in non-clean room environments may be utilized in semiconductor process flows and clean room environments.
FIG. 2A is a Secondary Ion Mass Spectrometry (SIMS) profile showing the concentration of species as a function of depth for an engineered structure according to an embodiment of the invention. The engineered structure does not include barrier layer 118. Referring to fig. 2A, several species (e.g., yttrium, calcium, and aluminum) present in the ceramic core are reduced to negligible concentrations in the engineered layer 120/122. The concentrations of calcium, yttrium and aluminum were reduced by three, four and six orders of magnitude, respectively.
Fig. 2B is a SIMS profile showing the species concentration as a function of depth for an annealed engineered structure without a barrier layer in accordance with an embodiment of the invention. As discussed above, the engineered substrate structures provided by embodiments of the present invention may be exposed to high temperatures (-1,100 ℃) for hours during semiconductor processing operations, for example, during epitaxial growth of GaN-based layers.
For the profile shown in fig. 2B, the engineered substrate structure was annealed at 1,100 ℃ for 4 hours. As shown in fig. 2B, calcium, yttrium and aluminum, which were initially present in the deposited sample at low concentrations, have diffused into the engineered layer to similar concentrations as the other elements.
Fig. 2C is a SIMS profile showing the species concentration as a function of depth for an annealed engineered structure with a barrier layer according to an embodiment of the invention. Integrating the diffusion barrier layer 118 (e.g., a silicon nitride layer) into the engineered substrate structure prevents the diffusion of calcium, yttrium, and aluminum into the engineered layer during the annealing process that occurs in the absence of the diffusion barrier layer. As shown in fig. 2C, the calcium, yttrium and aluminum present in the ceramic core remain at low concentrations in the engineered layer after annealing. Thus, the use of the barrier layer 118 (e.g., a silicon nitride layer) prevents these elements from diffusing through the diffusion barrier layer, thereby preventing their release into the environment surrounding the engineered substrate. Similarly, any other impurities contained in the bulk ceramic material will be contained by the barrier layer.
Generally, the ceramic material used to form the core 110 is fired at a temperature of 1,800 ℃. It is expected that this process will drive off a large amount of impurities present in the ceramic material. These impurities may include yttrium, which results from the use of yttrium oxide as a sintering agent, calcium, and other elements and compounds. Subsequently, during an epitaxial growth process carried out at a much lower temperature in the range of 800 ℃ to 1,100 ℃, it would be expected that the subsequent diffusion of these impurities would be insignificant. However, contrary to conventional expectations, the inventors have determined that significant diffusion of elements through layers of the engineered substrate may occur even during the epitaxial growth process at temperatures well below the firing temperature of the ceramic material. Accordingly, embodiments of the present invention integrate a barrier layer 118 (e.g., a silicon nitride layer) to prevent out-diffusion of background elements from the polycrystalline ceramic material (e.g., AlN) into the engineered layer 120/122 and epitaxial layers, such as the optional GaN layer 130. The silicon nitride layer 118 encapsulating the underlying layers and materials provides the desired barrier function.
As shown in fig. 2B, the elements originally present in the core 110 include yttrium that diffuses into and through the first TEOS layer 112, the polysilicon layer 114, and the second TEOS layer 116. However, as shown in fig. 2C, the presence of the silicon nitride layer 118 prevents these elements from diffusing through the silicon nitride layer, thereby preventing their release into the environment surrounding the engineered substrate.
Referring again to fig. 1, a bonding layer 120 (e.g., a silicon oxide layer) is deposited on a portion of the barrier layer 118 (e.g., a top surface of the barrier layer), and the bonding layer 120 is subsequently used during bonding of the substantially single crystal layer 122. In some embodiments, the bonding layer 120 may be about 1.5 μm thick.
The substantially single crystal layer 122 is suitable for use as a growth layer during an epitaxial growth process to form the epitaxial material 130. In some embodiments, epitaxial material 130 comprises a GaN layer having a thickness of 2 μm to 10 μm, which may be used as one of a plurality of layers used in optoelectronic devices, RF devices, power devices, and the like. In one embodiment, the substantially single crystal layer 122 comprises a substantially single crystal silicon layer attached to the silicon oxide layer 118 using a layer transfer process.
Fig. 3 is a simplified schematic diagram illustrating an engineered substrate structure according to an embodiment of the invention. The engineered substrate 300 shown in fig. 3 is suitable for use in a variety of electronic and optical applications. The engineered substrate includes a core 110, which may have a Coefficient of Thermal Expansion (CTE) that substantially matches the CTE of the epitaxial material 130 to be grown on the engineered substrate 300. Epitaxial material 130 is shown as optional because it is not required as an integral part of the engineered substrate structure, but will typically be grown on the engineered substrate structure.
For applications involving the growth of gallium nitride (GaN) -based materials, including epitaxial layers of GaN-based layers, the core 110 may be a polycrystalline ceramic material, such as polycrystalline aluminum nitride (AlN). The thickness of the core may be on the order of about 100 to 1,500 μm, for example 725 μm. The core 110 is encapsulated in a first adhesive layer 112, which first adhesive layer 112 may be referred to as a shell or an encapsulating shell. In this embodiment, the first adhesive layer 112 completely encapsulates the core, but as discussed in further detail with respect to fig. 4, this is not required by the present invention.
In one embodiment, the first adhesion layer 112 comprises a thickness of about
Figure BDA0003355056440000061
A layer of Tetraethylorthosilicate (TEOS). In other embodiments, the thickness of the first adhesive layer varies, for example from
Figure BDA0003355056440000062
Become to
Figure BDA0003355056440000063
Although TEOS is used for the adhesion layer in some embodiments, other materials that provide adhesion between a later deposited layer and an underlying layer or material (e.g., ceramic, particularly polycrystalline ceramic) may be used in accordance with embodiments of the present invention. For example, SiO2Or other silicon oxides (Si)xOy) Adhere well to ceramic materials and provide for subsequent deposition (e.g., deposition of conductive materials)A suitable surface. In some embodiments, the first adhesive layer 112 completely surrounds the core 110 to form a completely encapsulated core, and an LPCVD process may be used. The adhesion layer provides a surface upon which subsequent layers adhere to form an integral part of the engineered substrate structure.
In addition to forming the package adhesion layer using an LPCVD process, a furnace-based process, or the like, other semiconductor processes may be used according to embodiments of the present invention. By way of example, the core may be flipped using a deposition process that coats a portion of the core, e.g., CVD, PECVD, etc., and the deposition process may be repeated to coat additional portions of the core.
The conductive layer 314 is formed on at least a portion of the first adhesive layer 112. In one embodiment, conductive layer 314 comprises polysilicon (i.e., polycrystalline silicon) formed by a deposition process on a lower portion (e.g., the lower half of the back side) of the core/adhesion layer structure. In embodiments where the conductive layer is polysilicon, the thickness of the polysilicon layer may be on the order of several thousand angstroms, for example,
Figure BDA0003355056440000071
in some embodiments, the polysilicon layer may be formed using an LPCVD process.
In one embodiment, conductive layer 314 may be a doped polysilicon layer to provide a highly conductive material, for example, conductive layer 314 may be doped with boron to provide a p-type polysilicon layer. In some embodiments, the boron doping is at about 1 × 1019cm-3To 1X 1020cm-3To provide high conductivity. The presence of the conductive layer is useful during electrostatic chucking of the engineered substrate to a semiconductor processing tool, such as a tool having an electrostatic chuck (ESC). The conductive layer 314 can quickly remove the adsorption after processing. Thus, embodiments of the present invention provide substrate structures that can be processed in the manner used for conventional silicon wafers. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.
Forming a second adhesion layer 316 (e.g., a second TEO) around the conductive layer 314 (e.g., a polysilicon layer)S layer). The second adhesion layer 316 has a thickness of about
Figure BDA0003355056440000072
Magnitude. In some embodiments, the second adhesion layer 316 may completely surround the conductive layer 314 and the first adhesion layer 112 to form a completely encapsulated structure, and may be formed using an LPCVD process. In other embodiments, the second adhesive layer 316 only partially surrounds the conductive layer 314, e.g., terminating at a location shown by plane 317, which plane 317 may be aligned with the top surface of the conductive layer 314. In this example, the top surface of conductive layer 314 will be in contact with a portion of barrier layer 118. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.
A barrier layer 118 (e.g., a silicon nitride layer) is formed around the second adhesion layer 316. In some embodiments, the barrier layer 118 is about thick
Figure BDA0003355056440000073
To
Figure BDA0003355056440000074
Magnitude. In some embodiments, barrier layer 118 completely surrounds second adhesion layer 316 to form a fully encapsulated structure, and may be formed using an LPCVD process.
In some embodiments, the use of a silicon nitride barrier layer prevents elements (e.g., yttria oxide (yttria)), oxygen, metal impurities, other trace elements, etc.) present in the core 110 from diffusing and/or out-gassing into the environment of a semiconductor processing chamber in which the engineered substrate may be present, for example, during a high temperature (e.g., 1000 ℃) epitaxial growth process. With the encapsulation layers described herein, ceramic materials including polycrystalline AlN designed for use in non-clean room environments may be utilized in semiconductor processing flows and clean room environments.
Fig. 4 is a simplified schematic diagram illustrating an engineered substrate structure according to another embodiment of the invention. In the embodiment shown in fig. 4, the first adhesive layer 412 is formed on at least a portion of the core 110, but does not encapsulate the core 110. In this embodiment, as described more fully below, a first adhesion layer 412 is formed on the lower surface of the core 110 (the back surface of the core 110) in order to enhance adhesion of a subsequently formed conductive layer 414. Although the adhesion layer 412 is shown only on the lower surface of the core 110 in fig. 4, it should be understood that deposition of the adhesion layer material on other portions of the core will not adversely affect the performance of the engineered substrate structure, and such material may be present in various embodiments. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.
The conductive layer 414 does not encapsulate the first adhesive layer 412 and the core 110, but is substantially aligned with the first adhesive layer 412. Although conductive layer 414 is shown as extending along the bottom or back surface and extending up a portion of the sides of first adhesion layer 412, the present invention does not require extension along vertical sides. Thus, embodiments may utilize deposition on one side of a substrate structure, masking (masking) one side of a substrate structure, and the like. The conductive layer 414 may be formed on a portion of one side of the first adhesive layer 412, for example, a bottom/back side. The conductive layer 414 provides electrical conduction on one side of the engineered substrate structure, which can be advantageous in radio frequency and high power applications. As discussed with respect to conductive layer 114 in fig. 1, the conductive layer may comprise doped polysilicon.
A portion of the core 110, a portion of the first adhesive layer 412, and the conductive layer 414 are covered with a second adhesive layer 416 to enhance adhesion of the barrier layer 418 to the underlying material. As discussed above, barrier layer 418 forms an encapsulation structure to prevent diffusion from underlying layers.
In addition to semiconductor-based conductive layers, in other embodiments, the conductive layer 414 is a metal layer, such as
Figure BDA0003355056440000081
Titanium, etc.
Referring again to fig. 4, depending on the implementation, one or more layers may be removed. For example, layer 412 and layer 414 may be removed, leaving only a single adhesion shell 416 and barrier layer 418. In another embodiment, only layer 414 may be removed. In this embodiment, layer 412 may also balance the stress and wafer bow caused by layer 120 deposited on top of layer 418. The construction of a substrate structure with an insulating layer on the top side of the core 110 (e.g., with only an insulating layer between the core 110 and the layer 120) would provide benefits for power/radio frequency applications where a highly insulating substrate is required.
In another embodiment, the barrier layer 418 may encapsulate the core 110 directly, followed by the conductive layer 414 and subsequent adhesion layer 416. In this embodiment, layer 120 may be deposited directly on adhesion layer 416 from the top side. In yet another embodiment, an adhesion layer 416 may be deposited on the core 110, followed by a barrier layer 418, and then the conductive layer 414 and the further adhesion layer 412.
Although some embodiments have been discussed in terms of layers, the term "layer" should be understood such that a layer may include multiple sub-layers that are constructed to form the layer of interest. Thus, the term "layer" is not intended to mean a single layer composed of a single material, but rather encompasses one or more materials that are layered in a composite manner to form a desired structure. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.
FIG. 5 is a simplified flow diagram illustrating a method of fabricating an engineered substrate according to an embodiment of the invention. The method can be used to fabricate a substrate that is CTE matched to one or more epitaxial layers grown on the substrate. The method 500 includes forming a support structure by: a polycrystalline ceramic core is provided (510), the polycrystalline ceramic core is encapsulated in a shell formed of a first adhesion layer (e.g., a Tetraethylorthosilicate (TEOS) shell) (512), and the first adhesion layer is encapsulated in a conductive shell (e.g., a polysilicon shell) (514). The first adhesion layer may be formed as a single layer of TEOS. The conductive shell may be formed as a single layer of polysilicon.
The method also includes encapsulating the conductive shell in a second adhesion layer (e.g., a second TEOS shell) (516), and encapsulating the second adhesion layer in a barrier shell (518). The second adhesion layer may be formed as a single layer of TEOS. The barrier shell may be formed as a single layer of silicon nitride.
Once the support structure is formed, via step 510-518, the method further includes bonding a bonding layer (e.g., a silicon oxide layer) to the support structure(520) And bonding a substantially single crystal layer (e.g., a substantially single crystal silicon layer) to the silicon oxide layer (522). Other substantially single crystal layers may be used in accordance with embodiments of the present invention, including SiC, sapphire, GaN, AlN, SiGe, Ge, diamond, Ga2O3ZnO, etc. Bonding of the bonding layers may include depositing a bonding material followed by a planarization process as described herein. In embodiments described below, bonding a substantially single crystal layer (e.g., a substantially single crystal silicon layer) to a bonding layer utilizes a layer transfer process in which the layer is a single crystal silicon layer transferred from a silicon wafer.
Referring to fig. 1, bonding layer 120 may be formed by deposition of a thick (e.g., 4 μm thick) oxide layer followed by a Chemical Mechanical Polishing (CMP) process to thin the oxide to a thickness of about 1.5 μm. The thick initial oxide serves to fill voids and surface features present on the support structure that may be present after fabrication of the polycrystalline core and which persist in forming the encapsulation layer shown in fig. 1. The CMP process provides a substantially planar surface free of voids, particles, or other features, which may then be used during a wafer transfer process to bond a substantially single crystal layer 122 (e.g., a substantially single crystal silicon layer) to the bonding layer 120. It should be appreciated that bonding layer 120 need not feature an atomically flat surface, but rather should provide a substantially flat surface that supports bonding of a substantially single crystal layer (e.g., a substantially single crystal silicon layer) with a desired reliability.
A layer transfer process may be used to bond the substantially single crystal silicon layer 122 to the bonding layer 120. In some embodiments, a silicon wafer (e.g., a silicon (111) wafer) is implanted to form a cleave plane. After wafer bonding, the silicon substrate may be removed along with a portion of the single crystal silicon layer below the cleave plane, resulting in the delaminated single crystal silicon layer 122 shown in fig. 1. The thickness of the substantially single crystal layer 122 may vary to meet the specifications of various applications. In addition, the crystal orientation of the substantially single crystal layer 122 may be changed to meet the specifications of the application. In addition, the doping level and profile in the substantially single crystal layer 122 may be varied to meet the specifications of a particular application.
The method shown in fig. 5 may also include smoothing the substantially single crystal layer (524). In some embodiments, the thickness and surface roughness of the substantially single crystal layer 122 may be further modified for high quality epitaxial growth. Different device applications may have slightly different specifications with respect to thickness and surface smoothness of the substantially single-crystal layer 122. The cleaving process delaminates the substantially single crystal layer 122 from the bulk single crystal silicon wafer at the peak of the implanted ion distribution. After cleaving, the substantially single crystal layer 122 may be adjusted or modified in several respects before the substantially single crystal layer 122 is used as a growth surface for epitaxial growth of other materials (e.g., gallium nitride).
First, the transferred substantially single crystal layer 122 may contain a small residual hydrogen concentration and may have some crystal damage from the implant. Accordingly, it may be beneficial to remove thin portions of the transferred substantially single crystal layer 122 where the crystal lattice is damaged. In some embodiments, the depth of the implant may be adjusted to be greater than the desired final thickness of the substantially single crystal layer 122. The additional thickness allows for removal of damaged thin portions of the transferred substantially single crystal layer, leaving undamaged portions with a desired final thickness.
Second, it may be desirable to adjust the overall thickness of the substantially single crystal layer 122. In general, it may be desirable to have the substantially single crystal layer 122 thick enough to provide a high quality lattice template for subsequent growth of one or more epitaxial layers, but thin enough to have high compliance (compliance). When the substantially single-crystal layer 122 is relatively thin such that its physical properties are less constrained and have a low tendency to generate crystalline defects, much like the surrounding materials, the substantially single-crystal layer 122 may be referred to as "compliant". The compliance of the substantially single crystal layer 122 may be inversely related to the thickness of the substantially single crystal layer 122. Higher compliance can result in lower defect density in the epitaxial layer grown on the template and enable thicker epitaxial layer growth. In some embodiments, the thickness of the substantially single crystal layer 122 may be increased by epitaxially growing silicon on the delaminated silicon layer.
Third, it may be beneficial to improve the smoothness of the substantially single crystal layer 122. The smoothness of the layer may be related to the total hydrogen dose, the presence of any co-implant species, and the annealing conditions used to form the hydrogen-cleaved surface. As discussed below, the initial roughness caused by layer transfer (i.e., the dicing step) may be mitigated by thermal oxidation and oxide stripping.
In some embodiments, removal of the damaged layer and adjustment of the final thickness of the substantially single crystal layer 122 may be achieved by thermal oxidation of the top of the stripped silicon layer followed by oxide layer stripping with Hydrofluoric (HF) acid. For example, a stripped silicon layer having an initial thickness of 0.5 μm may be thermally oxidized to produce a silicon dioxide layer about 420nm thick. After removal of the grown thermal oxide, the remaining silicon thickness in the transfer layer may be about 53 nm. During thermal oxidation, the implanted hydrogen can migrate towards the surface. Thus, subsequent oxide layer stripping can remove some of the damage. Furthermore, thermal oxidation is generally carried out at a temperature of 1000 ℃ or higher. Elevated temperatures can also repair lattice damage.
The silicon oxide layer formed on top of the substantially single crystal layer during the thermal oxidation may be stripped using an HF acid etch. By adjusting the temperature and concentration of the HF solution and the stoichiometry and density of the silica, the HF acid concentration in the silica and Silicon (SiO) can be adjusted2: si) etch selectivity. Etch selectivity refers to the etch rate of one material relative to another. For (SiO)2: si), the selectivity of the HF solution may range from about 10: 1 to about 100: 1. the high etch selectivity may reduce the surface roughness by a factor similar to the initial surface roughness. However, the surface roughness of the resulting substantially single crystal layer 122 may still be greater than desired. For example, the bulk Si (111) surface may have a Root Mean Square (RMS) surface roughness of less than 0.1nm, as determined by 2 μm x 2 μm Atomic Force Microscope (AFM) scanning prior to additional processing. In some embodiments, the desired surface roughness of epitaxially grown gallium nitride material on Si (111) may be, for example, less than 1nm, less than 0.5nm, or less than 0.2nm in a 30 μm x 30 μm AFM scan region.
Additional surface smoothing may be performed if the surface roughness of the substantially single crystal layer 122 after thermal oxidation and oxide layer stripping exceeds a desired surface roughness. There are several ways to smooth the silicon surface. These methods may include hydrogen annealing, laser trimming, plasma smoothing, and touch polishing (e.g., chemical mechanical polishing or CMP). These methods may involve preferential erosion of high aspect ratio surface peaks. Thus, high aspect ratio features on a surface may be removed faster than low aspect ratio features, resulting in a smoother surface.
It should be understood that the specific steps shown in FIG. 5 provide a particular method of fabricating an engineered substrate according to an embodiment of the invention. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments of the present invention may perform the steps outlined above in a different order. Moreover, the individual steps illustrated in fig. 5 may include multiple sub-steps that may be performed in various sequences as appropriate to the individual step. In addition, additional steps may be added or removed depending on the particular application. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.
Fig. 6 is a simplified schematic diagram illustrating an epitaxial/engineered substrate structure for RF and power applications according to an embodiment of the present invention. In some LED applications, the engineered substrate structure provides a growth substrate capable of growing high quality GaN layers, and the engineered substrate structure is subsequently removed. However, for RF and power device applications, the engineered substrate structure forms part of the finished device, and thus, the electrical, thermal, and other properties of the engineered substrate structure or components of the engineered substrate structure are important for the particular application.
Referring to fig. 1, a single crystal silicon layer 122 is typically an exfoliation layer separated from a silicon donor wafer using implantation and exfoliation techniques. Typical implants are hydrogen and boron. For power and RF device applications, it is important to engineer the electrical properties of the layers and materials in the substrate structure. For example, some device architectures utilize a resistance greater than 103An Ohm-cm (Ohm-cm) high insulating silicon layer to reduce or eliminate leakage through the substrate and the interface layer. Other applications utilize designs that include a conductive silicon layer of a predetermined thickness (e.g., 1 μm) to connect the source of the device to other components. Therefore, in these applications, control of the monocrystalline silicon layer is requiredSize and nature. In designs that use implantation and lift-off techniques during layer transfer, residual implanted atoms, such as hydrogen or boron, are present in the silicon layer, thereby altering the electrical properties. In addition, it may be difficult to control the thickness, conductivity, and other properties of the thin silicon layer using, for example, adjustments in implant dose, surface roughness, and cleaved surface position accuracy, which may affect the conductivity of the implant profile and the full width at half maximum (FWHM) of the semiconductor, and adjustments using implant depth, which may affect the layer thickness.
According to embodiments of the present invention, silicon epitaxy on an engineered substrate structure is utilized to achieve desired characteristics of a single crystal silicon layer suitable for a particular device design.
Referring to fig. 6, an epitaxial/engineered substrate structure 600 includes an engineered substrate structure 610 and a silicon epitaxial layer 620 formed thereon. The engineered substrate structure 610 may be similar to the engineered substrate structures shown in fig. 1,3, and 4. Typically, after layer transfer, the substantially single crystal silicon layer 122 is on the order of about 0.5 μm. In some processes, the thickness of the monocrystalline silicon layer 122 may be reduced to about 0.3 μm using a surface conditioning process. In order to increase the thickness of the single crystal silicon layer to about 1 μm for achieving a reliable ohmic contact, an epitaxial single crystal silicon layer 620 is grown on the substantially single crystal silicon layer 122 formed by the layer transfer process using, for example, an epitaxial process. The epitaxial single crystal silicon layer 620 may be grown using various epitaxial growth processes including CVD, ALD, MBE, and the like. The thickness of the epitaxial single crystal silicon layer 620 may be in a range of about 0.1 μm to about 20 μm, for example, between 0.1 μm and 10 μm.
Fig. 7 is a simplified schematic diagram illustrating a III-V epitaxial layer on an engineered substrate structure in accordance with an embodiment of the invention. The structure shown in fig. 7 may be referred to as a double-epitaxial structure as described below. As shown in fig. 7, an engineered substrate structure 710 comprising an epitaxial single crystal silicon layer 620 has a III-V epitaxial layer 720 formed thereon. In one embodiment, the III-V epitaxial layer includes gallium nitride (GaN).
The desired thickness of the III-V epitaxial layer 720 may vary significantly depending on the desired functionality. In some embodiments, the thickness of the III-V epitaxial layer 720 may vary between 0.5 μm and 100 μm, for example, greater than 5 μm. The resulting breakdown voltage of devices fabricated on III-V epitaxial layer 720 may vary depending on the thickness of III-V epitaxial layer 720. Some embodiments provide a breakdown voltage of at least 100V, 300V, 600V, 1.2kV, 1.7kV, 3.3kV, 5.5kV, 13kV, or 20 kV.
To provide electrical conductivity between portions of the III-V epitaxial layer 720 (which may include multiple sublayers), a set of vias (vias)724 are formed, in this example, the vias 724 pass through the top surface of the III-V epitaxial layer 720 into the epitaxial single crystal silicon layer 620. The vias 724 are lined with an insulating layer (not shown) so that they are insulated from the III-V epitaxial layer 720. As an example, these vias may be used to connect the electrodes of a diode or transistor to the underlying silicon layer by providing an ohmic contact through the via, thereby discharging the charge accumulated in the device.
Such ohmic contact through vias is difficult to achieve if III-V epitaxial layers are grown on single crystal silicon layer 122 because it would be difficult to terminate the via etch in single crystal silicon layer 122: for example, etching through 5 μm of GaN and reliably stopping the etch in a 0.3 μm silicon layer across the wafer. Single crystal silicon layers with thicknesses of many microns can be provided using embodiments of the present invention, which are difficult to achieve using implantation and lift-off processes because of the high implantation energies required to achieve large implantation depths. In turn, the thick silicon layer enables applications such as the illustrated vias, which enable a wide variety of device designs.
In addition to increasing the thickness of the silicon "layer" by epitaxially growing a single crystal silicon layer 620 on the single crystal silicon layer 122, other adjustments to the original properties of the single crystal silicon layer 122 may be made, including modifications to conductivity, crystallinity, and the like. Such thick layers may be grown according to embodiments of the present invention, for example, if a silicon layer on the order of 10 μm is required prior to additional epitaxial growth of the III-V layer or other material.
Because the implantation process may affect the properties of single crystal silicon layer 122, for example, residual boron/hydrogen atoms may affect the electrical properties of silicon, embodiments of the present invention remove a portion of single crystal silicon layer 122 prior to epitaxial growth of single crystal silicon layer 620. For example, the single crystal silicon layer 122 may be thinned to form a layer having a thickness of 0.1 μm or less, removing most or all of the remaining boron/hydrogen atoms. Subsequent growth of the single crystal silicon layer 620 is then used to provide a single crystal material having electrical and/or other properties substantially independent of the corresponding properties of the layer formed using the layer transfer process.
In addition to increasing the thickness of the single crystal silicon material coupled to the engineered substrate structure, the electrical properties (including the conductivity of the epitaxial single crystal silicon layer 620) may be different from the electrical properties of the single crystal silicon layer 122. Doping of the epitaxial single crystal silicon layer 620 during growth can produce p-type silicon by doping with boron and n-type silicon by doping with phosphorus. Undoped silicon may be grown to provide high resistivity silicon for use in devices having insulating regions. In particular, the insulating layer may be used in RF devices.
The lattice constant of epitaxial single crystal silicon layer 620 may be adjusted during growth to be different from the lattice constant of single crystal silicon layer 122 to produce a strained epitaxial material. In addition to silicon, other elements may be epitaxially grown to provide a layer including a strained layer (which includes silicon germanium, etc.). For example, a buffer layer may be grown on monocrystalline silicon layer 122, on epitaxial monocrystalline silicon layer 620, or between layers to enhance subsequent epitaxial growth. These buffer layers may include strained III-V layers, silicon germanium strained layers, and the like. In addition, the buffer layer and other epitaxial layers may be graded in mole fraction, dopant, polarity, etc. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.
In some embodiments, the strain present in monocrystalline silicon layer 122 or epitaxial monocrystalline silicon layer 620 may be relieved during growth of subsequent epitaxial layers (including III-V epitaxial layers).
FIG. 8 is a simplified flow diagram illustrating a method of fabricating an engineered substrate according to another embodiment of the invention. The method includes forming a support structure by providing a polycrystalline ceramic core (810), forming a first adhesion layer (812) coupled to at least a portion of the polycrystalline ceramic core. The first adhesion layer may include a tetraethyl orthosilicate (TEOS) layer. The method also includes forming a conductive layer (814) coupled to the first adhesion layer. The conductive layer may be a polysilicon layer. The first adhesion layer may be formed as a single layer of TEOS. The conductive layer may be formed as a single layer of polysilicon.
The method also includes forming a second adhesive layer (816) coupled to at least a portion of the conductive layer and forming a barrier shell (818). The second adhesion layer may be formed as a single layer of TEOS. The barrier shell may be formed as a single layer of silicon nitride or a series of sub-layers forming the barrier shell.
Once the support structure is formed via step 810-818, the method further includes bonding a bonding layer (e.g., a silicon oxide layer) to the support structure (820), and bonding a substantially single crystal silicon layer or a substantially single crystal layer to the silicon oxide layer (822). Bonding of the bonding layer may include deposition of a bonding material followed by a planarization process as described herein.
A layer transfer process may be used to bond the substantially single crystal silicon layer 122 to the bonding layer 120. In some embodiments, a silicon wafer is implanted (e.g., a silicon (111) wafer) to form a cleave plane. After wafer bonding, the silicon substrate may be removed along with a portion of the single crystal silicon layer below the cleave plane, resulting in the delaminated single crystal silicon layer 122 shown in fig. 1. The thickness of the substantially single crystal silicon layer 122 may vary to meet the specifications of various applications. In addition, the crystal orientation of the substantially single crystal layer 122 may be changed to meet the specifications of the application. In addition, the doping level and profile in the substantially single crystal layer 122 may be varied to meet the specifications of a particular application. In some embodiments, the substantially single crystal silicon layer 122 may be smoothed as described above.
The method shown in fig. 8 may further include forming an epitaxial silicon layer by epitaxial growth on the substantially single crystal silicon layer (824), and forming an epitaxial III-V layer by epitaxial growth on the epitaxial silicon layer (826). In some embodiments, the epitaxial III-V layer may include gallium nitride (GaN).
It should be understood that the specific steps shown in fig. 8 provide a particular method of fabricating an engineered substrate according to another embodiment of the invention. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments of the present invention may perform the steps outlined above in a different order. Moreover, the individual steps illustrated in fig. 8 may include multiple sub-steps that may be performed in various sequences as appropriate to the individual step. In addition, additional steps may be added or removed depending on the particular application. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.
It is also understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims.

Claims (39)

1. A method of manufacturing a substrate, the method comprising:
forming a support structure by:
providing a polycrystalline ceramic core;
forming a first adhesion layer coupled to the polycrystalline ceramic core;
forming a conductive layer coupled to the first adhesion layer;
forming a second adhesion layer coupled to the conductive layer; and
forming a barrier layer coupled to the second adhesion layer;
forming a bonding layer coupled to the support structure;
bonding a substantially single crystal silicon layer to the bonding layer; and
one or more epitaxial III-V layers are formed that are coupled to the substantially single crystal silicon layer.
2. The method of claim 1, wherein the polycrystalline ceramic core comprises aluminum nitride.
3. The method of claim 2, wherein the one or more epitaxial III-V layers comprise an epitaxial gallium nitride layer.
4. The method of claim 3, wherein the epitaxial gallium nitride layer has a thickness of about 5 μm or greater.
5. The method of claim 3, wherein the one or more epitaxial III-V layers further comprise an epitaxial aluminum nitride layer, or an epitaxial aluminum gallium nitride layer, or a combination thereof.
6. The method of claim 1, wherein the bonding of the substantially single crystal silicon layer is performed by lift-off.
7. The method of claim 6, further comprising, prior to forming the one or more epitaxial III-V layers:
forming an epitaxial silicon layer coupled to the substantially single crystal silicon layer; wherein the one or more epitaxial III-V layers are coupled to the epitaxial silicon layer.
8. The method of claim 7, wherein the epitaxial silicon layer is strained.
9. The method of claim 1, wherein:
the first adhesion layer comprises tetraethyl orthosilicate (TEOS);
the conductive layer comprises polysilicon;
the second adhesion layer comprises tetraethyl orthosilicate;
the barrier layer comprises silicon nitride; and
the bonding layer includes silicon oxide.
10. The method of claim 9, wherein:
the first adhesion layer encapsulates the polycrystalline ceramic core;
the conductive layer encapsulates the first adhesive layer;
the second adhesive layer encapsulates the conductive layer; and
the barrier layer encapsulates the second adhesive layer.
11. An engineered substrate structure comprising:
a support structure, comprising:
a polycrystalline ceramic core;
a first adhesion layer coupled to the polycrystalline ceramic core;
a conductive layer coupled to the first adhesion layer;
a second adhesion layer coupled to the conductive layer; and
a barrier layer coupled to the second adhesion layer;
a bonding layer coupled to the support structure; and
a substantially single crystalline gallium oxide layer coupled to the bonding layer.
12. The engineered substrate structure of claim 11, wherein the polycrystalline ceramic core comprises aluminum nitride.
13. The engineered substrate structure of claim 12, wherein:
the first adhesion layer comprises a first Tetraethylorthosilicate (TEOS) layer encapsulating the polycrystalline ceramic core;
the conductive layer comprises a polysilicon layer encapsulating the first tetraethoxyorthosilicate layer;
the second adhesion layer comprises a second tetraethoxyorthosilicate layer encapsulating the polysilicon layer;
the barrier layer comprises a silicon nitride layer encapsulating the second tetraethoxyorthosilicate layer; and
the bonding layer includes silicon oxide.
14. The engineered substrate structure of claim 11, wherein the substantially single-crystal gallium oxide layer comprises a lift-off single-crystal gallium oxide layer.
15. The engineered substrate structure of claim 14, further comprising:
an epitaxial gallium oxide layer coupled to the substantially single-crystal gallium oxide layer.
16. The engineered substrate structure of claim 11, wherein the substantially single-crystal gallium oxide layer comprises a stripped single-crystal gallium oxide layer and an epitaxial gallium oxide layer grown on the stripped single-crystal gallium oxide layer.
17. The engineered substrate structure of claim 16, further comprising:
an epitaxial layer coupled to the substantially single-crystal gallium oxide layer.
18. The engineered substrate structure of claim 17, wherein the epitaxial layer comprises an epitaxial III-V layer.
19. The engineered substrate structure of claim 18, wherein the epitaxial III-V layers comprise epitaxial gallium nitride layers and/or epitaxial aluminum gallium nitride layers.
20. The engineered substrate structure of claim 17, further comprising a plurality of vias passing from the epitaxial layer to the epitaxial gallium oxide layer.
21. The engineered substrate structure of claim 17, further comprising one or more buffer layers disposed between the substantially single-crystal gallium oxide layer and the epitaxial layer.
22. A substrate, comprising:
a support structure, the support structure comprising:
a polycrystalline ceramic core;
a first adhesion layer coupled to the polycrystalline ceramic core;
a conductive layer coupled to the first adhesion layer;
a second adhesion layer coupled to the conductive layer; and
a barrier layer coupled to the second adhesion layer;
a bonding layer coupled to the support structure;
a substantially single crystalline gallium oxide layer coupled to the bonding layer; and
an epitaxial layer coupled to the substantially single-crystal gallium oxide layer.
23. The substrate of claim 22, wherein the polycrystalline ceramic core comprises aluminum nitride.
24. The substrate of claim 23, wherein the bonding layer comprises silicon oxide.
25. The substrate of claim 22, wherein the epitaxial layer comprises an epitaxial III-V layer.
26. The substrate of claim 25, wherein the epitaxial III-V layer comprises an epitaxial gallium nitride layer.
27. The substrate of claim 22, wherein the epitaxial layer has a thickness of about 5 μ ι η or greater.
28. The substrate of claim 22, wherein the substantially single-crystal gallium oxide layer comprises a lift-off gallium oxide layer.
29. The substrate of claim 22, wherein the substantially single-crystal gallium oxide layer comprises a lift-off gallium oxide layer and an epitaxial gallium oxide layer on the lift-off gallium oxide layer.
30. The substrate of claim 22, wherein:
the polycrystalline ceramic core comprises polycrystalline gallium nitride;
the first adhesion layer comprises tetraethyl orthosilicate (TEOS);
the conductive layer comprises polysilicon;
the second adhesion layer comprises tetraethyl orthosilicate;
the barrier layer comprises silicon nitride; and
the bonding layer includes silicon oxide.
31. A substrate, comprising:
a support structure, the support structure comprising:
a polycrystalline ceramic core;
a first adhesion layer coupled to the polycrystalline ceramic core;
a conductive layer coupled to the first adhesion layer;
a second adhesion layer coupled to the conductive layer; and
a barrier layer coupled to the second adhesion layer;
a bonding layer coupled to the support structure;
a single crystal silicon layer coupled to the bonding layer; and
an epitaxial III-V layer coupled to the monocrystalline silicon layer or an epitaxial monocrystalline silicon layer coupled to the monocrystalline silicon layer.
32. The substrate of claim 31, wherein the polycrystalline ceramic core comprises aluminum nitride.
33. The substrate of claim 31, wherein the epitaxial III-V layer comprises an epitaxial gallium nitride layer.
34. The substrate of claim 33, wherein the epitaxial gallium nitride layer has a thickness of 5 μ ι η or greater.
35. The substrate of claim 31, wherein the single crystal silicon layer comprises a delaminated silicon layer and an epitaxial silicon layer grown on the delaminated silicon layer, and wherein the single crystal silicon layer has a thickness of 0.5 μ ι η.
36. The substrate of claim 31, wherein:
the first adhesion layer comprises a first Tetraethylorthosilicate (TEOS) layer encapsulating the polycrystalline ceramic core;
the conductive layer comprises a polysilicon layer encapsulating the first tetraethoxyorthosilicate layer;
the second adhesion layer comprises a second tetraethoxyorthosilicate layer encapsulating the polysilicon layer; and
the barrier layer includes a silicon nitride layer encapsulating the second tetraethoxyorthosilicate layer.
37. The substrate of claim 36, wherein:
the thickness of the first tetraethoxyorthosilicate layer is 100 nm;
the thickness of the polycrystalline silicon layer is 300 nm;
the thickness of the second tetraethoxyorthosilicate layer is 100 nm; and
the thickness of the silicon nitride layer is 400 nm.
38. The substrate of claim 31, wherein the bonding layer is a silicon oxide layer.
39. The substrate of claim 31, wherein the substrate comprises the epitaxial single crystal silicon layer, wherein the substrate further comprises an epitaxial III-V layer coupled to the epitaxial single crystal silicon layer and a plurality of vias passing from the epitaxial III-V layer to the epitaxial single crystal silicon layer.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110383420A (en) * 2017-02-21 2019-10-25 克罗米斯有限公司 The RF device being integrated on engineering substrate

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10297445B2 (en) 2016-06-14 2019-05-21 QROMIS, Inc. Engineered substrate structure for power and RF applications
TWI743136B (en) * 2016-06-14 2021-10-21 美商克若密斯股份有限公司 Engineered substrate structure for power and rf applications
US10734303B2 (en) * 2017-11-06 2020-08-04 QROMIS, Inc. Power and RF devices implemented using an engineered substrate structure
US10586844B2 (en) * 2018-01-23 2020-03-10 Texas Instruments Incorporated Integrated trench capacitor formed in an epitaxial layer
TWI692869B (en) * 2019-05-03 2020-05-01 世界先進積體電路股份有限公司 Substrates and methods for forming the same
CN111987140A (en) * 2019-05-21 2020-11-24 世界先进积体电路股份有限公司 Substrate and method for manufacturing the same
JP7319227B2 (en) 2020-05-11 2023-08-01 信越化学工業株式会社 BASE SUBSTRATE FOR III-V COMPOUND CRYSTAL AND METHOD FOR MANUFACTURING THE SAME
KR20230020968A (en) 2020-06-09 2023-02-13 신에쓰 가가꾸 고교 가부시끼가이샤 Group III nitride substrate for epitaxial growth and its manufacturing method
JP2022012558A (en) 2020-07-01 2022-01-17 信越化学工業株式会社 Substrate for large-bore group iii nitride-based epitaxial growth, and production method thereof
KR102446604B1 (en) * 2021-01-04 2022-09-26 한국과학기술원 Growth structure for strained channel, and methods for manufacturing strained channel and device using the same
CN116848296A (en) 2021-02-05 2023-10-03 信越半导体株式会社 Nitride semiconductor substrate and method for manufacturing same
JP2022131086A (en) 2021-02-26 2022-09-07 信越半導体株式会社 Nitride semiconductor substrate and manufacturing method for the same
WO2022191079A1 (en) * 2021-03-10 2022-09-15 信越化学工業株式会社 Seed substrate for epitaxial growth use and method for manufacturing same, and semiconductor substrate and method for manufacturing same
CN117413345A (en) * 2021-06-08 2024-01-16 信越半导体株式会社 Nitride semiconductor substrate and method for manufacturing same
JP2023025432A (en) * 2021-08-10 2023-02-22 信越半導体株式会社 Nitride semiconductor substrate and method for producing the same
JPWO2023047864A1 (en) * 2021-09-21 2023-03-30
JPWO2023063278A1 (en) * 2021-10-15 2023-04-20
WO2023063046A1 (en) * 2021-10-15 2023-04-20 信越半導体株式会社 Nitride semiconductor substrate and manufacturing method therefor
JP2023065227A (en) 2021-10-27 2023-05-12 信越化学工業株式会社 Epitaxial growth seed substrate, method for manufacturing the same, semiconductor substrate and method for manufacturing the same
JP2023098137A (en) * 2021-12-28 2023-07-10 信越化学工業株式会社 Substrate for high characteristic epitaxial growth and method for manufacturing the same
JP2024070722A (en) * 2022-11-11 2024-05-23 信越半導体株式会社 Substrate for high frequency device and method for manufacturing same

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4430149A (en) * 1981-12-30 1984-02-07 Rca Corporation Chemical vapor deposition of epitaxial silicon
US7238595B2 (en) * 2003-03-13 2007-07-03 Asm America, Inc. Epitaxial semiconductor deposition methods and structures
US6972255B2 (en) * 2003-07-28 2005-12-06 Freescale Semiconductor, Inc. Semiconductor device having an organic anti-reflective coating (ARC) and method therefor
US20060284167A1 (en) * 2005-06-17 2006-12-21 Godfrey Augustine Multilayered substrate obtained via wafer bonding for power applications
US7420226B2 (en) * 2005-06-17 2008-09-02 Northrop Grumman Corporation Method for integrating silicon CMOS and AlGaN/GaN wideband amplifiers on engineered substrates
CN100424878C (en) * 2006-11-21 2008-10-08 华中科技大学 Ferroelectric film capacity used for ferroelectric memorizer and its manufacturing method
CN101192533B (en) * 2006-11-28 2010-06-16 中芯国际集成电路制造(上海)有限公司 Semiconductor device and manufacturing method thereof, and etch stop layer forming method
FR2912552B1 (en) * 2007-02-14 2009-05-22 Soitec Silicon On Insulator MULTILAYER STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
US7732301B1 (en) * 2007-04-20 2010-06-08 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
CN101669193B (en) * 2007-04-27 2012-02-15 株式会社半导体能源研究所 Soi substrate and manufacturing method of the same, and semiconductor device
US20090278233A1 (en) * 2007-07-26 2009-11-12 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
CN101621005B (en) * 2008-07-02 2012-08-22 中芯国际集成电路制造(上海)有限公司 TFT MONOS or SONOS memory cell structure
US7915645B2 (en) * 2009-05-28 2011-03-29 International Rectifier Corporation Monolithic vertically integrated composite group III-V and group IV semiconductor device and method for fabricating same
CN102044473B (en) * 2009-10-13 2013-03-06 中芯国际集成电路制造(上海)有限公司 Formation method of semiconductor device
US9012253B2 (en) * 2009-12-16 2015-04-21 Micron Technology, Inc. Gallium nitride wafer substrate for solid state lighting devices, and associated systems and methods
KR20120020526A (en) * 2010-08-30 2012-03-08 삼성전자주식회사 Substrate have buried conductive layer and formation method thereof, and fabricating method of semiconductor device using the same
CN102456721A (en) * 2010-10-17 2012-05-16 金木子 Gallium nitride-based chip with ceramic substrate and manufacturing method
US8546165B2 (en) * 2010-11-02 2013-10-01 Tsmc Solid State Lighting Ltd. Forming light-emitting diodes using seed particles
KR20140017515A (en) * 2010-12-14 2014-02-11 헥사테크, 인크. Thermal expansion engineering for polycrystalline aluminum nitride sintered bodies, and application to the manufacture of semi-conductors
JP2012142385A (en) * 2010-12-28 2012-07-26 Sumitomo Electric Ind Ltd Semiconductor device manufacturing method
US8916483B2 (en) 2012-03-09 2014-12-23 Soitec Methods of forming semiconductor structures including III-V semiconductor material using substrates comprising molybdenum
JP6152548B2 (en) * 2012-08-06 2017-06-28 並木精密宝石株式会社 Gallium oxide substrate and manufacturing method thereof
US9082692B2 (en) * 2013-01-02 2015-07-14 Micron Technology, Inc. Engineered substrate assemblies with epitaxial templates and related systems, methods, and devices
US9650723B1 (en) * 2013-04-11 2017-05-16 Soraa, Inc. Large area seed crystal for ammonothermal crystal growth and method of making
JP6176069B2 (en) * 2013-11-13 2017-08-09 住友電気工業株式会社 Group III nitride composite substrate and method for manufacturing the same, laminated group III nitride composite substrate, group III nitride semiconductor device and method for manufacturing the same
JP6488917B2 (en) * 2014-07-04 2019-03-27 三菱マテリアル株式会社 Power module substrate with heat sink and power module
JP2016058693A (en) * 2014-09-12 2016-04-21 株式会社東芝 Semiconductor device, semiconductor wafer, and method of manufacturing semiconductor device
US9997391B2 (en) * 2015-10-19 2018-06-12 QROMIS, Inc. Lift off process for chip scale package solid state devices on engineered substrate
WO2017096032A1 (en) * 2015-12-04 2017-06-08 Quora Technology, Inc. Wide band gap device integrated circuit architecture on engineered substrate
TWI743136B (en) * 2016-06-14 2021-10-21 美商克若密斯股份有限公司 Engineered substrate structure for power and rf applications
JP6580267B2 (en) * 2016-07-26 2019-09-25 三菱電機株式会社 Semiconductor device and manufacturing method of semiconductor device
CN109671612B (en) * 2018-11-15 2020-07-03 中国科学院上海微系统与信息技术研究所 Gallium oxide semiconductor structure and preparation method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110383420A (en) * 2017-02-21 2019-10-25 克罗米斯有限公司 The RF device being integrated on engineering substrate
CN110383420B (en) * 2017-02-21 2023-11-28 克罗米斯有限公司 RF device integrated on engineered substrate

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