TW201807839A - Engineered substrate structure for power and RF applications - Google Patents

Abstract

A substrate includes a support structure comprising: a polycrystalline ceramic core; a first adhesion layer coupled to the polycrystalline ceramic core; a conductive layer coupled to the first adhesion layer; a second adhesion layer coupled to the conductive layer; and a barrier layer coupled to the second adhesion layer. The substrate also includes a silicon oxide layer coupled to the support structure, a substantially single crystalline silicon layer coupled to the silicon oxide layer, and an epitaxial III-V layer coupled to the substantially single crystalline silicon layer.

Description

Engineering substrate structure for power and RF applications

This patent application claims U.S. Provisional Patent Application No. 62 / 350,084, filed on June 14, 2016, entitled "ENGINEERED SUBSTRATE STRUCTURE FOR POWER AND RF APPLICATIONS" And the priority right of US Provisional Patent Application No. 62 / 350,077, filed on June 14, 2016, entitled "ENGINEERED SUBSTRATE STRUCTURE AND METHOD OF MANUFACTURE" Purpose The entire disclosure of these applications is incorporated herein by reference.

The following two U.S. patent applications are filed concurrently with this application, and the disclosures of both applications are incorporated herein by reference for all purposes:

Application number ______, filed on June 13, 2017, titled "Engineering Substrate Structures for Power and RF Applications (ENGINEERED SUBSTRATE STRUCTURE FOR POWER AND RF APPLICATIONS)" (Agent Case No. 098825-1049529-001110US) ),and

Application number ______, filed on June 13, 2017, with the title "ENGINEERED SUBSTRATE STRUCTURE AND METHOD OF MANUFACTURE" (Agent Case No. 098825-1049532-001610US).

The present invention generally relates to an engineering substrate structure. More specifically, the present invention relates to methods and systems suitable for epitaxial growth processes.

The structure of a light emitting diode (LED) is usually epitaxially grown on a sapphire substrate. Many products currently use LED components, including lighting, computer monitors, and other display devices.

Growing a GaN series LED structure on a sapphire substrate is a heteroepitaxial growth process because the substrate and the epitaxial layer are composed of different materials. Due to the heteroepitaxial growth process, epitaxially grown materials can exhibit various adverse effects, including reduced uniformity and reduced metrics related to the electronic / optical characteristics of the epitaxial layer. Therefore, there is a need in the art for improved methods and systems related to epitaxial growth processes and substrate structures.

The present invention generally relates to an engineering substrate structure. More specifically, the present invention relates to methods and systems suitable for epitaxial growth processes. For example only, the present invention has been applied to a method and system for providing a substrate structure suitable for epitaxial growth, the substrate structure being characterized by a coefficient of thermal expansion (CTE) substantially matching the epitaxial layer grown thereon. The methods and techniques can be applied to a wide variety of semiconductor processing operations.

According to an embodiment of the present invention, a substrate is provided. The substrate includes a support structure including: a polycrystalline ceramic core; a first adhesive layer coupled to the polycrystalline ceramic core; a conductive layer coupled to the first adhesive layer; and a first conductive layer coupled to the conductive layer. Two adhesive layers; and a barrier layer coupled to the second adhesive layer. The substrate further includes a silicon oxide layer coupled to the support structure, a substantially single crystal silicon layer coupled to the silicon oxide layer, and an epitaxial III-V layer coupled to the substantially single crystal silicon layer.

According to another embodiment of the present invention, a method for manufacturing a substrate is provided. The method includes forming a support structure by the following steps: providing a polycrystalline ceramic core; encapsulating the polycrystalline ceramic core in a first adhesive shell; encapsulating the first adhesive shell in a conductive shell; encapsulating the conductive shell Enclosed in a second adhesive shell; and encapsulated in the second adhesive shell. The method further includes bonding a bonding layer to the support structure, bonding a substantially single crystal silicon layer to the bonding layer, forming an epitaxial silicon layer by epitaxial growth on the substantially single crystal silicon layer, and Epitaxial growth on the epitaxial silicon layer forms an epitaxial III-V layer.

According to a specific embodiment of the present invention, an engineering substrate structure is provided. The engineering substrate structure includes a supporting structure, a bonding layer coupled to the supporting structure, a substantially single crystal silicon layer coupled to the bonding layer, and an epitaxial single crystal silicon layer coupled to the substantially single crystal silicon layer. The support structure includes a polycrystalline ceramic core, a first adhesive layer coupled to the polycrystalline ceramic core, a conductive layer coupled to the first adhesive layer, a second adhesive layer coupled to the conductive layer, and a coupling. To the barrier shell of the second adhesive layer.

Many advantages are achieved through the present invention over conventional techniques. For example, embodiments of the present invention provide an engineering substrate structure with a CTE matched to a gallium nitride series epitaxial layer suitable for optical, electronic, and optoelectronic applications. The encapsulation layer serving as a component of the engineering substrate structure prevents impurities existing in the central portion of the substrate from diffusing to reach the semiconductor processing environment using the engineering substrate. Key characteristics related to substrate materials, including thermal expansion coefficient, lattice mismatch, thermal stability, and shape control are independently designed to improve (eg, optimize) matching to GaN epitaxy and device layers, and Matching with different component architectures and performance goals. Because the substrate material layers are integrated together in traditional semiconductor manufacturing processes, process integration is simplified. These and other embodiments of the present invention and many of its advantages and features are described in more detail in conjunction with the following and drawings.

The embodiment of the present invention relates to an engineering substrate structure. More specifically, the present invention relates to methods and systems suitable for epitaxial growth processes. For example only, the present invention has been applied to a method and system for providing a substrate structure suitable for epitaxial growth, the substrate structure being characterized by a coefficient of thermal expansion (CTE) substantially matching the epitaxial layer grown thereon. The methods and techniques can be applied to a wide variety of semiconductor processing operations.

FIG. 1 is a simplified diagram illustrating a structure of an engineering substrate according to an embodiment of the present invention. The engineering substrate 100 illustrated in Figure 1 is suitable for a wide variety of electronic and optical applications. The engineering substrate includes a core 110 that may have a CTE that substantially matches a coefficient of thermal expansion (CTE) of an epitaxial material to be grown on the engineering substrate 100. The epitaxial material 130 is illustrated as optional because the epitaxial material 130 is not required as an element of the engineering substrate, but the epitaxial material 130 will usually be grown on the engineering substrate.

For applications including the growth of gallium nitride (GaN) series materials (including epitaxial layers of GaN series layers), the core 110 may be a polycrystalline ceramic material, such as polycrystalline aluminum nitride (AlN), polycrystalline nitride Aluminum (AlN) may include a bonding material such as yttrium oxide. Other materials can be used for the core 110, including polycrystalline gallium nitride (GaN), polycrystalline aluminum gallium nitride (AlGaN), polycrystalline silicon carbide (SiC), polycrystalline zinc oxide (ZnO), polycrystalline gallium trioxide ( Ga ₂ O ₃ ) and the like.

The thickness of the core can be on the order of 100 μm to 1,500 μm, such as 725 μm. The core 110 is encapsulated in the first adhesive layer 112. The first adhesive layer 112 may be referred to as a shell or an encapsulating shell. In one embodiment, the first adhesive layer 112 includes a tetraethyl orthosilicate (TEOS) layer having a thickness on the order of 1,000 Å. In other embodiments, the thickness of the first adhesive layer varies, for example, from 100 Å to 2,000 Å. Although TEOS is used for the adhesive layer in some embodiments, according to one embodiment of the present invention, other materials may be used to provide adhesion between the subsequently deposited layer and the underlying layer or material (such as ceramic, especially polycrystalline ceramic). For example, SiO ₂ or other silicon oxides (Si _x O _y ) adhere well to ceramic materials and provide a suitable surface for subsequent deposition, such as conductive materials. In some embodiments, the first adhesive layer 112 completely surrounds the core 110 to form a fully encapsulated core, and the LPCVD process can be used to form the first adhesive layer 112. The first adhesive layer 112 provides a surface, and subsequent layers are adhered to the surface to form components of the engineering substrate structure.

In addition to using the LPCVD process, the furnace-based process, and the like to form the encapsulated first adhesive layer, embodiments of the present invention may use other semiconductor processes, including a CVD process or a similar deposition process. As an example, a deposition process that coats a portion of the core can be used, the core can be turned over, and the deposition process can be repeated to coat other portions of the core. Therefore, although LPCVD technology is used to provide a fully encapsulated structure in some embodiments, other film formation technologies can be used depending on the particular application.

A conductive layer 114 is formed surrounding the adhesive layer 112. In one embodiment, the conductive layer 114 is a polycrystalline silicon (ie, polycrystalline silicon) shell formed around the first adhesive layer 112 because the polycrystalline silicon exhibits poor adhesion to ceramic materials. In embodiments where the conductive layer is polycrystalline silicon, the thickness of the polycrystalline silicon layer may be on the order of 500-5,000 Å, such as 2,500 Å. In some embodiments, the polycrystalline silicon layer can be formed as a shell that completely surrounds the first adhesive layer 112 (eg, a TEOS layer), thereby forming a fully encapsulated first adhesive layer, and can be formed using an LPCVD process. In other embodiments, as discussed below, a conductive material may be formed on a portion of the adhesive layer, such as on the lower half of the substrate structure. In some embodiments, the conductive material may be formed as a complete encapsulation layer, and then the conductive material on one side of the substrate structure is removed.

In one embodiment, the conductive layer 114 may be a polycrystalline silicon layer doped to provide a highly conductive material, such as doped with boron to provide a p-type polycrystalline silicon layer. In some embodiments, doping with boron is at a content of 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ to provide high conductivity. Other dopants with different dopant concentrations (eg, phosphorus, arsenic, bismuth, etc., ranging from 1 × 10 ¹⁶ cm ^-3 to 5 × 10 ¹⁸ cm ^-3 ) can be used to provide suitable conductive layers N-type or p-type semiconductor material. Those skilled in the art will recognize many variations, modifications, and alternatives.

The presence of the conductive layer 114 is useful in electrostatically clamping an engineering substrate to a semiconductor processing tool, such as a tool having an electrostatic chuck (ESC). After processing in the semiconductor processing tool, the conductive layer 114 can be quickly released from the clamping. Therefore, embodiments of the present invention provide a substrate structure that can be processed in a manner used in a conventional silicon wafer. Those skilled in the art will recognize many variations, modifications, and alternatives.

A second adhesive layer 116 (eg, a TEOS layer with a thickness of the order of 1000 Å) is formed to surround the conductive layer 114. In some embodiments, the second adhesive layer 116 completely surrounds the conductive layer 114 to form a fully encapsulated structure, and may be formed using an LPCVD process, a CVD process, or any other suitable deposition process, including deposition of a spin-on dielectric.

A barrier layer 118, such as a silicon nitride layer, is formed to surround the second adhesive layer 116. In one embodiment, the barrier layer 118 is a silicon nitride layer 118 having a thickness on the order of 2,000 Å to 5,000 Å. In some embodiments, the barrier layer 118 completely surrounds the second adhesive layer 116 to form a fully encapsulated structure, and can be formed using an LPCVD process. In addition to the silicon nitride layer, amorphous materials (including SiCN, SiON, AlN, SiC, etc.) can be used as the barrier layer. In some implementations, the barrier layer 118 includes several sub-layers that are built to form the barrier layer. Thus, the term barrier layer is not intended to mean a single layer or a single material, but encompasses one or more materials layered in a composite manner. Those skilled in the art will recognize many variations, modifications, and alternatives.

In some embodiments, the barrier layer 118 (eg, a silicon nitride layer) prevents the elements (eg, yttrium oxide (ie, yttrium oxide), oxygen, metal impurities, other trace elements, etc.) existing in the core 110 from diffusing and / or The outgas enters the environment of a semiconductor processing chamber where an engineering substrate may be present, such as during an epitaxial growth process at a high temperature (eg, 1,000 ° C). With the encapsulation layer described herein, ceramic materials can be used in semiconductor process flows and clean room environments, including polycrystalline AlN designed for non-clean room environments.

FIG. 2A is a secondary ion mass spectrometry (SIMS) curve illustrating that the species concentration of the engineering structure is a function of depth according to an embodiment of the present invention. The engineering structure does not include a barrier layer 118. Referring to FIG. 2A, several species (such as yttrium, calcium, and aluminum) present in the ceramic core are reduced to a negligible concentration in the engineering layer 120/122. Calcium, yttrium, and aluminum concentrations decreased by three, four, and six orders of magnitude, respectively.

FIG. 2B is a SIMS curve illustrating an engineering structure without a barrier layer as a function of depth after annealing according to an embodiment of the present invention. As discussed above, during a semiconductor processing operation, such as during the epitaxial growth of a GaN series layer, the engineering substrate structure provided by embodiments of the present invention may be exposed to high temperatures (~ 1,100 ° C) for several hours.

For the curve shown in Figure 2B, the engineering substrate structure was annealed at 1,100 ° C for 4 hours. As shown in Figure 2B, the calcium, yttrium, and aluminum originally present at low concentrations in the freshly deposited untreated sample have diffused into the engineering layer and reached similar concentrations to other elements.

FIG. 2C is a SIMS curve illustrating that the engineering structure with a barrier layer according to an embodiment of the present invention has a species concentration as a function of depth after annealing. Integrating the diffusion barrier layer 118 (such as a silicon nitride layer) into the engineering substrate structure prevents calcium, yttrium, and aluminum, which would occur when the diffusion barrier layer is not present, from diffusing into the engineering layer during the annealing process. As illustrated in Figure 2C, after annealing, the calcium, yttrium, and aluminum present in the ceramic core remain low in the engineering layer. Therefore, the use of the barrier layer 118 (such as a silicon nitride layer) can prevent these elements from diffusing through the diffusion barrier layer, thereby preventing these elements from being released into the environment around the engineering substrate. Similarly, any other impurities contained in the bulk ceramic material will also be contained by the barrier layer.

Generally, the ceramic material used to form the core 110 is fired at a temperature in the range of 1800 ° C. It is expected that this process will drive away a significant amount of impurities present in the ceramic material. Such impurities may include yttrium, calcium, and other elements and compounds generated by using yttrium oxide as a sintering agent. Subsequently, during the epitaxial growth process at a much lower temperature in the range of 800 ° C to 1100 ° C, it is expected that the subsequent diffusion of these impurities will be insignificant. However, contrary to conventional expectations, the inventors determined that a large amount of diffusion of elements through the layer of the engineering substrate occurs even during the epitaxial growth process at a temperature much lower than the firing temperature of the ceramic material. Therefore, the embodiment of the present invention integrates the barrier layer 118 (such as a silicon nitride layer) to prevent background elements from diffusing outward from the polycrystalline ceramic material (such as AlN) to the engineering layer 120/122 and the epitaxial layer (such as optional GaN layer 130). The silicon nitride layer 118, which encapsulates the underlying layers and materials, provides the desired barrier layer function.

As illustrated in FIG. 2B, elements (including yttrium) originally present in the core 110 diffuse into and pass through the first TEOS layer 112, the polycrystalline silicon layer 114, and the second TEOS layer 116. However, the presence of the silicon nitride layer 118 can prevent these elements from diffusing through the silicon nitride layer, thereby preventing these elements from being released into the environment around the engineering substrate, as illustrated in FIG. 2C.

Referring again to FIG. 1, a bonding layer 120 (eg, a silicon oxide layer) is deposited on a portion of the barrier layer 118 (eg, the top surface of the barrier layer), and then the bonding layer is used in the bonding process of the substantially single-crystal silicon layer 122 120. In some embodiments, the thickness of the bonding layer 120 may be about 1.5 μm.

The substantially single crystal layer 122 is suitable for being used as a growth layer during an epitaxial growth process for forming an epitaxial material 130. In some embodiments, the epitaxial material 130 includes a GaN layer having a thickness of 2 μm to 10 μm. The GaN layer may be used as one of a plurality of layers used in optoelectronic components, RF components, power components, and the like. In one embodiment, the substantially single crystal layer 122 includes a substantially single crystal silicon layer attached to the silicon oxide layer 118 using a layer transfer process.

FIG. 3 is a simplified diagram illustrating a structure of an engineering substrate according to an embodiment of the present invention. The engineering substrate 300 illustrated in FIG. 3 is suitable for various electronic and optical applications. The engineering substrate includes a core 110 that may have a CTE that substantially matches a coefficient of thermal expansion (CTE) of the epitaxial material 130 to be grown on the engineering substrate 300. The epitaxial material 130 is illustrated as optional because the epitaxial material 130 is not required as an element of the engineering substrate, but the epitaxial material 130 will usually be grown on the engineering substrate.

For applications including growth of a gallium nitride (GaN) series material (including an epitaxial layer of a GaN series layer), the core 110 may be a polycrystalline ceramic material such as polycrystalline aluminum nitride (AlN). The thickness of the core can be on the order of 100 μm to 1,500 μm, such as 725 μm. The core 110 is encapsulated in the first adhesive layer 112. The first adhesive layer 112 may be referred to as a shell or an encapsulating shell. In this embodiment, the first adhesive layer 112 completely encapsulates the core, but this is not required by the present invention, as discussed in further detail with respect to FIG. 4.

In one embodiment, the first adhesive layer 112 includes a tetraethyl orthosilicate (TEOS) layer having a thickness on the order of 1,000 Å. In other embodiments, the thickness of the first adhesive layer varies, for example, from 100 Å to 2,000 Å. Although TEOS is used for the adhesion layer in some embodiments, according to one embodiment of the present invention, other materials may be used to provide adhesion between the subsequent deposited layer and the underlying layer or material. For example, SiO ₂ , SiON, and the like adhere well to ceramic materials and provide suitable surfaces for subsequent deposition, such as conductive materials. In some embodiments, the first adhesive layer 112 completely surrounds the core 110 to form a fully encapsulated core, and the LPCVD process can be used to form the first adhesive layer 112. The adhesive layer provides a surface, and subsequent layers are adhered to the surface to form components of the engineering substrate structure.

In addition to using an LPCVD process, a furnace-based process, and the like to form the encapsulated adhesive layer, other semiconductor processes can be used according to embodiments of the present invention. As an example, a deposition process (eg, CVD, PECVD, or similar process) that coats a portion of the core can be used, the core can be inverted, and the deposition process can be repeated to coat other parts of the core.

A conductive layer 314 is formed on at least a portion of the first adhesive layer 112. In one embodiment, the conductive layer 314 includes polycrystalline silicon (ie, polycrystalline silicon) formed on a lower portion (such as the lower half or the back side) of the core / adhesive layer structure by a deposition process. In embodiments where the conductive layer is polycrystalline silicon, the thickness of the polycrystalline silicon layer may be on the order of several thousand angstroms, such as 3,000 Å. In some embodiments, a polycrystalline silicon layer can be formed using an LPCVD process.

In one embodiment, the conductive layer 314 may be a polycrystalline silicon layer doped to provide a highly conductive material. For example, the conductive layer 314 may be doped with boron to provide a p-type polycrystalline silicon layer. In some embodiments, doping with boron is at a content ranging from about 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ to provide high conductivity. The presence of a conductive layer is useful in electrostatically clamping an engineering substrate to a semiconductor processing tool, such as a tool with an electrostatic chuck (ESC). The conductive layer 314 can be quickly released after processing. Therefore, embodiments of the present invention provide a substrate structure that can be processed in a manner used in a conventional silicon wafer. Those skilled in the art will recognize many variations, modifications, and alternatives.

A second adhesive layer 316 (eg, a second TEOS layer) is formed to surround the conductive layer 314 (eg, a polycrystalline silicon layer). The thickness of the second adhesive layer 316 is on the order of 1,000 Å. In some embodiments, the second adhesive layer 316 may completely surround the conductive layer 314 and the first adhesive layer 112 to form a completely encapsulated structure, and may be formed using an LPCVD process. In other embodiments, the second adhesive layer 316 only partially surrounds the conductive layer 314, for example, it terminates at the position shown in the plane 317, and the plane 317 can be aligned with the top surface of the conductive layer 314. In this example, the top surface of the conductive layer 314 will be in contact with a portion of the barrier layer 118. Those skilled in the art will recognize many variations, modifications, and alternatives.

A barrier layer 118 (such as a silicon nitride layer) is formed to surround the second adhesive layer 316. In some embodiments, the thickness of the barrier layer 118 is on the order of 4,000 Å to 5,000 Å. In some embodiments, the barrier layer 118 completely surrounds the second adhesive layer 316 to form a fully encapsulated structure, and may be formed using an LPCVD process.

In some embodiments, a silicon nitride barrier layer is used to prevent the elements (such as yttrium oxide (ie, yttrium oxide), oxygen, metal impurities, other trace elements, etc.) existing in the core 110 from diffusing and / or outgassing into the An environment in which a semiconductor processing chamber of an engineering substrate exists, such as during an epitaxial growth process at a high temperature (eg, 1,000 ° C). With the encapsulation layer described herein, ceramic materials can be used in semiconductor process flows and clean room environments, including polycrystalline AlN designed for non-clean room environments.

FIG. 4 is a simplified schematic diagram illustrating a structure of an engineering substrate according to another embodiment of the present invention. In the embodiment illustrated in FIG. 4, the first adhesive layer 412 is formed on at least a portion of the core 110, but does not encapsulate the core 110. In this embodiment, a first adhesive layer 412 is formed on the lower surface of the core 110 (the back side of the core 110) to enhance the adhesion of a conductive layer 414 that is formed later, as described more fully below. Although FIG. 4 only illustrates the adhesive layer 412 on the lower surface of the core 110, it will be understood that depositing the adhesive layer material on other parts of the core will not adversely affect the performance of the engineering substrate structure, and this Similar materials may be present in various embodiments. Those skilled in the art will recognize many variations, modifications, and alternatives.

The conductive layer 414 does not encapsulate the first adhesive layer 412 and the core 110, but is substantially aligned with the first adhesive layer 412. Although the conductive layer 414 is illustrated as extending along the bottom or back side of the first adhesive layer 412 and extending upward along a portion of the side surface of the first adhesive layer 412, extending along the vertical side is not required by the present invention. Therefore, embodiments may utilize deposition on the substrate structure side, masking on the substrate structure side, and the like. The conductive layer 414 may be formed on a portion (eg, bottom / back side) of the first adhesive layer 412. The conductive layer 414 provides electrical conduction on one side of the engineering substrate structure, which may be advantageous in RF and high power applications. The conductive layer may include doped polycrystalline silicon as discussed with respect to the conductive layer 114 in FIG. 1.

A part of the core 110, parts of the first adhesive layer 412, and the conductive layer 414 are covered by the second adhesive layer 416, so as to enhance the adhesion of the barrier layer 418 to the underlying material. As discussed above, the barrier layer 418 forms an encapsulation structure to prevent diffusion from the underlying layers.

In addition to the semiconductor series conductive layer, in other embodiments, the conductive layer 414 is a metal layer, such as 500 Å titanium or the like.

Referring again to Figure 4, depending on the implementation, one or more layers may be removed. For example, the layers 412 and 414 may be removed, leaving only the single adhesive shell 416 and the barrier layer 418. In another embodiment, only layer 414 may be removed. In this embodiment, the layer 412 may also balance the stress and wafer bending caused by the layer 120 deposited on top of the layer 418. The construction of a substrate structure with an insulating layer on the top side of the core 110 (eg, only an insulating layer between the core 110 and the layer 120) will provide benefits for power / RF applications where a highly insulating substrate is required.

In another embodiment, the barrier layer 418 may directly encapsulate the core 110, followed by a conductive layer 414 and a subsequent adhesive layer 416. In this embodiment, the layer 120 may be deposited directly onto the adhesive layer 416 from the top side. In yet another embodiment, an adhesive layer 416 may be deposited on the core 110, followed by a barrier layer 418, then a conductive layer 414, and another adhesive layer 412.

Although some embodiments have been discussed with respect to layers, the term layer should be understood such that a layer may include several sub-layers that are constructed to form a layer of interest. Therefore, the term layer is not intended to mean a single layer composed of a single material, but rather encompasses one or more materials layered in a composite manner to form a desired structure. Those skilled in the art will recognize many variations, modifications, and alternatives.

FIG. 5 is a simplified flowchart illustrating a method for manufacturing an engineering substrate according to an embodiment of the present invention. This method can be used to manufacture a substrate that matches one or more epitaxial layers CTE grown on the substrate. The method 500 includes forming a shell (eg, a tetraethyl orthosilicate (TEOS) shell) by providing a polycrystalline ceramic core (510), encapsulating the polycrystalline ceramic core in a first adhesive layer (512), and The first adhesive layer is encapsulated in a conductive shell (such as a polycrystalline silicon shell) (514) to form a supporting structure. The first adhesive layer may be formed as a single layer of TEOS. The conductive shell can be formed as a single layer of polycrystalline silicon.

The method further includes encapsulating the conductive shell in a second adhesive layer (eg, a second TEOS shell) (516), and encapsulating the second adhesive layer in a barrier layer shell (518). The second adhesive layer may be formed as a single layer of TEOS. The barrier shell can be formed as a single layer of silicon nitride.

Once the support structure is formed by processes 510-518, the method further includes bonding a bonding layer (such as a silicon oxide layer) to the support structure (520), and bonding a substantially single crystal layer (such as a substantially single crystal silicon layer) to the oxide. Silicon layer (522). According to embodiments of the present invention, other substantially single crystal layers may be used, including SiC, sapphire, GaN, AlN, SiGe, Ge, diamond, Ga ₂ O ₃ , ZnO, and the like. The bonding of the bonding layer may include depositing a bonding material and then performing a planarization process as described herein. In the embodiment described below, a substantially single crystal layer (such as a substantially single crystal silicon layer) is connected to a bonding layer system using a layer transfer process, wherein the substantially single crystal layer is a single crystal silicon layer transferred from a silicon wafer.

Referring to FIG. 1, the bonding layer 120 may be formed by depositing a thick (eg, 4 μm thick) oxide layer and then performing a chemical mechanical polishing (CMP) process to thin the oxide to a thickness of about 1.5 μm. The thick initial oxide is used to fill the voids and surface features present on the support structure. These voids and surface features may exist after the polycrystalline core is manufactured and continue to exist when the encapsulation layer shown in FIG. 1 is formed. The CMP process provides a substantially flat surface without voids, particles, or other features, which can then be used during the wafer transfer process to bond a substantially single crystal layer 122 (eg, a substantially single crystal silicon layer) to the bonding layer 120. It will be understood that the bonding layer 120 need not be characterized by an atomically flat surface, but rather should provide a substantially flat surface that will support the bonding of a substantially single crystal layer (eg, a substantially single crystal silicon layer) with the desired reliability.

A layer transfer process may be used to bond the substantially single crystal silicon layer 122 to the bonding layer 120. In some embodiments, a silicon wafer (eg, a silicon (111) wafer) is implanted to form a split surface. After the wafers are bonded, the silicon substrate can be removed together with the portion of the single crystal silicon layer below the split plane, so as to produce the peeled single crystal silicon layer 122 shown in FIG. 1. The thickness of the substantially single crystal layer 122 may be changed to meet the specifications of various applications. In addition, the crystal direction of the substantially single crystal layer 122 can be changed to meet application specifications. In addition, the doping level and distribution in the substantially single crystal layer 122 can be changed to meet the specifications of a particular application.

The method illustrated in FIG. 5 may further include smoothing the substantially single crystal layer (524). In some embodiments, the thickness and surface roughness of the substantially single crystal layer 122 can be modified to obtain high-quality epitaxial growth. Regarding the thickness and surface smoothness of the substantially single crystal layer 122, different element applications may have slightly different specifications. The splitting process causes the substantially single crystal layer 122 to delaminate from the bulk single crystal silicon wafer at the peak of the implant ion distribution. After splitting, the substantially single crystal layer 122 can be adjusted or modified in several ways and then used as a growth surface for epitaxial growth of other materials (such as gallium nitride).

First, the transferred substantially single crystal layer 122 may contain a small amount of residual hydrogen concentration and may have some crystal damage from the cloth plant. Therefore, it may be beneficial to remove the thin portions of the lattice that are damaged in the transferred substantially single crystal layer 122. In some embodiments, the depth of the cloth plant can be adjusted to be greater than the desired final thickness of the substantially single crystal layer 122. The additional thickness allows removal of the damaged thin portion of the transferred substantially single crystal layer, leaving an undamaged portion of the desired final thickness.

Second, the total thickness of the substantially single crystal layer 122 may need to be adjusted. In general, it may be desirable to make the substantially single crystal layer 122 thick enough to provide a high-quality lattice template for subsequent growth of one or more epitaxial layers, but thin enough to be highly compliant. When the substantially single crystal layer 122 is relatively thin, the substantially single crystal layer 122 can be referred to as "compliant", so that the physical properties of the substantially single crystal layer 122 are relatively unrestricted and can simulate the physical properties of surrounding materials, and produce crystals. The tendency to defects is low. The compliance of the substantially single crystal layer 122 may be inversely proportional to the thickness of the substantially single crystal layer 122. Higher compliance results in a lower defect density in the epitaxial layer grown on the template, and the ability to grow a thicker epitaxial layer. In some embodiments, the thickness of the substantially single crystal layer 122 can be increased by epitaxially growing silicon on the stripped silicon layer.

Third, it may be beneficial to improve the smoothness of the substantially single crystal layer 122. The smoothness of the layer may be related to the total hydrogen dose, the presence of any co-plant species, and the annealing conditions used to form the hydrogen-based split plane. The initial roughness resulting from the layer transfer (ie, the splitting step) can be reduced by thermal oxidation and oxide stripping, as discussed below.

In some embodiments, removing the damaged layer and adjusting the final thickness of the substantially single crystal layer 122 may be achieved by thermally oxidizing the top portion of the silicon layer and subsequently stripping the oxide layer using hydrogen fluoride (HF) acid. For example, a stripped silicon layer with an initial thickness of 0.5 μm can be thermally oxidized to produce a silicon dioxide layer that is approximately 420 nm thick. After removing the grown thermal oxide, the remaining silicon thickness in the transfer layer can be about 53 nm. During thermal oxidation, the implanted hydrogen may migrate to the surface. Therefore, subsequent stripping of the oxide layer can remove some damage. And, the thermal oxidation is usually performed at a temperature of 1000 ° C or higher. Elevated temperatures can also repair lattice damage.

The silicon oxide layer formed on the top portion of the substantially single crystal layer during thermal oxidation can be stripped using HF acid etching. The etching selectivity of HF acid to silicon oxide and silicon (SiO ₂ : Si) can be adjusted by adjusting the temperature and concentration of the HF solution and the stoichiometry and density of the silicon oxide. Etching selectivity refers to the etch rate of one material relative to another. The selectivity of the HF solution for (SiO ₂ : Si) may be in the range of about 10: 1 to about 100: 1. High etch selectivity can reduce surface roughness by a factor similar to the initial surface roughness. However, the surface roughness of the resulting substantially single crystal layer 122 may still be greater than desired. For example, the surface of bulk Si (111) may have a root mean square (RMS) surface roughness of less than 0.1 nm, as measured by a 2 μm × 2 μm atomic force microscope (AFM) scan before additional processing. In some embodiments, the surface roughness required for epitaxially growing a gallium nitride material on Si (111) may be, for example, less than 1 nm, less than 0.5 nm, or less than 0.2 over an AFM scanning area of 30 μm × 30 μm. nm.

If the surface roughness of the substantially single crystal layer 122 after the thermal oxidation and the oxide layer peeling exceeds the required surface roughness, another surface smoothing may be performed. There are several ways to smooth the surface of silicon. These methods may include hydrogen annealing, laser trimming, plasma smoothing, and contact polishing (such as chemical mechanical polishing or CMP). These methods may involve preferentially eroding surface peaks with high aspect ratios. As a result, high aspect ratio features on the surface can be removed faster than low aspect ratio features, resulting in a smoother surface.

It should be understood that the specific steps illustrated in FIG. 5 provide a specific method for manufacturing an engineering substrate according to an embodiment of the present invention. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments of the invention may perform the steps described above in a different order. In addition, each step illustrated in FIG. 5 may include a plurality of sub-steps that can be performed in various orders suitable for a single step. In addition, additional steps can be added or removed depending on the application. Those skilled in the art will recognize many variations, modifications, and alternatives.

FIG. 6 is a simplified schematic diagram illustrating an epitaxial / engineering substrate structure for RF and power applications according to an embodiment of the present invention. In some LED applications, the engineering substrate structure provides a growth substrate capable of growing a high-quality GaN layer, and the engineering substrate structure is subsequently removed. However, for the application of RF and power components, the engineering substrate structure forms part of the completed component, and as a result, the engineering substrate structure or the electrical, thermal, and other characteristics of the components of the engineering substrate structure are important for a particular application.

Referring to FIG. 1, the single crystal silicon layer 122 is generally a release layer separated from a silicon donor wafer by using a implantation and lift-off technique. Typical cloth plants are hydrogen and boron. For power and RF component applications, the electrical properties of the layers and materials in the engineering substrate structure are important. For example, some device architectures use highly insulating silicon layers with a resistance greater than 10 ³ Ohm-cm to reduce or eliminate leakage through the substrate and interface layers. Other applications utilize designs that include a conductive silicon layer with a predetermined thickness (eg, 1 μm) to connect the source of a component to other components. Therefore, in these applications, it is desirable to control the size and performance of the single crystal silicon layer. In designs where implanting and stripping techniques are used during layer transfer, residual implanted atoms (such as hydrogen or boron) are present in the silicon layer, altering electrical characteristics. In addition, it may be difficult to control the thickness, conductivity, and other characteristics of the thin silicon layer using, for example, the adjustment of the implantation dose. The adjustment of the implantation dose will affect the conductivity and the FWHM and rough surface of the plant And the accuracy of the position of the split plane, and the depth of the implant that may affect the thickness of the layer.

According to the embodiment of the present invention, a silicon epitaxial crystal on an engineering substrate structure is used to realize a desired characteristic of a single crystal silicon layer suitable for a specific element design.

Referring to FIG. 6, the epitaxial / engineering substrate structure 600 includes an engineering substrate structure 610 and a silicon epitaxial layer 620 formed on the engineering substrate structure 610. The engineering substrate structure 610 may be similar to the engineering substrate structure illustrated in FIG. 1, FIG. 3, and FIG. 4. Generally, after the layer transfer, the substantially single crystal silicon layer 122 is on the order of 0.5 μm. In some processes, a surface conditioning process may be used to reduce the thickness of the single crystal silicon layer 122 to about 0.3 μm. In order to increase the thickness of the single crystal silicon layer to about 1 μm for manufacturing, for example, a reliable ohmic contact, an epitaxial single crystal silicon layer 620 is grown on a substantially single crystal silicon layer 122 formed by a layer transfer process using an epitaxial process. Various epitaxial growth processes can be used to grow the epitaxial single crystal silicon layer 620, including CVD, ALD, MBE, and the like. The thickness of the epitaxial single crystal silicon layer 620 may be in a range of about 0.1 μm to about 20 μm, for example, between 0.1 μm and 10 μm.

FIG. 7 is a simplified schematic diagram illustrating an III-V epitaxial layer on an engineering substrate structure according to an embodiment of the present invention. As described below, the structure illustrated in FIG. 7 may be referred to as a double epitaxial structure. As illustrated in FIG. 7, the engineering substrate structure 710 including the epitaxial single crystal silicon layer 620 has a III-V epitaxial layer 720 formed thereon. In one embodiment, the III-V epitaxial layer includes gallium nitride (GaN).

Depending on the desired function, the desired thickness of the III-V epitaxial layer 720 may vary widely. In some embodiments, the thickness of the III-V epitaxial layer 720 may vary between 0.5 μm and 100 μm, for example, the thickness is greater than 5 μm. The resulting breakdown voltage of a device fabricated on the III-V epitaxial layer 720 may vary depending on the thickness of the III-V epitaxial layer 720. Some embodiments provide breakdown voltages of at least 100 V, 300 V, 600 V, 1.2 kV, 1.7 kV, 3.3 kV, 5.5 kV, 13 kV, or 20 kV.

In order to provide conductivity between certain portions of the III-V epitaxial layer 720, which may include multiple sublayers, an epitaxial single crystal silicon layer 620 is formed from the top surface of the III-V epitaxial layer 720 in this example. A set of through holes 724. The through hole 724 may be lined with an insulating layer (not shown), so that the through hole 724 is insulated from the III-V epitaxial layer 720. As an example, these vias can be used by providing ohmic contacts through the vias to connect the electrodes of the diode or transistor to the underlying silicon layer, thereby mitigating the charge buildup in the element.

If a III-V epitaxial layer is grown on the single crystal silicon layer 122, it would be difficult to obtain such ohmic contacts through the vias, as it would be difficult to stop via etching in the single crystal silicon layer 122: for example Ground etched 5 μm GaN across the entire wafer and terminated the etch in a 0.3 μm silicon layer. The embodiments of the present invention can provide a single-crystal silicon layer with a thickness of a few micrometers, which is difficult under the use of the implantation and stripping process, because achieving a large implantation depth requires high implantation energy. Next, the thick silicon layer enables applications such as the illustrated vias that enable a wide variety of component designs.

In addition to increasing the thickness of the silicon "layer" by epitaxially growing the single crystal silicon layer 620 on the single crystal silicon layer 122, other adjustments to the original characteristics of the single crystal silicon layer 122, including conductivity and crystallinity Modifications. For example, if a silicon layer on the order of 10 μm is needed before the III-V layer or other materials are epitaxially grown, such a thick layer may be grown according to an embodiment of the present invention.

Because the implantation process will affect the properties of the single crystal silicon layer 122, for example, the residual boron / hydrogen atoms will affect the electrical properties of the silicon, the embodiment of the present invention removes a part of the single crystal before epitaxial growth of the single crystal silicon layer 620. Silicon layer 122. For example, the single crystal silicon layer 122 may be thinned to form a layer having a thickness of 0.1 μm or less, thereby removing most or all of the residual boron / hydrogen atoms. The subsequently grown single crystal silicon layer 620 is then used to provide a single crystal material having electrical and / or other properties substantially independent of the corresponding properties of the layers formed using the layer transfer process.

In addition to increasing the thickness of the single crystal silicon material coupled to the engineering substrate structure, the electrical properties (including conductivity) of the epitaxial single crystal silicon layer 620 may be different from the electrical properties of the single crystal silicon layer 122. The doped epitaxial single crystal silicon layer 620 during growth may generate p-type silicon by using boron doping and n-type silicon by using phosphorus doping. Undoped silicon can be grown to provide high-resistivity silicon for use in devices with insulating regions. In particular, an insulating layer can be used for the RF element.

The lattice constant of the epitaxial single crystal silicon layer 620 may be adjusted during growth to change the lattice constant of the single crystal silicon layer 122 to generate a strained epitaxial material. In addition to silicon, other elements can be epitaxially grown to provide layers, including strained layers or the like containing silicon germanium. For example, a buffer layer may be grown on the single crystal silicon layer 122, on the epitaxial single crystal silicon layer 620, or between layers to enhance subsequent epitaxial growth. Such buffer layers may include strained III-V layers, silicon germanium strained layers, and the like. In addition, the buffer layer and other epitaxial layers can be classified by Mohr fraction, dopant, polarity, and the like. Those skilled in the art will recognize many variations, modifications, and alternatives.

In some embodiments, the strain existing in the single crystal silicon layer 122 or the epitaxial single crystal silicon layer 620 may be relaxed during the growth of subsequent epitaxial layers (including the III-V epitaxial layer).

FIG. 8 is a simplified flowchart illustrating a method for manufacturing an engineering substrate according to another embodiment of the present invention. The method includes forming a support structure by providing a polycrystalline ceramic core (810) and forming a first adhesive layer (812) coupled to at least a portion of the polycrystalline ceramic core. The first adhesive layer may include a tetraethyl orthosilicate (TEOS) layer. The method further includes forming a conductive layer (814) coupled to the first adhesive layer. The conductive layer may be a polycrystalline silicon layer. The first adhesive layer may be formed as a single layer of TEOS. The conductive layer may be formed as a single layer of polycrystalline silicon.

The method further includes forming a second adhesive layer (816) coupled to at least a portion of the conductive layer, and forming a barrier shell (818). The second adhesive layer may be formed as a single layer of TEOS. The barrier shell may be formed as a single layer of silicon nitride or a series of sub-layers that form the barrier shell.

Once the support structure is formed by processes 810-818, the method further includes bonding a bonding layer (such as a silicon oxide layer) to the support structure (820) and bonding a substantially single crystal silicon layer or a substantially single crystal layer to the silicon oxide layer ( 822). The bonding of the bonding layer may include depositing a bonding material as described herein, followed by a planarization process.

A layer transfer process may be used to bond the substantially single crystal silicon layer 122 to the bonding layer 120. In some embodiments, a silicon wafer (eg, a silicon (111) wafer) is implanted to form a split surface. After the wafers are bonded, the silicon substrate can be removed together with the portion of the single crystal silicon layer below the split plane, so as to produce the peeled single crystal silicon layer 122 shown in FIG. 1. The thickness of the substantially single crystal silicon layer 122 can be changed to meet the specifications of various applications. In addition, the crystal direction of the substantially single crystal layer 122 can be changed to meet application specifications. In addition, the doping level and distribution in the substantially single crystal layer 122 can be changed to meet the specifications of a particular application. In some embodiments, the substantially single crystal silicon layer 122 may be smoothed, as described above.

The method illustrated in FIG. 8 may further include forming an epitaxial silicon layer by epitaxial growth on the substantially single crystal silicon layer (824), and forming an epitaxial growth by epitaxial growth on the epitaxial silicon layer. III-V layer (826). In some embodiments, the epitaxial III-V layer may include gallium nitride (GaN).

It should be understood that the specific steps illustrated in FIG. 8 provide a specific method for manufacturing an engineering substrate according to another embodiment of the present invention. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments of the invention may perform the steps described above in a different order. Further, each step illustrated in FIG. 8 may include a plurality of sub-steps that can be performed in various orders suitable for a single step. In addition, additional steps can be added or removed depending on the specific application. Those skilled in the art will recognize many variations, modifications, and alternatives.

It should also be understood that the examples and embodiments described herein are for illustration purposes only, and various modifications or changes will be conceivable by those with ordinary knowledge in the technical field in view of these examples and embodiments, and It is to be included within the spirit and scope of this application and the scope of the appended patent applications.

100‧‧‧Engineering substrate
110‧‧‧core
112‧‧‧first adhesive layer
114‧‧‧ conductive layer
116‧‧‧Second adhesive layer
118‧‧‧ barrier layer
120‧‧‧Combination layer
122‧‧‧Substantial monocrystalline silicon layer
130‧‧‧Epicrystalline material
300‧‧‧Engineering substrate
314‧‧‧ conductive layer
316‧‧‧Second adhesive layer
317‧‧‧plane
412‧‧‧first adhesive layer
414‧‧‧ conductive layer
416‧‧‧Second adhesive layer
418‧‧‧Barrier layer
500‧‧‧method
600‧‧‧Epimorph / Engineering Substrate Structure
610‧‧‧Engineering substrate structure
620‧‧‧ Silicon epitaxial layer
710‧‧‧Engineering substrate structure
720‧‧‧III-V epitaxial layer
724‧‧‧through hole

FIG. 1 is a simplified diagram illustrating a structure of an engineering substrate according to an embodiment of the present invention.

FIG. 2A is a SIMS curve illustrating the species concentration as a function of depth of an engineering structure according to an embodiment of the present invention.

FIG. 2B is a SIMS curve illustrating that the species concentration of an engineering structure after annealing is a function of depth according to an embodiment of the present invention.

FIG. 2C is a SIMS curve illustrating an engineering structure having a silicon nitride layer as a function of depth after annealing according to an embodiment of the present invention.

FIG. 3 is a simplified schematic diagram illustrating a structure of an engineering substrate according to another embodiment of the present invention.

FIG. 4 is a simplified diagram illustrating a structure of an engineering substrate according to yet another embodiment of the present invention.

FIG. 5 is a simplified flowchart illustrating a method for manufacturing an engineering substrate according to an embodiment of the present invention.

FIG. 6 is a simplified schematic diagram illustrating an epitaxial / engineering substrate structure for RF and power applications according to an embodiment of the present invention.

FIG. 7 is a simplified schematic diagram illustrating an III-V epitaxial layer on an engineering substrate structure according to an embodiment of the present invention.

FIG. 8 is a simplified flowchart illustrating a method for manufacturing an engineering substrate according to another embodiment of the present invention.

Domestic hosting information (please note in order of hosting institution, date, and number) None

Information on foreign deposits (please note in order of deposit country, institution, date, and number) None

100‧‧‧Engineering substrate

110‧‧‧core

112‧‧‧first adhesive layer

114‧‧‧ conductive layer

116‧‧‧Second adhesive layer

118‧‧‧ barrier layer

120‧‧‧Combination layer

122‧‧‧Substantial monocrystalline silicon layer

130‧‧‧Epicrystalline material

Claims (40)

A substrate includes: a support structure including: a polycrystalline ceramic core; a first adhesive layer coupled to the polycrystalline ceramic core; a conductive layer coupled to the first adhesive layer; and a second adhesive layer Is coupled to the conductive layer; and a barrier layer is coupled to the second adhesive layer; a silicon oxide layer is coupled to the support structure; a substantially single crystal silicon layer is coupled to the silicon oxide layer; An epitaxial III-V layer is coupled to the substantially single crystal silicon layer. The substrate according to claim 1, wherein the polycrystalline ceramic core comprises aluminum nitride. The substrate according to claim 2, wherein the epitaxial III-V layer comprises an epitaxial gallium nitride layer. The substrate according to claim 3, wherein the epitaxial gallium nitride layer has a thickness of about 5 μm or more. The substrate according to claim 1, wherein the substantially single crystal silicon layer includes a peeled silicon layer having a thickness of about 0.5 μm. The substrate according to claim 1, wherein the substantially single crystal silicon layer includes a stripped silicon layer and an epitaxial silicon layer grown on the stripped silicon layer, and the substantially single crystal silicon layer has a thickness of about 0.5 μm . The substrate according to claim 2, wherein: the first adhesive layer includes a first tetraethyl orthosilicate (TEOS) layer encapsulating the polycrystalline ceramic core; the conductive layer includes encapsulating the first TEOS oxide A polycrystalline silicon layer of the physical layer; the second adhesive layer includes a second TEOS layer encapsulating the polycrystalline silicon layer; and the barrier layer includes a silicon nitride layer encapsulating the second TEOS layer. The substrate according to claim 7, wherein: the first TEOS layer has a thickness of about 1000 Å; the polycrystalline silicon layer has a thickness of about 3000 Å; the second TEOS layer has a thickness of about 1000 Å; and the The silicon nitride layer has a thickness of about 4000 Å. A method for manufacturing a substrate includes the following steps: forming a supporting structure by the following steps: providing a polycrystalline ceramic core; encapsulating the polycrystalline ceramic core in a first bonding shell; and bonding the first bonding Encapsulating a shell in a conductive shell; Encapsulating the conductive shell in a second adhesive shell; Encapsulating the second adhesive shell in a barrier shell; Bonding a bonding layer to the support structure; A substantially single crystal silicon layer is bonded to the bonding layer; an epitaxial silicon layer is formed by epitaxial growth on the substantially single crystal silicon layer; and an epitaxial layer is formed by epitaxial growth on the epitaxial silicon layer. Crystal III-V layer. The method according to claim 9, further comprising forming a plurality of through holes passing from the epitaxial III-V layer to the epitaxial silicon layer. The method of claim 9, wherein the epitaxial III-V layer comprises gallium nitride. The method according to claim 9, wherein: the first adhesive shell comprises a tetraethyl orthosilicate (TEOS) shell; the conductive shell comprises a polycrystalline silicon shell; the second adhesive shell comprises a second TEOS shell; The barrier material includes a silicon nitride shell; and the bonding layer includes silicon oxide. The method according to claim 12, wherein: the first TEOS shell comprises a single TEOS layer; the polycrystalline silicon layer comprises a polycrystalline silicon single layer; the second TEOS oxide shell comprises a TEOS single layer; and the silicon nitride shell Contains a single layer of silicon nitride. An engineering substrate structure includes: a support structure including: a polycrystalline ceramic core; a first adhesive layer coupled to the polycrystalline ceramic core; a conductive layer coupled to the first adhesive layer; a second An adhesive layer is coupled to the conductive layer; and a barrier shell is coupled to the second adhesive layer; a bonding layer is coupled to the support structure; a substantially monocrystalline silicon layer is coupled to the bonding layer; And an epitaxial single crystal silicon layer, which is coupled to the substantially single crystal silicon layer. The engineering substrate structure according to claim 14, wherein: the polycrystalline ceramic core comprises polycrystalline gallium nitride; the first adhesive layer comprises tetraethyl orthosilicate (TEOS); the conductive layer comprises polycrystalline silicon; the second The adhesive layer includes TEOS; the barrier shell includes silicon nitride; and the bonding layer includes silicon oxide. The engineering substrate structure according to claim 14, further comprising an epitaxial III-V layer coupled to the epitaxial single crystal silicon layer. The engineering substrate structure according to claim 16, further comprising a plurality of through holes passing from the epitaxial III-V layer to the epitaxial single crystal silicon layer. The engineering substrate structure according to claim 14, further comprising one or more buffer layers between the substantially single crystal silicon layer and the epitaxial single crystal silicon layer. The engineering substrate structure according to claim 14, wherein the epitaxial single crystal silicon layer has a strain. The engineering substrate structure according to claim 14, wherein the epitaxial single crystal silicon layer is characterized by a thickness in a range of 1 μm to 20 μm. A substrate includes: a polycrystalline ceramic core; a first adhesive layer encapsulating the polycrystalline ceramic core; a conductive layer encapsulating the first adhesive layer; a second adhesive layer encapsulating the conductive layer; a A barrier layer encapsulates the second adhesive layer; a bonding layer is coupled to the barrier layer; and a substantially single crystal silicon layer is coupled to the bonding layer. The substrate according to claim 21, wherein the polycrystalline ceramic core comprises polycrystalline aluminum nitride. The substrate according to claim 21, wherein the first adhesive layer comprises tetraethyl orthosilicate (TEOS). The substrate according to claim 21, wherein the first adhesive layer has a thickness of about 1000 Å. The substrate according to claim 21, wherein the conductive layer comprises polycrystalline silicon. The substrate according to claim 21, wherein the conductive layer has a thickness of about 3000 Å. The substrate according to claim 21, wherein the second adhesive layer comprises tetraethyl orthosilicate (TEOS). The substrate according to claim 21, wherein the second adhesive layer has a thickness of about 1000 Å. The substrate according to claim 21, wherein the barrier layer comprises silicon nitride. The substrate according to claim 21, wherein the barrier layer has a thickness of about 4000 Å. The substrate according to claim 21, wherein the substantially single-crystal silicon layer comprises a stripped silicon layer. The substrate according to claim 21, wherein the substantially single crystal silicon layer has a thickness of about 0.5 μm. A method for manufacturing a substrate includes the following steps: providing a polycrystalline ceramic core; encapsulating the polycrystalline ceramic core in a first adhesive shell; encapsulating the first adhesive shell in a conductive shell; Encapsulating the conductive shell in a second adhesive shell; encapsulating the second adhesive shell in a barrier shell; bonding a bonding layer to the barrier shell; and bonding a single crystal silicon layer to the Bonding layer. The method of claim 33, wherein the polycrystalline ceramic core comprises polycrystalline aluminum nitride. The method according to claim 33, wherein the first adhesive shell comprises tetraethyl orthosilicate (TEOS). The method of claim 33, wherein the conductive shell comprises polycrystalline silicon. The method of claim 33, wherein the second adhesive shell comprises tetraethyl orthosilicate (TEOS). The method of claim 33, wherein the barrier shell comprises silicon nitride. The method of claim 33, wherein combining the single crystal silicon layer includes performing a layer transfer process from a silicon wafer on insulator. The method of claim 39, further comprising smoothing the substantially single crystal silicon layer.