TWI839076B - Engineered substrate structure for power and rf applications - Google Patents

Abstract

A substrate includes a support structure comprising: a polycrystalline ceramic core; a first adhesion layer coupled to the polycrystalline ceramic core; a conductive layer coupled to the first adhesion layer; a second adhesion layer coupled to the conductive layer; and a barrier layer coupled to the second adhesion layer. The substrate also includes a silicon oxide layer coupled to the support structure, a substantially single crystalline silicon layer coupled to the silicon oxide layer, and an epitaxial III-V layer coupled to the substantially single crystalline silicon layer.

Description

Engineered substrate structures for power and RF applications

This patent application claims priority to U.S. Provisional Patent Application No. 62/350,084 filed on June 14, 2016, entitled "ENGINEERED SUBSTRATE STRUCTURE FOR POWER AND RF APPLICATIONS" and U.S. Provisional Patent Application No. 62/350,077 filed on June 14, 2016, entitled "ENGINEERED SUBSTRATE STRUCTURE AND METHOD OF MANUFACTURE", the disclosures of which are hereby incorporated by reference in their entirety for all purposes.

The present invention generally relates to engineered substrate structures. More specifically, the present invention relates to methods and systems suitable for use in epitaxial growth processes.

The structure of a light-emitting diode (LED) is usually epitaxially grown on a sapphire substrate. There are many products that use LED components, including lighting, computer monitors and other display devices.

Growing a GaN series LED structure on a sapphire substrate is a heterogeneous epitaxial growth process because the substrate and epitaxial layer are composed of different materials. Due to the heterogeneous epitaxial growth process, the epitaxially grown material will exhibit various adverse effects, including reduced uniformity and reduced metrics related to the electronic/optical properties of the epitaxial layer. Therefore, there is a need in the art for improved methods and systems related to epitaxial growth processes and substrate structures.

The present invention generally relates to engineered substrate structures. More specifically, the present invention relates to methods and systems suitable for use in epitaxial growth processes. By way of example only, the present invention has been applied to methods and systems for providing a substrate structure suitable for epitaxial growth, the substrate structure being characterized by a coefficient of thermal expansion (CTE) that is substantially matched to an epitaxial layer grown thereon. Such methods and techniques may be applied to a wide variety of semiconductor processing operations.

According to one embodiment of the present invention, a substrate is provided. The substrate includes a support structure, which includes: a polycrystalline ceramic core; a first adhesive layer coupled to the polycrystalline ceramic core; a conductive layer coupled to the first adhesive layer; a second adhesive layer coupled to the conductive layer; and a barrier layer coupled to the second adhesive layer. The substrate also includes a silicon oxide layer coupled to the support structure, a substantially single crystal silicon layer coupled to the silicon oxide layer, and an epitaxial III-V layer coupled to the substantially single crystal silicon layer.

According to another embodiment of the present invention, a method for manufacturing a substrate is provided. The method includes forming a support structure by the following steps: providing a polycrystalline ceramic core; encapsulating the polycrystalline ceramic core in a first bonding shell; encapsulating the first bonding shell in a conductive shell; encapsulating the conductive shell in a second bonding shell; and encapsulating the second bonding shell in a barrier shell. The method also includes bonding a bonding layer to the support structure, bonding a substantially single crystal silicon layer to the bonding layer, forming an epitaxial silicon layer by epitaxial growth on the substantially single crystal silicon layer, and forming an epitaxial III-V layer by epitaxial growth on the epitaxial silicon layer.

According to a specific embodiment of the present invention, an engineering substrate structure is provided. The engineering substrate structure includes a support structure, a bonding layer coupled to the support structure, a substantial single crystal silicon layer coupled to the bonding layer, and an epitaxial single crystal silicon layer coupled to the substantial single crystal silicon layer. The support structure includes a polycrystalline ceramic core, a first bonding layer coupled to the polycrystalline ceramic core, a conductive layer coupled to the first bonding layer, a second bonding layer coupled to the conductive layer, and a barrier shell coupled to the second bonding layer.

Numerous benefits over conventional techniques are realized through the present invention. For example, embodiments of the present invention provide an engineered substrate structure having a CTE matched to a gallium nitride series epitaxial layer suitable for optical, electronic, and optoelectronic applications. The encapsulation layer that is a component of the engineered substrate structure prevents impurities present in the central portion of the substrate from diffusing into the semiconductor processing environment in which the engineered substrate is used. Key properties associated with the substrate material, including coefficient of thermal expansion, lattice mismatch, thermal stability, and shape control are independently designed to improve (e.g., optimize) matching with gallium nitride series epitaxial and device layers, as well as matching with different device architectures and performance targets. Because the substrate material layers are integrated together in a conventional semiconductor manufacturing process, process integration is simplified. These and other embodiments of the present invention and their many advantages and features are described in more detail below and in conjunction with the accompanying drawings.

100: Engineering substrate

110: Core

112: First adhesive layer

114: Conductive layer

116: Second adhesive layer

118: Barrier layer

120: Binding layer

122: Substantial single crystal silicon layer

130: Epitaxial materials

300: Engineering substrate

314: Conductive layer

316: Second adhesive layer

317: Plane

412: First adhesive layer

414: Conductive layer

416: Second adhesive layer

418: Barrier layer

500:Methods

600: Epitaxial/engineering substrate structure

610: Engineering substrate structure

620: Silicon epitaxial layer

710: Engineering substrate structure

720: III-V epitaxial layer

724:Through hole

Figure 1 is a simplified schematic diagram showing the structure of an engineering substrate according to one embodiment of the present invention.

Figure 2A is a SIMS curve showing the species concentration as a function of depth of an engineering structure according to one embodiment of the present invention.

Figure 2B is a SIMS curve showing the species concentration as a function of depth of an engineering structure after annealing according to one embodiment of the present invention.

FIG. 2C is a SIMS curve showing the species concentration as a function of depth of an engineering structure having a silicon nitride layer after annealing according to one embodiment of the present invention.

Figure 3 is a simplified schematic diagram of an engineering substrate structure according to another embodiment of the present invention.

Figure 4 is a simplified schematic diagram showing the structure of an engineering substrate according to another embodiment of the present invention.

Figure 5 is a simplified flow chart illustrating a method for manufacturing an engineering substrate according to one embodiment of the present invention.

Figure 6 is a simplified schematic diagram of an epitaxial/engineered substrate structure for RF and power applications according to one embodiment of the present invention.

FIG. 7 is a simplified schematic diagram showing a III-V epitaxial layer on an engineering substrate structure according to one embodiment of the present invention.

Figure 8 is a simplified flow chart illustrating a method for manufacturing an engineering substrate according to another embodiment of the present invention.

Embodiments of the present invention relate to engineered substrate structures. More specifically, the present invention relates to methods and systems suitable for use in epitaxial growth processes. By way of example only, the present invention has been applied to methods and systems for providing a substrate structure suitable for epitaxial growth, the substrate structure being characterized by a coefficient of thermal expansion (CTE) that is substantially matched to the epitaxial layer grown thereon. Such methods and techniques may be applied to a wide variety of semiconductor processing operations.

FIG. 1 is a simplified schematic diagram illustrating an engineering substrate structure according to one embodiment of the present invention. The engineering substrate 100 illustrated in FIG. 1 is suitable for use in a wide variety of electronic and optical applications. The engineering substrate includes a core 110 that may have a coefficient of thermal expansion (CTE) that substantially matches the CTE of an epitaxial material to be grown on the engineering substrate 100. The epitaxial material 130 is illustrated as optional because the epitaxial material 130 is not required as a component of the engineering substrate, but the epitaxial material 130 will typically be grown on the engineering substrate.

For applications involving the growth of gallium nitride (GaN) family materials (including epitaxial layers of GaN family layers), core 110 may be a polycrystalline ceramic material, such as polycrystalline aluminum nitride (AlN), which may include bonding materials such as yttrium oxide. Other materials may be used for core 110, including polycrystalline gallium nitride (GaN), polycrystalline gallium aluminum nitride (AlGaN), polycrystalline silicon carbide (SiC), polycrystalline zinc oxide (ZnO), polycrystalline gallium trioxide (Ga ₂ O ₃ ), and the like.

The thickness of the core can be in the order of 100 μm to 1,500 μm, for example 725 μm. The core 110 is encapsulated in a first bonding layer 112, which can be referred to as a shell or an encapsulation shell. In one embodiment, the first bonding layer 112 includes a tetraethyl orthosilicate (TEOS) layer having a thickness on the order of 1,000 Å. In other embodiments, the thickness of the first bonding layer varies, for example, from 100 Å to 2,000 Å. Although TEOS is used for the bonding layer in some embodiments, according to one embodiment of the present invention, other materials can be used to provide bonding between subsequently deposited layers and underlying layers or materials (such as ceramics, particularly polycrystalline ceramics). For example, _SiO2 or other silicon oxides (Si _x O _y ) adhere well to ceramic materials and provide a suitable surface for subsequent deposition (e.g., conductive materials). In some embodiments, the first bonding layer 112 completely surrounds the core 110 to form a fully encapsulated core, and the first bonding layer 112 can be formed using an LPCVD process. The first bonding layer 112 provides a surface to which subsequent layers adhere to form elements of the engineered substrate structure.

In addition to using an LPCVD process, a furnace-based process, etc. to form the encapsulated first adhesive layer, other semiconductor processes, including CVD processes or similar deposition processes, may be used in accordance with embodiments of the present invention. As an example, a deposition process may be used to coat a portion of the core, the core may be turned over, and the deposition process may be repeated to coat other portions of the core. Thus, while LPCVD technology is used in some embodiments to provide a fully encapsulated structure, other film formation techniques may be used depending on the specific application.

A conductive layer 114 is formed surrounding the first adhesive layer 112. In one embodiment, the conductive layer 114 is a polysilicon (i.e., multicrystalline silicon) shell formed around the first adhesive layer 112, because polysilicon can exhibit poor adhesion to ceramic materials. In embodiments where the conductive layer is polysilicon, the thickness of the polysilicon layer can be on the order of 500-5,000 Å, such as 2,500 Å. In some embodiments, the polysilicon layer can be formed as a shell that completely surrounds the first adhesive layer 112 (e.g., TEOS layer), thereby forming a completely encapsulated first adhesive layer, and can be formed using an LPCVD process. In other embodiments, as discussed below, the conductive material can be formed on a portion of the adhesive layer, such as on the lower half of the substrate structure. In some embodiments, the conductive material may be formed as a fully encapsulating layer and the conductive material on one side of the substrate structure may be subsequently removed.

In one embodiment, the conductive layer 114 may be a polysilicon layer doped to provide a highly conductive material, such as boron doped to provide a p-type polysilicon layer. In some embodiments, the boron doping is at a content of 1×10 ¹⁹ cm ^-3 to 1×10 ²⁰ cm ^-3 to provide high conductivity. Other dopants (e.g., phosphorus, arsenic, bismuth, etc. with a dopant concentration ranging from 1×10 ¹⁶ cm ^-3 to 5×10 ¹⁸ cm ^-3 ) may be used to provide n-type or p-type semiconductor materials suitable for the conductive layer. Those skilled in the art will recognize many variations, modifications, and substitutions.

The presence of the conductive layer 114 is useful during electrostatic clamping of an engineered substrate in a semiconductor processing tool, such as a tool having an electrostatic chuck (ESC). After processing in the semiconductor processing tool, the conductive layer 114 can be quickly unclamped. Thus, embodiments of the present invention provide a substrate structure that can be processed in the same manner as conventional silicon wafers. Those skilled in the art will recognize numerous variations, modifications, and substitutions.

A second adhesive layer 116 (e.g., a TEOS layer having a thickness on the order of 1000Å) is formed surrounding the conductive layer 114. In some embodiments, the second adhesive layer 116 completely surrounds the conductive layer 114 to form a fully encapsulated structure, and can be formed using an LPCVD process, a CVD process, or any other suitable deposition process, including the deposition of a spin-on dielectric.

A barrier layer 118, such as a silicon nitride layer, is formed to surround the second adhesion layer 116. In one embodiment, the barrier layer 118 is a silicon nitride layer 118 having a thickness on the order of 2,000 Å to 5,000 Å. In some embodiments, the barrier layer 118 completely surrounds the second adhesion layer 116 to form a completely encapsulated structure, and may be formed using an LPCVD process. In addition to the silicon nitride layer, an amorphous material (including SiCN, SiON, AlN, SiC, etc.) may be used as the barrier layer. In some embodiments, the barrier layer 118 includes a plurality of sub-layers built to form the barrier layer. Therefore, the term barrier layer is not intended to represent a single layer or a single material, but rather encompasses one or more materials layered in a composite manner. Those skilled in the art will recognize many variations, modifications, and substitutions.

In some embodiments, barrier layer 118 (e.g., silicon nitride layer) prevents elements present in core 110 (e.g., yttrium oxide (i.e., yttrium oxide), oxygen, metal impurities, other trace elements, etc.) from diffusing and/or outgassing into the environment of a semiconductor processing chamber where an engineered substrate may be present, such as during a high temperature (e.g., 1,000°C) epitaxial growth process. With the encapsulation layer described herein, ceramic materials, including polycrystalline AlN designed for non-cleanroom environments, may be used in semiconductor process flows and cleanroom environments.

FIG. 2A is a secondary ion mass spectroscopy (SIMS) curve illustrating species concentration as a function of depth for an engineered structure according to one embodiment of the present invention. The engineered structure does not include barrier layer 118. Referring to FIG. 2A, several species present in the ceramic core (e.g., yttrium, calcium, and aluminum) are reduced to negligible concentrations in the engineered layers 120/122. The concentrations of calcium, yttrium, and aluminum are reduced by three, four, and six orders of magnitude, respectively.

FIG. 2B is a SIMS curve illustrating species concentration as a function of depth for an engineered structure without a barrier layer after annealing according to one embodiment of the present invention. As discussed above, during semiconductor processing operations, such as during epitaxial growth of GaN series layers, the engineered substrate structure provided by embodiments of the present invention may be exposed to high temperatures (~1,100°C) for several hours.

For the curves shown in Figure 2B, the engineered substrate structure was annealed at 1,100°C for 4 hours. As shown in Figure 2B, the calcium, yttrium, and aluminum that were originally present at low concentrations in the as-deposited, untreated sample have diffused into the engineered layer to concentrations similar to those of the other elements.

FIG. 2C is a SIMS plot illustrating species concentration as a function of depth for an engineering structure having a barrier layer after annealing according to one embodiment of the present invention. Integrating a diffusion barrier layer 118 (e.g., a silicon nitride layer) into the engineering substrate structure prevents calcium, yttrium, and aluminum from diffusing into the engineering layer during the annealing process, which would occur if the diffusion barrier layer were not present. As illustrated in FIG. 2C, after annealing, calcium, yttrium, and aluminum present in the ceramic core remain at low concentrations in the engineering layer. Thus, the use of a barrier layer 118 (e.g., a silicon nitride layer) prevents these elements from diffusing through the diffusion barrier layer, thereby preventing these elements from being released into the environment surrounding the engineering substrate. Similarly, any other impurities contained in the bulk ceramic material will also be contained by the barrier layer.

Typically, the ceramic material used to form the core 110 is fired at a temperature in the range of 1800°C. It is expected that this process will drive off a significant amount of impurities present in the ceramic material. Such impurities may include yttrium, calcium, and other elements and compounds resulting from the use of yttrium oxide as a sintering agent. Subsequently, during the epitaxial growth process conducted at a much lower temperature in the range of 800°C to 1100°C, it is expected that subsequent diffusion of such impurities will not be significant. However, contrary to conventional expectations, the inventors have determined that significant diffusion of elements through the layers of the engineered substrate occurs even during the epitaxial growth process at temperatures much lower than the firing temperature of the ceramic material. Therefore, embodiments of the present invention integrate a barrier layer 118 (e.g., a silicon nitride layer) to prevent background elements from diffusing outward from the polycrystalline ceramic material (e.g., AlN) into the engineering layers 120/122 and epitaxial layers (e.g., the optional GaN layer 130). The silicon nitride layer 118 encapsulates the underlying layers and materials to provide the desired barrier layer function.

As shown in FIG. 2B , elements originally present in the core 110 (including yttrium) diffuse into and through the first TEOS layer 112 , the polysilicon layer 114 , and the second TEOS layer 116 . However, the presence of the silicon nitride layer 118 prevents these elements from diffusing through the silicon nitride layer, thereby preventing these elements from being released into the environment surrounding the engineered substrate, as shown in FIG. 2C .

Referring again to FIG. 1 , a bonding layer 120 (e.g., a silicon oxide layer) is deposited on a portion of the barrier layer 118 (e.g., the top surface of the barrier layer), and the bonding layer 120 is then used in the bonding process of the substantially single crystal silicon layer 122. In some embodiments, the thickness of the bonding layer 120 may be about 1.5 μm.

The substantially single crystal layer 122 is suitable for use as a growth layer during an epitaxial growth process to form an epitaxial material 130. In some embodiments, the epitaxial material 130 includes a GaN layer having a thickness of 2 μm to 10 μm, which can be used as one of a plurality of layers used in optoelectronic components, RF components, power components, etc. In one embodiment, the substantially single crystal layer 122 includes a substantially single crystal silicon layer attached to the silicon oxide layer 118 using a layer transfer process.

FIG. 3 is a simplified schematic diagram illustrating an engineering substrate structure according to one embodiment of the present invention. The engineering substrate 300 illustrated in FIG. 3 is suitable for use in a wide variety of electronic and optical applications. The engineering substrate includes a core 110 that can have a coefficient of thermal expansion (CTE) that substantially matches the CTE of an epitaxial material 130 to be grown on the engineering substrate 300. The epitaxial material 130 is illustrated as optional because the epitaxial material 130 is not required as a component of the engineering substrate, but the epitaxial material 130 will typically be grown on the engineering substrate.

For applications including the growth of gallium nitride (GaN) family materials (including epitaxial layers of GaN family layers), core 110 can be a polycrystalline ceramic material, such as polycrystalline aluminum nitride (AlN). The thickness of the core can be on the order of 100 μm to 1,500 μm, such as 725 μm. Core 110 is encapsulated in a first adhesive layer 112, which can be referred to as a shell or encapsulation shell. In this embodiment, first adhesive layer 112 completely encapsulates the core, but this is not required by the present invention, as discussed in further detail with respect to FIG. 4.

In one embodiment, the first adhesion layer 112 comprises a layer of tetraethylorthosilicate (TEOS) having a thickness on the order of 1,000 Å. In other embodiments, the thickness of the first adhesion layer varies, for example, from 100 Å to 2,000 Å. Although TEOS is used for the adhesion layer in some embodiments, other materials may be utilized to provide adhesion between subsequently deposited layers and underlying layers or materials in accordance with one embodiment of the present invention. For example, _SiO2 , SiON, and the like adhere well to ceramic materials and provide a suitable surface for subsequent deposition (e.g., conductive materials). In some embodiments, the first adhesion layer 112 completely surrounds the core 110 to form a fully encapsulated core, and the first adhesion layer 112 may be formed using an LPCVD process. The adhesive layer provides a surface to which subsequent layers are adhered to form components of the engineered substrate structure.

In addition to using an LPCVD process, a furnace-based process, etc. to form an encapsulated adhesive layer, other semiconductor processes may be used in accordance with embodiments of the present invention. As an example, a deposition process (e.g., CVD, PECVD, or similar process) may be used to coat a portion of the core, the core may be flipped, and the deposition process may be repeated to coat other portions of the core.

A conductive layer 314 is formed on at least a portion of the first adhesive layer 112. In one embodiment, the conductive layer 314 includes polysilicon (i.e., polycrystalline silicon) formed on the lower portion (e.g., lower half or back side) of the core/adhesion layer structure by a deposition process. In embodiments where the conductive layer is polysilicon, the thickness of the polysilicon layer can be on the order of several kiloangstroms, such as 3,000Å. In some embodiments, the polysilicon layer can be formed using an LPCVD process.

In one embodiment, the conductive layer 314 can be a polycrystalline silicon layer doped to provide a highly conductive material, for example, the conductive layer 314 can be doped with boron to provide a p-type polycrystalline silicon layer. In some embodiments, the doping with boron is in a range from about 1×10 ¹⁹ cm ^-3 to 1×10 ²⁰ cm ^-3 to provide high conductivity. The presence of the conductive layer is useful during electrostatic chucking of the engineered substrate in a semiconductor processing tool, such as a tool with an electrostatic chuck (ESC). The conductive layer 314 can be quickly unclamped after processing. Therefore, embodiments of the present invention provide a substrate structure that can be processed in the same manner as conventional silicon wafers. Those skilled in the art will recognize many variations, modifications and substitutions.

A second adhesive layer 316 (e.g., a second TEOS layer) is formed surrounding the conductive layer 314 (e.g., a polysilicon layer). The thickness of the second adhesive layer 316 is on the order of 1,000 Å. In some embodiments, the second adhesive layer 316 may completely surround the conductive layer 314 and the first adhesive layer 112 to form a fully encapsulated structure, and may be formed using an LPCVD process. In other embodiments, the second adhesive layer 316 only partially surrounds the conductive layer 314, such as terminating at a position illustrated by a plane 317, which may be aligned with the top surface of the conductive layer 314. In this example, the top surface of the conductive layer 314 will contact a portion of the barrier layer 118. Those skilled in the art will recognize many variations, modifications, and substitutions.

A barrier layer 118 (e.g., a silicon nitride layer) is formed surrounding the second adhesive layer 316. In some embodiments, the barrier layer 118 has a thickness on the order of 4,000Å to 5,000Å. In some embodiments, the barrier layer 118 completely surrounds the second adhesive layer 316 to form a fully encapsulated structure, and can be formed using an LPCVD process.

In some embodiments, a silicon nitride barrier layer is used to prevent elements present in the core 110 (e.g., yttrium oxide (i.e., yttrium oxide), oxygen, metal impurities, other trace elements, etc.) from diffusing and/or outgassing into the environment of a semiconductor processing chamber where an engineered substrate may be present, such as during a high temperature (e.g., 1,000°C) epitaxial growth process. With the encapsulation layer described herein, ceramic materials, including polycrystalline AlN designed for non-cleanroom environments, can be used in semiconductor process flows and cleanroom environments.

FIG. 4 is a simplified schematic diagram illustrating an engineering substrate structure according to another embodiment of the present invention. In the embodiment illustrated in FIG. 4, a first adhesive layer 412 is formed on at least a portion of the core 110, but does not encapsulate the core 110. In this embodiment, the first adhesive layer 412 is formed on the lower surface of the core 110 (the back side of the core 110) to enhance the adhesion of the subsequently formed conductive layer 414, as described more fully below. Although FIG. 4 only illustrates the adhesive layer 412 on the lower surface of the core 110, it will be understood that depositing the adhesive layer material on other portions of the core will not adversely affect the performance of the engineering substrate structure, and such material may be present in various embodiments. Those skilled in the art will recognize many variations, modifications and substitutions.

The conductive layer 414 does not encapsulate the first adhesive layer 412 and the core 110, but is generally aligned with the first adhesive layer 412. Although the conductive layer 414 is illustrated as extending along the bottom or back side of the first adhesive layer 412 and extending upward along a portion of the side of the first adhesive layer 412, it is not required by the present invention to extend along the vertical side. Therefore, embodiments can utilize deposition on one side of the substrate structure, masking of one side of the substrate structure, etc. The conductive layer 414 can be formed on a portion of one side (e.g., the bottom/back side) of the first adhesive layer 412. The conductive layer 414 provides electrical conduction on one side of the engineered substrate structure, which can be advantageous in RF and high power applications. The conductive layer may include doped polysilicon as discussed with respect to conductive layer 114 in FIG. 1 .

A portion of the core 110, portions of the first adhesive layer 412, and the conductive layer 414 are covered by a second adhesive layer 416 to enhance the adhesion of the barrier layer 418 to the underlying material. As discussed above, the barrier layer 418 forms an encapsulation structure to prevent diffusion from the underlying layers.

In addition to the semiconductor series conductive layer, in other embodiments, the conductive layer 414 is a metal layer, such as 500Å titanium or the like.

Referring again to FIG. 4, one or more layers may be removed, depending on the implementation. For example, layers 412 and 414 may be removed, leaving only a single bond shell 416 and barrier layer 418. In another embodiment, only layer 414 may be removed. In this embodiment, layer 412 may also balance stress and wafer bow caused by layer 120 deposited on top of layer 418. Construction of a substrate structure with an insulating layer on the top side of core 110 (e.g., only an insulating layer between core 110 and layer 120) would provide benefits for power/RF applications where a highly insulating substrate is required.

In another embodiment, barrier layer 418 may directly encapsulate core 110, followed by conductive layer 414 and then adhesive layer 416. In this embodiment, layer 120 may be deposited directly onto adhesive layer 416 from the top side. In yet another embodiment, adhesive layer 416 may be deposited onto core 110, followed by barrier layer 418, then conductive layer 414 and another adhesive layer 412.

Although some embodiments have been discussed with respect to layers, the term layer should be understood such that a layer may include several sub-layers constructed to form the layer of interest. Thus, the term layer is not intended to mean a single layer composed of a single material, but rather encompasses one or more materials layered in a composite manner to form a desired structure. Those skilled in the art will recognize many variations, modifications, and substitutions.

FIG. 5 is a simplified flow chart illustrating a method of manufacturing an engineered substrate according to an embodiment of the present invention. The method can be used to manufacture a substrate that is CTE matched to one or more epitaxial layers grown on the substrate. Method 500 includes forming a support structure by providing a polycrystalline ceramic core (510), encapsulating the polycrystalline ceramic core in a first adhesive layer to form a shell (e.g., a tetraethyl orthosilicate (TEOS) shell) (512), and encapsulating the first adhesive layer in a conductive shell (e.g., a polycrystalline silicon shell) (514). The first adhesive layer can be formed as a single layer of TEOS. The conductive shell can be formed as a single layer of polycrystalline silicon.

The method also includes encapsulating the conductive shell in a second adhesive layer (e.g., a second TEOS shell) (516), and encapsulating the second adhesive layer in a barrier layer shell (518). The second adhesive layer can be formed as a single layer of TEOS. The barrier layer shell can be formed as a single layer of silicon nitride.

Once the support structure is formed by processes 510-518, the method further includes bonding a bonding layer (e.g., a silicon oxide layer) to the support structure (520) and bonding a substantially single crystalline layer (e.g., a substantially single crystalline silicon layer) to the silicon oxide layer ( ₅₂₂ ). Other substantially single crystalline layers may be used according to embodiments of the present invention, including SiC, sapphire, GaN, AlN, SiGe, Ge, diamond, _Ga2O3 , ZnO, etc. Bonding of the bonding layer may include depositing a bonding material followed by a planarization process as described herein. In the embodiments described below, a substantially single crystalline layer (eg, a substantially single crystalline silicon layer) is connected to a bonding layer using a layer transfer process, wherein the substantially single crystalline layer is a single crystalline silicon layer transferred from a silicon wafer.

1, the bonding layer 120 may be formed by depositing a thick (e.g., 4 μm thick) oxide layer followed by a chemical mechanical polishing (CMP) process to thin the oxide to a thickness of about 1.5 μm. The thick initial oxide is used to fill voids and surface features present on the support structure that may exist after the polycrystalline core is fabricated and continue to exist when the encapsulation layer illustrated in FIG. 1 is formed. The CMP process provides a generally flat surface without voids, particles, or other features that may then be used to bond a substantially single crystal layer 122 (e.g., a substantially single crystal silicon layer) to the bonding layer 120 during a wafer transfer process. It will be appreciated that the bonding layer 120 need not be characterized by an atomically flat surface, but rather should provide a generally flat surface that will support bonding to a substantially single crystal layer (e.g., a substantially single crystal silicon layer) with the desired reliability.

A layer transfer process may be used to bond the substantially single crystal silicon layer 122 to the bonding layer 120. In some embodiments, a silicon wafer (e.g., a silicon (111) wafer) is implanted to form a cleavage plane. After the wafers are bonded, the silicon substrate may be removed along with the portion of the single crystal silicon layer below the cleavage plane, thereby producing the peeled single crystal silicon layer 122 illustrated in FIG. 1. The thickness of the substantially single crystal layer 122 may be varied to meet the specifications of various applications. In addition, the crystal orientation of the substantially single crystal layer 122 may be varied to meet the specifications of the application. In addition, the doping level and distribution in the substantially single crystal layer 122 may be varied to meet the specifications of a particular application.

The method illustrated in FIG. 5 may also include smoothing the substantial single crystal layer (524). In some embodiments, the thickness and surface roughness of the substantial single crystal layer 122 may be modified to obtain high quality epitaxial growth. Different device applications may have slightly different specifications regarding the thickness and surface smoothness of the substantial single crystal layer 122. The splitting process causes the substantial single crystal layer 122 to be layered from the bulk single crystal silicon wafer at the peak of the implanted ion distribution. After splitting, the substantial single crystal layer 122 may be adjusted or modified in several aspects and then used as a growth surface for epitaxial growth of other materials, such as gallium nitride.

First, the transferred substantial single crystal layer 122 may contain a small amount of residual hydrogen concentration and may have some crystalline damage from the planting. Therefore, it may be beneficial to remove the thin portion of the transferred substantial single crystal layer 122 where the lattice is damaged. In some embodiments, the depth of the planting can be adjusted to be greater than the desired final thickness of the substantial single crystal layer 122. The additional thickness allows the damaged thin portion of the transferred substantial single crystal layer to be removed, leaving an undamaged portion of the desired final thickness.

Second, it may be desirable to adjust the overall thickness of the substantially single crystal layer 122. Generally, it may be desirable to make the substantially single crystal layer 122 thick enough to provide a high quality lattice template for subsequently growing one or more epitaxial layers, but thin enough to be highly compliant. The substantially single crystal layer 122 may be referred to as "compliant" when it is relatively thin, such that the physical properties of the substantially single crystal layer 122 are less restricted and can mimic the physical properties of the surrounding material, and have a lower tendency to produce crystallographic defects. The compliance of the substantially single crystal layer 122 may be inversely proportional to the thickness of the substantially single crystal layer 122. Higher compliance can produce lower defect density in the epitaxial layer grown on the template and enable the growth of thicker epitaxial layers. In some embodiments, the thickness of the substantial single crystal layer 122 can be increased by epitaxially growing silicon on a peeled silicon layer.

Third, it may be beneficial to improve the smoothness of the substantially single crystal layer 122. The smoothness of the layer may be related to the total hydrogen dosage, the presence of any co-existing species, and the annealing conditions used to form the hydrogen-based cleavage plane. The initial roughness resulting from the layer transfer (i.e., cleavage step) may be reduced by thermal oxidation and oxide stripping, as discussed below.

In some embodiments, removing the damaged layer and adjusting the final thickness of the substantial single crystal layer 122 can be achieved by thermally oxidizing the top portion of the silicon layer, followed by oxide layer stripping using hydrogen fluoride (HF) acid. For example, a stripped silicon layer having an initial thickness of 0.5 μm can be thermally oxidized to produce a silicon dioxide layer having a thickness of about 420 nm. After removing the grown thermal oxide, the remaining silicon thickness in the transfer layer can be about 53 nm. During thermal oxidation, the implanted hydrogen may migrate to the surface. Therefore, the subsequent oxide layer stripping can remove some of the damage. Furthermore, thermal oxidation is typically performed at a temperature of 1000° C. or higher. Increased temperatures can also repair lattice damage.

The silicon oxide layer formed on the top portion of the substantially single crystal layer during thermal oxidation can be stripped using HF acid etching. The etching selectivity of the HF acid to silicon oxide and silicon ( _SiO2 :Si) can be adjusted by adjusting the temperature and concentration of the HF solution and the stoichiometry and density of the silicon oxide. Etching selectivity refers to the etching rate of one material relative to another material. The selectivity of the HF solution for ( _SiO2 :Si) can be in the range of about 10:1 to about 100:1. A high etching selectivity can reduce the surface roughness by a factor similar to the initial surface roughness. However, the surface roughness of the resulting substantially single crystal layer 122 may still be greater than desired. For example, a bulk Si(111) surface may have a root mean square (RMS) surface roughness of less than 0.1 nm as measured by a 2 μm×2 μm atomic force microscope (AFM) scan before additional processing. In some embodiments, the surface roughness required for epitaxial growth of gallium nitride material on Si(111) may be, for example, less than 1 nm, less than 0.5 nm, or less than 0.2 nm over a 30 μm×30 μm AFM scan area.

If the surface roughness of the substantial single crystal layer 122 after thermal oxidation and oxide layer stripping exceeds the desired surface roughness, additional surface smoothing may be performed. There are several methods for smoothing a silicon surface. Such methods may include hydrogen annealing, laser trimming, plasma smoothing, and contact polishing (e.g., chemical mechanical polishing or CMP). Such methods may involve preferentially etching high aspect ratio surface peaks. Thus, high aspect ratio features on the surface may be removed faster than low aspect ratio features, resulting in a smoother surface.

It should be understood that the specific steps illustrated in FIG. 5 provide a specific method for manufacturing an engineered substrate according to one embodiment of the present invention. Other step sequences may also be performed according to alternative embodiments. For example, alternative embodiments of the present invention may perform the above steps in different sequences. In addition, each step illustrated in FIG. 5 may include multiple sub-steps that may be performed in various sequences suitable for a single step. In addition, additional steps may be added or removed depending on the specific application. A person of ordinary skill in the art will recognize many variations, modifications, and substitutions.

FIG. 6 is a simplified schematic diagram of an epitaxial/engineered substrate structure for RF and power applications according to one embodiment of the present invention. In some LED applications, the engineered substrate structure provides a growth substrate capable of growing a high quality GaN layer and then removing the engineered substrate structure. However, for RF and power device applications, the engineered substrate structure forms some portion of the finished device, and as a result, the electrical, thermal and other properties of the engineered substrate structure or components of the engineered substrate structure are important for specific applications.

Referring to FIG. 1 , the single crystal silicon layer 122 is typically a peeling layer separated from a silicon donor wafer using implant and stripping techniques. Typical implants are hydrogen and boron. For power and RF component applications, the electrical properties of the layers and materials in the engineered substrate structure are important. For example, some component architectures use highly insulating silicon layers with a resistance greater than 10 ³ Ohm-cm to reduce or eliminate leakage through the substrate and interface layers. Other applications utilize designs that include a conductive silicon layer with a predetermined thickness (e.g., 1 μm) to connect the source of the component to other components. Therefore, in these applications, it is desirable to control the size and performance of the single crystal silicon layer. In designs where implant and strip techniques are used during layer transfer, residual implant atoms (e.g., hydrogen or boron) remain in the silicon layer, changing the electrical properties. Additionally, it can be difficult to control the thickness, conductivity, and other properties of thin silicon layers using, for example, adjustments in implant dosage, which affect conductivity as well as the full width at half height (FWHM) of the implant distribution, surface roughness, and cleavage plane location accuracy, as well as implant depth, which can affect layer thickness.

According to an embodiment of the present invention, silicon epitaxy on an engineered substrate structure is used to achieve desired properties of a single-crystal silicon layer suitable for a specific device design.

Referring to FIG. 6 , the epitaxial/engineered substrate structure 600 includes an engineered substrate structure 610 and a silicon epitaxial layer 620 formed on the engineered substrate structure 610. The engineered substrate structure 610 may be similar to the engineered substrate structures illustrated in FIGS. 1 , 3 , and 4 . Typically, after the layer transfer, the substantial single crystal silicon layer 122 is on the order of 0.5 μm. In some processes, a surface conditioning process may be used to reduce the thickness of the single crystal silicon layer 122 to about 0.3 μm. In order to increase the thickness of the single crystal silicon layer to about 1 μm for making, for example, a reliable ohmic contact, an epitaxial process is used to grow the epitaxial single crystal silicon layer 620 on the substantial single crystal silicon layer 122 formed by the layer transfer process. Various epitaxial growth processes may be used to grow the epitaxial single crystal silicon layer 620, including CVD, ALD, MBE, etc. The thickness of the epitaxial single crystal silicon layer 620 may be in the range of about 0.1 μm to about 20 μm, for example, between 0.1 μm and 10 μm.

FIG. 7 is a simplified schematic diagram illustrating a III-V epitaxial layer on an engineered substrate structure according to one embodiment of the present invention. As described below, the structure illustrated in FIG. 7 may be referred to as a dual epitaxial structure. As illustrated in FIG. 7, an engineered substrate structure 710 including an epitaxial single crystal silicon layer 620 has a III-V epitaxial layer 720 formed thereon. In one embodiment, the III-V epitaxial layer comprises gallium nitride (GaN).

Depending on the desired functionality, the desired thickness of the III-V epitaxial layer 720 can vary widely. In some embodiments, the thickness of the III-V epitaxial layer 720 can vary between 0.5 μm and 100 μm, such as a thickness greater than 5 μm. The resulting breakdown voltage of components fabricated on the III-V epitaxial layer 720 can vary depending on the thickness of the III-V epitaxial layer 720. Some embodiments provide a breakdown voltage of at least 100 V, 300 V, 600 V, 1.2 kV, 1.7 kV, 3.3 kV, 5.5 kV, 13 kV, or 20 kV.

To provide conductivity between certain portions of the III-V epitaxial layer 720, which may include multiple sublayers, a set of vias 724 are formed in this example from the top surface of the III-V epitaxial layer 720 into the epitaxial single crystal silicon layer 620. The vias 724 may be lined with an insulating layer (not shown) such that the vias 724 are insulated from the III-V epitaxial layer 720. As an example, such vias may be used to connect the electrodes of a diode or transistor to the underlying silicon layer by providing an ohmic contact through the vias, thereby mitigating charge accumulation in the device.

If the III-V epitaxial layer is grown on the single crystal silicon layer 122, it would be difficult to obtain such an ohmic contact through the via, because it would be difficult to terminate the via etch in the single crystal silicon layer 122: for example, reliably etching through 5μm of GaN across the wafer and terminating in a 0.3μm silicon layer. Using embodiments of the present invention, single crystal silicon layers with a thickness of several microns can be provided, which is difficult using implant and strip processes because high implant energies are required to achieve large implant depths. The thick silicon layer then enables applications such as the described vias that enable a wide variety of device designs.

In addition to increasing the thickness of the silicon "layer" by epitaxially growing single crystal silicon layer 620 on single crystal silicon layer 122, other adjustments may be made to the original properties of single crystal silicon layer 122, including modifications to conductivity, crystallinity, etc. For example, if a silicon layer on the order of 10 μm is required prior to additional epitaxial growth of a III-V layer or other material, such a thick layer may be grown in accordance with embodiments of the present invention.

Because the implantation process affects the properties of the single crystal silicon layer 122, for example, residual boron/hydrogen atoms may affect the electrical properties of silicon, embodiments of the present invention remove a portion of the single crystal silicon layer 122 before epitaxially growing the single crystal silicon layer 620. For example, the single crystal silicon layer 122 may be thinned to form a layer having a thickness of 0.1 μm or less, thereby removing most or all of the residual boron/hydrogen atoms. Then the subsequently grown single crystal silicon layer 620 is used to provide a single crystal material having electrical and/or other properties that are substantially unrelated to the corresponding properties of the layer formed using the layer transfer process.

In addition to increasing the thickness of the single crystal silicon material coupled to the engineered substrate structure, the electrical properties (including conductivity) of the epitaxial single crystal silicon layer 620 can be different from the electrical properties of the single crystal silicon layer 122. The epitaxial single crystal silicon layer 620 can be doped during growth to produce p-type silicon by doping with boron and n-type silicon by doping with phosphorus. Undoped silicon can be grown to provide high resistivity silicon for use in components with insulating regions. In particular, the insulating layer can be used for RF components.

The lattice constant of the epitaxial single crystal silicon layer 620 can be adjusted during growth to change the lattice constant of the single crystal silicon layer 122 to produce a strained epitaxial material. In addition to silicon, other elements can be epitaxially grown to provide layers, including strain layers containing silicon germanium or the like. For example, a buffer layer can be grown on the single crystal silicon layer 122, on the epitaxial single crystal silicon layer 620, or between layers to enhance subsequent epitaxial growth. Such buffer layers can include strained III-V layers, silicon germanium strain layers, etc. In addition, the buffer layers and other epitaxial layers can be graded by mole fraction, dopant, polarity, etc. Those skilled in the art will recognize many variations, modifications, and substitutions.

In some embodiments, strain present in the single crystal silicon layer 122 or the epitaxial single crystal silicon layer 620 can be relaxed during the growth of subsequent epitaxial layers (including III-V epitaxial layers).

FIG. 8 is a simplified flow chart illustrating a method of manufacturing an engineered substrate according to another embodiment of the present invention. The method includes forming a support structure by providing a polycrystalline ceramic core (810), forming a first bonding layer (812) coupled to at least a portion of the polycrystalline ceramic core. The first bonding layer may include a tetraethyl orthosilicate (TEOS) layer. The method also includes forming a conductive layer (814) coupled to the first bonding layer. The conductive layer may be a polycrystalline silicon layer. The first bonding layer may be formed as a single layer of TEOS. The conductive layer may be formed as a single layer of polycrystalline silicon.

The method also includes forming a second adhesive layer (816) coupled to at least a portion of the conductive layer, and forming a barrier shell (818). The second adhesive layer can be formed as a single layer of TEOS. The barrier shell can be formed as a single layer of silicon nitride or a series of sub-layers forming the barrier shell.

Once the support structure is formed by processes 810-818, the method further includes bonding a bonding layer (e.g., a silicon oxide layer) to the support structure (820) and bonding a substantially single crystalline silicon layer or a substantially single crystalline layer to the silicon oxide layer (822). Bonding of the bonding layer may include depositing a bonding material as described herein, followed by a planarization process.

A layer transfer process may be used to bond the substantially single crystal silicon layer 122 to the bonding layer 120. In some embodiments, a silicon wafer (e.g., a silicon (111) wafer) is implanted to form a cleavage plane. After the wafers are bonded, the silicon substrate may be removed along with the portion of the single crystal silicon layer below the cleavage plane, thereby producing the peeled single crystal silicon layer 122 illustrated in FIG. 1. The thickness of the substantially single crystal silicon layer 122 may be varied to meet the specifications of various applications. In addition, the crystal orientation of the substantially single crystal layer 122 may be varied to meet the specifications of the application. In addition, the doping level and distribution in the substantially single crystal layer 122 may be varied to meet the specifications of a particular application. In some embodiments, the substantially single crystal silicon layer 122 may be smoothed as described above.

The method illustrated in FIG. 8 may also include forming an epitaxial silicon layer (824) by epitaxial growth on the substantially single crystal silicon layer, and forming an epitaxial III-V layer (826) by epitaxial growth on the epitaxial silicon layer. In some embodiments, the epitaxial III-V layer may include gallium nitride (GaN).

It should be understood that the specific steps illustrated in FIG. 8 provide a specific method for manufacturing an engineered substrate according to another embodiment of the present invention. Other step sequences may also be performed according to alternative embodiments. For example, alternative embodiments of the present invention may perform the above steps in different sequences. In addition, each step illustrated in FIG. 8 may include multiple sub-steps that may be performed in various sequences suitable for a single step. In addition, additional steps may be added or removed depending on the specific application. A person of ordinary skill in the art will recognize many variations, modifications, and substitutions.

It should also be understood that the examples and embodiments described herein are for illustrative purposes only, and that in view of such examples and embodiments, various modifications or changes will be conceivable to those with ordinary knowledge in the art and will be included within the spirit and scope of this application and the scope of the attached patent application.

100: Engineering substrate

110: Core

112: First adhesive layer

114: Conductive layer

116: Second adhesive layer

118: Barrier layer

120: Binding layer

122: Substantial single crystal silicon layer

130: Epitaxial materials

Claims (24)

An engineering substrate comprises: a supporting structure, comprising: a polycrystalline ceramic core; a first adhesive layer encapsulating the polycrystalline ceramic core; a barrier layer encapsulating the first adhesive layer; a second adhesive layer coupled to the barrier layer; and a conductive layer coupled to the second adhesive layer; a bonding layer coupled to the supporting structure; a substantially single crystal silicon layer coupled to the bonding layer; and an epitaxial semiconductor layer coupled to the substantially single crystal silicon layer. An engineered substrate as described in claim 1, wherein the polycrystalline ceramic core comprises aluminum nitride. An engineered substrate as described in claim 1, wherein the bonding layer comprises silicon oxide. An engineered substrate as described in claim 1, wherein the epitaxial semiconductor layer includes an epitaxial III-V layer. An engineered substrate as described in claim 4, wherein the epitaxial III-V layer comprises an epitaxial gallium nitride layer. An engineered substrate as described in claim 5, wherein the epitaxial gallium nitride layer has a thickness of about 5 μm or greater. An engineering substrate as described in claim 1, wherein the epitaxial semiconductor layer includes an epitaxial single crystal silicon layer. The engineered substrate as described in claim 7 further comprises an epitaxial III-V layer, the epitaxial III-V layer being coupled to the epitaxial single crystal silicon layer. The engineering substrate as described in claim 8 further comprises a plurality of through holes extending from the epitaxial III-V layer into the epitaxial single crystal silicon layer. An engineered substrate as described in claim 1, wherein the substantially single crystal silicon layer comprises a peeled silicon layer. An engineering substrate as described in claim 1, wherein the substantially single-crystal silicon layer comprises a peel-off silicon layer and an epitaxial silicon layer grown on the peel-off silicon layer, and the substantially single-crystal silicon layer has a thickness of about 0.5 μm. An engineered substrate as described in claim 1, wherein: the first adhesive layer comprises a first tetraethyl orthosilicate (TEOS) layer encapsulating the polycrystalline ceramic core; the barrier layer comprises a silicon nitride layer; the second adhesive layer comprises a second TEOS layer; and the conductive layer comprises a polycrystalline silicon layer. An engineering substrate comprises: a supporting structure, comprising: a polycrystalline ceramic core; a first adhesive layer encapsulating the polycrystalline ceramic core; a barrier layer encapsulating the first adhesive layer; a second adhesive layer coupled to the barrier layer; and a conductive layer coupled to the second adhesive layer; a bonding layer coupled to the supporting structure; a substantial single crystal layer coupled to the bonding layer; and an epitaxial semiconductor layer coupled to the substantial single crystal layer. An engineered substrate as described in claim 13, wherein the polycrystalline ceramic core comprises aluminum nitride. An engineered substrate as described in claim 13, wherein the bonding layer comprises silicon oxide. An engineered substrate as described in claim 13, wherein the epitaxial semiconductor layer includes an epitaxial III-V layer. An engineered substrate as described in claim 16, wherein the epitaxial III-V layer comprises an epitaxial gallium nitride layer. An engineered substrate as described in claim 17, wherein the epitaxial gallium nitride layer has a thickness of about 5 μm or greater. An engineering substrate as described in claim 13, wherein the epitaxial semiconductor layer includes an epitaxial single crystal silicon layer. The engineered substrate as described in claim 19 further comprises an epitaxial III-V layer, the epitaxial III-V layer being coupled to the epitaxial single crystal silicon layer. The engineering substrate as described in claim 20 further comprises a plurality of through holes extending from the epitaxial III-V layer into the epitaxial single crystal silicon layer. An engineered substrate as described in claim 13, wherein the substantially single crystal layer comprises a silicon carbide layer. An engineered substrate as described in claim 13, wherein the substantially single crystal layer comprises a sapphire layer. An engineered substrate as described in claim 13, wherein: the first adhesive layer comprises a first tetraethyl orthosilicate (TEOS) layer encapsulating the polycrystalline ceramic core; the barrier layer comprises a silicon nitride layer; the second adhesive layer comprises a second TEOS layer; and the conductive layer comprises a polycrystalline silicon layer.