JP2019523994A - Designed substrate structure for power and RF applications - Google Patents

Abstract

The substrate includes a polycrystalline ceramic core, a first adhesive layer bonded to the polycrystalline ceramic core, a conductive layer bonded to the first adhesive layer, a second adhesive layer bonded to the conductive layer, A support structure comprising a barrier layer coupled to a second adhesive layer. The substrate also includes a silicon oxide layer coupled to the support structure, a substantially single crystal silicon layer coupled to the silicon oxide layer, and an epitaxial III-V layer coupled to the substantially single crystal silicon layer. [Selection] Figure 1

Description

Cross-reference of related applications
[0001] This application is filed on June 14, 2016, US Provisional Patent Application No. 62 / 350,084, entitled "ENGINEERED SUBSTRATE FOR STRUCTURE FOR RF APPLICATIONS", and June 14, 2016. Claimed priority under US Provisional Patent Application No. 62 / 350,077 entitled “ENGINEERED SUBSTRATE STRUCTURE AND METHOD OF MANUFACTURE” filed on the same date, the disclosure of which is incorporated herein by reference The entirety of which is incorporated herein by reference.

  [0002] The following two US patent applications are filed concurrently with this application, the disclosures of these two applications are hereby incorporated by reference in their entirety for all purposes.

  [0003] Application No. 15 / 621,335 filed June 13, 2017, entitled "ENGINEERED SUBSTRATE STRUCTURE FOR POWER AND RF APPLICATIONS" (Attorney Docket No. 098825-1049529-001110US).

  [0004] Application No. 15 / 621,338 (Attorney Docket No. 098825-1049532-USUS), filed June 13, 2017, entitled "ENGINEERED SUBSTRATE STRUCTURE AND METHOD OF MANUFACTURE".

  [0005] Light emitting diode (LED) structures are typically grown epitaxially on a sapphire substrate. Currently, many products use LED devices, including lighting, computer monitors, and other display devices.

  [0006] Growth of gallium nitride based LED structures on a sapphire substrate is a heteroepitaxial growth process because the substrate and the epitaxial layer are composed of different materials. Due to the heteroepitaxial growth process, the epitaxially grown material can exhibit a variety of adverse effects including reduced uniformity and reduced metrics associated with the electronic / optical properties of the epitaxial layer. Accordingly, there is a need in the art for improved methods and systems related to epitaxial growth processes and substrate structures.

  [0007] The present invention relates generally to designed substrate structures. More specifically, the present invention relates to methods and systems suitable for use in epitaxial growth processes. By way of example only, the present invention has been applied to a method and system for providing a substrate structure suitable for epitaxial growth, which structure has a coefficient of thermal expansion (CTE) that is substantially compatible with the epitaxial layer grown thereon. Characterized. The methods and techniques can be applied to various semiconductor processing operations.

  [0008] According to an embodiment of the invention, a substrate is provided. The substrate includes a polycrystalline ceramic core, a first adhesive layer bonded to the polycrystalline ceramic core, a conductive layer bonded to the first adhesive layer, a second adhesive layer bonded to the conductive layer, A support structure comprising a barrier layer coupled to a second adhesive layer. The substrate also includes a silicon oxide layer coupled to the support structure, a substantially single crystal silicon layer coupled to the silicon oxide layer, and an epitaxial III-V layer coupled to the substantially single crystal silicon layer.

  [0009] According to another embodiment of the present invention, a method of manufacturing a substrate is provided. The method includes providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core in a first adhesive shell, encapsulating the first adhesive shell in a conductive shell, and a conductive shell. Encapsulating in a second adhesive shell and encapsulating the second adhesive shell in a barrier shell. The method also includes bonding the bonding layer to the support structure, bonding the substantially single crystal silicon layer to the bonding layer, and forming an epitaxial silicon layer on the substantially single crystal silicon layer by epitaxial growth. Forming an epitaxial III-V layer on the epitaxial silicon layer by epitaxial growth.

  [0010] According to certain embodiments of the invention, a designed substrate structure is provided. The designed substrate structure includes a support structure, a bonding layer bonded to the support structure, a substantially single crystal silicon layer bonded to the bonding layer, and an epitaxial single crystal silicon layer bonded to the substantially single crystal silicon layer. Including. The support structure includes a polycrystalline ceramic core, a first adhesive layer bonded to the polycrystalline ceramic core, a conductive layer bonded to the first adhesive layer, and a second adhesive layer bonded to the conductive layer. And a barrier shell coupled to the second adhesive layer.

  [0011] Many advantages are achieved by the present invention over the prior art. For example, embodiments of the present invention provide a designed substrate structure that is CTE aligned to a gallium nitride based epitaxial layer suitable for use in optical, electronic, and optoelectronic applications. The encapsulation layer utilized as a component of the designed substrate structure prevents the diffusion of impurities present in the central portion of the substrate from reaching the semiconductor processing environment in which the designed substrate is utilized. Important properties associated with substrate materials, including coefficient of thermal expansion, lattice mismatch, thermal stability, shape control, have been improved with gallium nitride based epitaxial and device layers and various device architectures and performance goals (e.g. Designed uniquely for optimized) alignment. Process integration is simplified because the substrate material layers are integrated together in a conventional semiconductor manufacturing process. These and other embodiments of the present invention, as well as many of its advantages and features, will be described in more detail in connection with the following text and the accompanying drawings.

FIG. 2 is a simplified schematic diagram illustrating a designed substrate structure according to an embodiment of the present invention. FIG. 4 is a SIMS profile showing the seed concentration as a function of depth for a designed structure according to an embodiment of the invention. FIG. 4 is a SIMS profile showing seed concentration as a function of depth for a designed structure after annealing according to an embodiment of the present invention. 4 is a SIMS profile showing seed concentration as a function of depth for a designed structure with a annealed silicon nitride layer according to an embodiment of the present invention. FIG. 4 is a simplified schematic diagram illustrating a designed substrate structure according to another embodiment of the present invention. FIG. 6 is a simplified schematic diagram illustrating a designed substrate structure according to yet another embodiment of the present invention. 3 is a simplified flowchart illustrating a method of manufacturing a designed substrate according to an embodiment of the present invention. FIG. 2 is a simplified schematic diagram illustrating an epitaxial / designed substrate structure for RF and power applications according to one embodiment of the present invention. FIG. 5 is a simplified schematic diagram illustrating a III-V epitaxial layer on a designed substrate structure according to an embodiment of the present invention. 6 is a simplified flowchart illustrating a method of manufacturing a designed substrate according to another embodiment of the present invention.

  [0022] Embodiments of the invention relate to a designed substrate structure. More specifically, the present invention relates to methods and systems suitable for use in epitaxial growth processes. By way of example only, the present invention has been applied to a method and system for providing a substrate structure suitable for epitaxial growth, which structure has a coefficient of thermal expansion (CTE) that is substantially compatible with the epitaxial layer grown thereon. Characterized. The methods and techniques can be applied to various semiconductor processing operations.

  [0023] FIG. 1 is a simplified schematic diagram illustrating a designed substrate structure according to an embodiment of the present invention. The designed substrate 100 shown in FIG. 1 is suitable for various electronic and optical applications. The designed substrate includes a core 110 that can have a coefficient of thermal expansion (CTE) that substantially matches the CTE of the epitaxial material grown on the designed substrate 100. Epitaxial material 130 is not required as a component of a designed substrate, but is shown as an option because it is typically grown on a designed substrate.

[0024] For applications involving the growth of gallium nitride (GaN) based materials (epitaxial layers including GaN based layers), the core 110 may include a polycrystalline ceramic material, for example, a polycrystalline material such as yttrium oxide. Aluminum nitride (AlN) can be used. Other materials including polycrystalline gallium nitride (GaN), polycrystalline aluminum gallium nitride (AlGaN), polycrystalline silicon carbide (SiC), polycrystalline zinc oxide (ZnO), polycrystalline gallium trioxide (Ga ₂ O ₃ ), etc. Can be used for the core 110.

[0025] The thickness of the core may be on the order of 100-1500 μm, for example 725 μm. The core 110 is encapsulated in a first adhesive layer 112, which can be referred to as a shell or encapsulated shell. In one embodiment, the first adhesive layer 112 includes a tetraethylorthosilicate (TEOS) layer having a thickness on the order of 1,000 mm. In other embodiments, the thickness of the first adhesive layer varies, for example, from 100 to 2,000 inches. In some embodiments, TEOS is utilized for the adhesion layer, although other materials that provide adhesion between the subsequently deposited layer and the underlying layer or material (eg, ceramics, particularly polycrystalline ceramics) are also present. Available according to embodiments of the invention. For example, SiO ₂ or other silicon oxide (Si _x O _y ) adheres well to the ceramic material and provides a suitable surface for subsequent deposition of, for example, conductive materials. In some embodiments, the first adhesive layer 112 may completely form the core 110 to form a fully encapsulated core and may be formed using an LPCVD process. The first adhesive layer 112 provides a surface onto which subsequent layers are bonded to form the designed substrate structure elements.

  [0026] In addition to the use of LPCVD processes, furnace-based processes, etc. to form the first encapsulating adhesive layer, other semiconductor processes including CVD processes or similar deposition processes may be utilized in accordance with embodiments of the present invention. Can do. As an example, a deposition process that covers a portion of the core can be utilized, the core can be turned over, and the deposition process can be repeated to cover additional portions of the core. Thus, in some embodiments, LPCVD techniques are utilized to provide a fully enclosed structure, although other deposition techniques can be utilized depending on the particular application.

  A conductive layer 114 is formed so as to surround the adhesive layer 112. In one embodiment, because polysilicon has poor adhesion to ceramic materials, the conductive layer 114 is a polysilicon (ie, polycrystalline silicon) shell formed to surround the first adhesive layer 112. In embodiments where the conductive layer is polysilicon, the thickness of the polysilicon layer can be on the order of 500-5,000 mm, for example 2,500 mm. In some embodiments, the polysilicon layer can be formed as a shell that completely surrounds the first adhesive layer 112 (eg, TEOS layer), thereby fully encapsulating the first adhesive layer. And can be formed using an LPCVD process. In other embodiments, as described below, the conductive material can be formed on a portion of the adhesive layer, eg, the lower half of the substrate structure. In some embodiments, the conductive material can be formed as a fully encapsulated layer and subsequently removed on one side of the substrate structure.

[0028] In one embodiment, the conductive layer 114 may be a polysilicon layer that is doped to provide a highly conductive material, such as a polysilicon layer that is doped with boron to provide a p-type polysilicon layer. In some embodiments, the doping with boron is at a level of 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ to provide high conductivity. Other dopants with different dopant concentrations (eg, phosphorus, arsenic, bismuth, etc. with dopant concentrations ranging from 1 × 10 ¹⁶ cm ⁻³ to 5 × 10 ¹⁸ cm ⁻³ ) for use in conductive layers Any suitable n-type or p-type semiconductor material can be provided. Those skilled in the art will recognize many variations, modifications, and alternatives.

  [0029] The presence of conductive layer 114 is useful in electrostatic chucking the designed substrate to a semiconductor processing tool, such as a tool having an electrostatic chuck (ESC). Conductive layer 114 allows for rapid dechucking after processing in a semiconductor processing tool. Accordingly, embodiments of the present invention provide a substrate structure that can be processed in a manner utilized with conventional silicon wafers. Those skilled in the art will recognize many variations, modifications, and alternatives.

  [0030] A second adhesive layer 116 (eg, a TEOS layer having a thickness of about 1,000 mm) is formed surrounding the conductive layer 114. In some embodiments, the second adhesion layer 116 completely surrounds the conductive layer 114 to form a complete encapsulating structure, including LPCVD processes, CVD processes, or any other suitable deposition including spin-on dielectric deposition. It can be formed using a deposition process.

  [0031] A barrier layer 118, eg, a silicon nitride layer, is formed to surround the second adhesion layer 116. In one embodiment, the barrier layer 118 is a silicon nitride layer 118 having a thickness on the order of 2,000 to 5,000 mm. The barrier layer 118, in some embodiments, completely surrounds the second adhesion layer 116 to form a complete encapsulation structure and can be formed using an LPCVD process. In addition to the silicon nitride layer, an amorphous material containing SiCN, SiON, AlN, SiC, or the like can be used as the barrier layer. In some embodiments, the barrier layer 118 includes several sublayers constructed to form the barrier layer. Thus, the term barrier layer is not intended to mean a single layer or a single material, but is intended to encompass one or more materials laminated in a composite manner. Those skilled in the art will recognize many variations, modifications, and alternatives.

  [0032] In some embodiments, the barrier layer 118, eg, a silicon nitride layer, cores the semiconductor substrate into a semiconductor processing chamber environment where the designed substrate can exist, for example, during a high temperature (eg, 1,000 ° C.) epitaxial growth process. Elements present in 110, such as yttrium oxide (ie, yttria), oxygen, metal impurities, other trace elements, etc., are prevented from diffusing and / or outgassing. Utilizing the encapsulation layers described herein, ceramic materials including polycrystalline AlN designed for non-clean room environments can be utilized in semiconductor process flows and clean room environments.

  [0033] FIG. 2A is a secondary ion mass spectrometry (SIMS) profile showing species concentration as a function of depth for a designed structure according to one embodiment of the invention. The designed structure did not include the barrier layer 118. Referring to FIG. 2A, some species (eg, yttrium, calcium, and aluminum) present in the ceramic core are reduced to negligible concentrations in the designed layers 120/122. The concentrations of calcium, yttrium, and aluminum are reduced by 3, 4, and 6 orders of magnitude, respectively.

  [0034] FIG. 2B is a SIMS profile showing the seed concentration as a function of depth for a designed structure without a barrier layer after annealing according to an embodiment of the invention. As mentioned above, during semiconductor processing operations, the designed substrate structure provided by embodiments of the present invention may be exposed to high temperatures (about 1100 ° C.) for several hours, for example during epitaxial growth of GaN-based layers. is there.

  [0035] For the profile shown in FIG. 2B, the designed substrate structure was annealed at 1100 ° C. for 4 hours. As shown in FIG. 2B, calcium, yttrium, and aluminum that were originally present at low concentrations in the as-deposited sample diffused into the designed layer and reached concentrations similar to the other elements.

  [0036] FIG. 2C is a SIMS profile showing seed concentration as a function of depth for a designed structure having a barrier layer after annealing, according to one embodiment of the invention. Integration of the diffusion barrier layer 118 (eg, a silicon nitride layer) into the designed substrate structure into the designed layers of calcium, yttrium, and aluminum during the annealing process that occurred in the absence of the diffusion barrier layer. Prevent the spread of. As shown in FIG. 2C, calcium, yttrium, and aluminum present in the ceramic core remain at low concentrations in the designed layer after annealing. Thus, the use of a barrier layer 118 (eg, a silicon nitride layer) prevents these elements from diffusing through the diffusion barrier, thereby preventing them from being released into the environment surrounding the designed substrate. Similarly, any other impurities contained within the bulk ceramic material are also contained by the barrier layer.

  [0037] Typically, the ceramic material utilized to form the core 110 is fired at a temperature in the range of 1800 ° C. This process is expected to remove a significant amount of impurities present in the ceramic material. These impurities can include yttrium, calcium, and other elements and compounds resulting from the use of yttria as a sintering agent. Subsequently, during the epitaxial growth process performed at a much lower temperature in the range of 800 ° C. to 1100 ° C., subsequent diffusion of these impurities would be expected to be negligible. However, contrary to conventional expectations, we can see that significant diffusion of elements through the layers of the engineered substrate can occur even during the epitaxial growth process at temperatures much lower than the firing temperature of the ceramic material. I found out. Thus, embodiments of the invention integrate barrier layer 118 (eg, a silicon nitride layer) into an epitaxial layer 120/122 designed from a polycrystalline ceramic material (eg, AlN) as well as optional GaN layer 130, etc. Prevent out-diffusion of background elements into layers. A silicon nitride layer 118 that encapsulates the underlying layers and materials provides the desired barrier layer function.

  [0038] As shown in FIG. 2B, the elements originally present in the core 110, including yttrium, enter the first TEOS layer 112, the polysilicon layer 114, and the second TEOS layer 116. It also diffuses through them. However, the presence of the silicon nitride layer 118 prevents these elements from diffusing through the silicon nitride layer, thereby preventing their release into the environment surrounding the designed substrate, as shown in FIG. 2C. prevent.

  [0039] Referring again to FIG. 1, a bonding layer 120 (eg, a silicon oxide layer) is deposited on a portion of the barrier layer 118, eg, the top surface of the barrier layer, and then bonded to the substantially single crystal silicon layer 122. Used inside. The bonding layer 120 may have a thickness of about 1.5 μm in some embodiments.

  [0040] The substantially single crystal layer 122 is suitable for use as a growth layer during an epitaxial growth process to form the epitaxial material 130. In some embodiments, the epitaxial material 130 includes a 2 μm to 10 μm thick GaN layer that is utilized as one of a plurality of layers utilized in optoelectronic devices, RF devices, power devices, and the like. can do. In one embodiment, the substantially single crystal layer 122 includes a substantially single crystal silicon layer that is attached to the silicon oxide layer 118 using a layer transfer process.

  [0041] FIG. 3 is a simplified schematic diagram illustrating a designed substrate structure according to one embodiment of the invention. The designed substrate 300 shown in FIG. 3 is suitable for various electronic and optical applications. The designed substrate includes a core 110 that can have a coefficient of thermal expansion (CTE) that substantially matches the CTE of the epitaxial material 130 grown on the designed substrate 300. Epitaxial material 130 is not required as an element of a designed substrate structure, but is shown as an option because it is typically grown on a designed substrate structure.

  [0042] For applications involving the growth of gallium nitride (GaN) based materials (epitaxial layers including GaN based layers), the core 110 can be a polycrystalline ceramic material, such as polycrystalline aluminum nitride (AlN). The thickness of the core may be about 100 to 1500 μm, for example, 725 μm. The core 110 is encapsulated in a first adhesive layer 112, which can be referred to as a shell or encapsulated shell. In this embodiment, the first adhesive layer 112 completely encapsulates the core, but this is not required by the present invention as discussed in more detail with respect to FIG.

[0043] In one embodiment, the first adhesive layer 112 includes a tetraethylorthosilicate (TEOS) layer having a thickness on the order of 1,000 mm. In other embodiments, the thickness of the first adhesive layer varies, for example, from 100 to 2,000 inches. In some embodiments, TEOS is utilized for the adhesion layer, although other materials that provide adhesion between a subsequently deposited layer and the underlying layer or material may also be utilized in accordance with embodiments of the present invention. For example, SiO _2, SiON or the like is often adhered to the ceramic material to provide a surface suitable for example for the subsequent deposition of conductive material. In some embodiments, the first adhesive layer 112 may completely form the core 110 to form a fully encapsulated core and may be formed using an LPCVD process. The adhesive layer provides a surface onto which subsequent layers are adhered to form the designed substrate structure elements.

  [0044] In addition to the use of LPCVD processes, furnace-based processes, etc. to form the encapsulating adhesive layer, other semiconductor processes can be utilized in accordance with embodiments of the present invention. As an example, a deposition process such as CVD, PECVD, etc. that covers a portion of the core can be utilized, the core can be turned over, and the deposition process can be repeated to cover additional portions of the core .

  [0045] A conductive layer 314 is formed on at least a portion of the first adhesive layer 112. In one embodiment, the conductive layer 314 includes polysilicon (ie, polycrystalline silicon) formed by a deposition process on the bottom (eg, lower half or back side) of the core / adhesion layer structure. In embodiments where the conductive layer is polysilicon, the thickness of the polysilicon layer can be on the order of thousands of angstroms, for example 3,000 mm. In some embodiments, the polysilicon layer can be formed using an LPCVD process.

[0046] In one embodiment, the conductive layer 314 can be a polysilicon layer that is doped to provide a highly conductive material, for example, the conductive layer 314 is doped with boron to provide a p-type polysilicon layer. can do. In some embodiments, the doping with boron is at a level in the range of about 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ to provide high conductivity. The presence of the conductive layer is useful in electrostatic chucking the designed substrate to a semiconductor processing tool, such as a tool having an electrostatic chuck (ESC). Conductive layer 314 allows for rapid dechucking after processing. Accordingly, embodiments of the present invention provide a substrate structure that can be processed in a manner utilized with conventional silicon wafers. Those skilled in the art will recognize many variations, modifications, and alternatives.

  [0047] A second adhesive layer 316 (eg, a second TEOS layer) is formed surrounding the conductive layer 314 (eg, a polysilicon layer). The thickness of the second adhesive layer 316 is about 1,000 mm. In some embodiments, the second adhesive layer 316 completely surrounds the conductive layer 314 and the first adhesive layer 112 to form a complete encapsulation structure and can be formed using an LPCVD process. . In other embodiments, the second adhesive layer 316 only partially surrounds the conductive layer 314 that terminates at a location indicated by, for example, a plane 317 that can be aligned with the top surface of the conductive layer 314. In this example, the upper surface of the conductive layer 314 is in contact with part of the barrier layer 118. Those skilled in the art will recognize many variations, modifications, and alternatives.

  [0048] A barrier layer 118 (eg, a silicon nitride layer) is formed to surround the second adhesive layer 316. In some embodiments, the thickness of the barrier layer 118 is on the order of 4,000 mm to 5,000 mm. In some embodiments, the barrier layer 118 completely surrounds the second adhesive layer 316 to form a complete encapsulation structure and can be formed using an LPCVD process.

  [0049] In some embodiments, the use of a silicon nitride barrier layer allows the engineered substrate to enter the core 110 environment into a semiconductor processing chamber environment where it can exist during, for example, a high temperature (eg, 1,000 ° C.) epitaxial growth process. Preventing diffusion and / or outgassing of elements present in the substrate, such as yttrium oxide (ie, yttria), oxygen, metal impurities, other trace elements, and the like. Utilizing the encapsulation layers described herein, ceramic materials including polycrystalline AlN designed for non-clean room environments can be utilized in semiconductor process flows and clean room environments.

  [0050] FIG. 4 is a simplified schematic diagram illustrating a designed substrate structure according to another embodiment of the present invention. In the embodiment shown in FIG. 4, the first adhesive layer 412 is formed on at least a part of the core 110, but does not enclose the core 110. In this embodiment, the first adhesive layer 412 is the bottom surface of the core 110 (the back side of the core 110) to enhance the adhesion of the subsequently formed conductive layer 414, as described more fully below. Formed. Although the adhesive layer 412 is only shown on the lower surface of the core 110 in FIG. 4, the deposition of the adhesive layer material on other parts of the core does not adversely affect the performance of the designed substrate structure, such a material. It will be appreciated that can exist in various embodiments. Those skilled in the art will recognize many variations, modifications, and alternatives.

  [0051] The conductive layer 414 does not encapsulate the first adhesive layer 412 and the core 110, but is substantially aligned with the first adhesive layer 412. The conductive layer 414 is shown to extend along the bottom or back surface of the first adhesive layer 412 and to extend upward along a portion of the side surface, but the extension along the vertical surface is according to the present invention. Not needed. Thus, embodiments can utilize deposition on one side of the substrate structure, masking on one side of the substrate structure, and the like. The conductive layer 414 can be formed on one surface of the first adhesive layer 412, for example, a part of the bottom surface / back surface. Conductive layer 414 provides electrical conduction to one side of the designed substrate structure, which can be advantageous in RF and high power applications. The conductive layer can include doped polysilicon as described with respect to the conductive layer 114 of FIG.

  [0052] A portion of the core 110, a portion of the first adhesive layer 412 and the conductive layer 414 are covered with a second adhesive layer 416 to enhance the adhesion of the barrier layer 418 to the underlying material. ing. As described above, the barrier layer 418 forms an encapsulating structure for preventing diffusion from the lower layer.

  [0053] In addition to the semiconductor-based conductive layer, in other embodiments, the conductive layer 414 is a metal layer, such as 500 チ タ ン titanium.

  [0054] Referring again to FIG. 4, depending on the embodiment, one or more layers may be removed. For example, layers 412 and 414 can be removed, leaving only a single adhesive shell 416 and barrier layer 418. In another embodiment, only layer 414 can be removed. In this embodiment, the layer 412 can also balance the stress caused by the layer 120 deposited on the layer 418 and the bending of the wafer. The configuration of a substrate structure having an insulating layer on the top surface of core 110 (eg, having only an insulating layer between core 110 and layer 120) benefits power / RF applications where a highly insulating substrate is desirable.

  [0055] In another embodiment, the barrier layer 418 may directly encapsulate the core 110, followed by the conductive layer 414 followed by the adhesive layer 416. In this embodiment, layer 120 can be deposited directly on adhesive layer 416 from the top surface. In yet another embodiment, an adhesive layer 416 can be deposited on the core 110, followed by a barrier layer 418, followed by a conductive layer 414, and another adhesive layer 412.

  [0056] Although some embodiments have been discussed with respect to layers, the term layer is understood so that a layer can include several sub-layers that are constructed to form a layer of interest. It should be. Thus, the term layer is not intended to mean a single layer of a single material, but is intended to encompass one or more materials that are laminated together to form the desired structure. Those skilled in the art will recognize many variations, modifications, and alternatives.

  [0057] FIG. 5 is a simplified flowchart illustrating a method of manufacturing a designed substrate according to an embodiment of the present invention. Using this method, a substrate that is CTE matched to one or more epitaxial layers grown on the substrate can be manufactured. The method 500 includes providing a polycrystalline ceramic core (510), encapsulating the polycrystalline ceramic core in a first adhesive layer (eg, a tetraethylorthosilicate (TEOS) shell) that forms the shell (512), and Forming a support structure by encapsulating a first adhesive layer in a conductive shell (514) (eg, a polysilicon shell). The first adhesive layer can be formed as a single layer of TEOS. The conductive shell can be formed as a single layer of polysilicon.

  [0058] The method also encapsulates a conductive shell in a second adhesive layer (516) (eg, a second TEOS shell) and encapsulates the second adhesive layer in a barrier layer shell (518). Including. The second adhesive layer can be formed as a single layer of TEOS. The barrier layer shell can be formed as a single layer of silicon nitride.

[0059] Once the support structure is formed by processes 510-518, the method includes bonding a bonding layer (eg, a silicon oxide layer) to the support structure (520) and a substantially single crystal layer, eg, a substantially single layer. Bonding the crystalline silicon layer to the silicon oxide layer (522). In accordance with embodiments of the present invention, other substantially single crystal layers including SiC, sapphire, GaN, AlN, SiGe, Ge, diamond, Ga ₂ O ₃ , ZnO, and the like can be used. Bonding the bonding layer can include deposition of a bonding material followed by a planarization process as described herein. In embodiments described below, bonding a substantially single crystal layer (eg, a substantially single crystal silicon layer) to a bonding layer utilizes a layer transfer process in which the layer is a single crystal silicon layer that is transferred from a silicon wafer. .

  [0060] Referring to FIG. 1, the bonding layer 120 is a chemical mechanical polishing (CMP) process in which the oxide is subsequently thinned to a thickness of about 1.5 μm by deposition of a thick (eg, 4 μm thick) oxide layer. Can be formed. The thick initial oxide fills the voids and surface features present on the support structure that may be present after fabrication of the polycrystalline core and may continue to exist when the encapsulation layer shown in FIG. 1 is formed. To help. The CMP process provides a substantially flat surface that is free of voids, particles, or other features, which are then used during the wafer transfer process to provide a substantially single crystal layer 122 (eg, substantially single crystal silicon). Layer) can be bonded to the bonding layer 120. The bonding layer 120 need not be characterized by an atomically flat surface, but a substantially flat surface that supports bonding of a substantially single crystal layer (eg, a substantially single crystal silicon layer) with the desired reliability. Should be provided.

  [0061] A substantially single crystal silicon layer 122 can be bonded to the bonding layer 120 using a layer transfer process. In some embodiments, a silicon wafer (eg, a silicon (111) wafer) is implanted to form a cleavage plane. After the wafer bonding, the silicon substrate can be removed together with a part of the single crystal silicon layer under the cleavage plane, and as a result, the peeled single crystal silicon layer 122 shown in FIG. 1 is obtained. The thickness of the substantially single crystal layer 122 can be varied to meet various application specifications. Further, the crystal orientation of the substantially single crystal layer 122 can be varied to meet the application specifications. Further, the doping level and profile in the substantially single crystal layer 122 can be varied to meet the specifications of a particular application.

  [0062] The method shown in FIG. 5 may also include smoothing the substantially single crystal layer (524). In some embodiments, the thickness and surface roughness of the substantially single crystal layer 122 can be modified for high quality epitaxial growth. Different device applications may have slightly different specifications regarding the thickness and surface smoothness of the substantially single crystal layer 122. The cleavage process strips the substantially single crystal layer 122 from the bulk single crystal silicon wafer at the peak of the implanted ion profile. After cleaving, the substantially single crystal layer 122 can be adjusted or modified in several ways before being utilized as a growth surface for epitaxial growth of other materials such as gallium nitride.

  [0063] First, the transferred substantially single crystal layer 122 may contain a small amount of residual hydrogen concentration and may have some crystal damage due to implantation. Accordingly, it may be beneficial to remove a thin portion of the transferred substantially single crystal layer 122 where the crystal lattice is damaged. In some embodiments, the depth of implantation can be adjusted to be greater than the desired final thickness of the substantially single crystal layer 122. The additional thickness allows removal of a thin portion of the damaged transferred substantially monocrystalline layer, leaving an undamaged portion of the desired final thickness.

  [0064] Second, it may be desirable to adjust the overall thickness of the substantially single crystal layer 122. In general, the substantially single crystal layer 122 is thick enough to provide a high quality lattice template for subsequent growth of one or more epitaxial layers, but desirably thin enough to be highly compatible. The substantially single crystal layer 122 is not substantially constrained in its physical properties and can mimic the physical properties of the surrounding material in a tendency to be less prone to crystal defects. If it is relatively thin, it can be said to be “fit”. The adaptation of the substantially single crystal layer 122 may be inversely proportional to the thickness of the substantially single crystal layer 122. The higher the match, the lower the defect density of the epitaxial layer grown on the template, allowing a thicker epitaxial layer to grow. In some embodiments, the thickness of the substantially single crystal layer 122 can be increased by epitaxially growing silicon on the release silicon layer.

  [0065] Third, it may be beneficial to improve the smoothness of the substantially single crystal layer 122. The smoothness of the layer can be related to the total hydrogen dose, the presence of any co-implanted species, and the annealing conditions used to form the hydrogen-based cleavage plane. As described below, the initial roughness resulting from layer transfer (ie, the cleavage step) can be reduced by thermal oxidation and oxide stripping.

  [0066] In some embodiments, removing the damaged layer and adjusting the final thickness of the substantially single crystal layer 122 includes thermal oxidation of the top of the release silicon layer followed by oxide with hydrofluoric acid (HF) acid. It can be achieved by delamination. For example, a release silicon layer having an initial thickness of 0.5 μm can be thermally oxidized to form a silicon dioxide layer having a thickness of about 420 nm. After removing the grown thermal oxide, the remaining silicon thickness in the transfer layer can be about 53 nm. During thermal oxidation, the injected hydrogen can move toward the surface. Thus, subsequent oxide layer stripping can remove some damage. Thermal oxidation is typically performed at a temperature of 1000 ° C. or higher. High temperatures can also repair lattice damage.

[0067] The silicon oxide layer formed on top of the substantially single crystal layer during thermal oxidation can be stripped using HF acid etching. The etch selectivity between silicon oxide and silicon (SiO ₂ : Si) with HF acid can be adjusted by adjusting the temperature and concentration of the HF solution and the stoichiometry and density of the silicon oxide. Etch selectivity refers to the etch rate of one material relative to another. The selectivity of the HF solution can range from about 10: 1 to about 100: 1 with respect to (SiO ₂ : Si). High etch selectivity can reduce the surface roughness by a similar factor from the initial surface roughness. However, the surface roughness of the resulting substantially single crystal layer 122 may still be greater than desired. For example, the bulk Si (111) surface has a root mean square (RMS) surface roughness of less than 0.1 nm, as determined by a 2 μm × 2 μm atomic force microscope (AFM) scan prior to additional processing. Can do. In some embodiments, the desired surface roughness for epitaxial growth of gallium nitride material on Si (111) is, for example, less than 1 nm, less than 0.5 nm, or 0 on a 30 μm × 30 μm AFM scan region. Can be less than 2 nm.

  [0068] If the surface roughness of the substantially single crystal layer 122 after thermal oxidation and oxide layer stripping exceeds the desired surface roughness, additional surface smoothing can be performed. There are several ways to smooth the silicon surface. These methods can include hydrogen annealing, laser trimming, plasma smoothing, and touch polishing (eg, chemical mechanical polishing or CMP). These methods may include preferential attack of high aspect ratio surface peaks. Thus, high aspect ratio features on the surface can be removed more quickly than low aspect ratio features, thus resulting in a smoother surface.

  [0069] It should be understood that the specific steps shown in FIG. 5 provide a specific method of manufacturing a designed substrate according to one embodiment of the present invention. According to another embodiment, another series of steps can be performed. For example, alternative embodiments of the present invention can perform the steps outlined above in a different order. Further, the individual steps shown in FIG. 5 may include multiple sub-steps that may be performed in various orders as appropriate for the individual steps. Furthermore, additional steps can be added or deleted depending on the particular application. Those skilled in the art will recognize many variations, modifications, and alternatives.

  [0070] FIG. 6 is a simplified schematic diagram illustrating an epitaxial / designed substrate structure for RF and power applications according to an embodiment of the present invention. In some LED applications, the designed substrate structure provides a growth substrate that allows growth of a high quality GaN layer, which is then removed. However, for RF and power device applications, the designed substrate structure forms part of the completed device, so that the electrical, thermal, and design of the designed substrate structure or elements of the designed substrate structure, and Other properties are important for specific applications.

[0071] Referring to FIG. 1, single crystal silicon layer 122 is a release layer that is typically separated from a silicon donor wafer using implantation and release techniques. Typical implants are hydrogen and boron. For power and RF device applications, the electrical properties of the layers and materials in the designed substrate structure are important. For example, some device architectures utilize a highly insulating silicon layer having a resistance greater than 10 ³ Ωcm to reduce or eliminate leakage through the substrate and interface layers. Other applications have utilized designs that include a conductive silicon layer of a predetermined thickness (eg, 1 μm) to connect the source of the device to other elements. Therefore, in these applications it is desirable to control the dimensions and properties of the single crystal silicon layer. In designs where implantation and stripping techniques are used during layer transfer, residual implanted atoms, such as hydrogen or boron, are present in the silicon layer, thereby changing the electrical properties. In addition, for example, adjustments in implant depth, which may affect conductivity and implantation profile, surface roughness and cleaved position accuracy, which may affect the full width at half maximum (FWHM) of the implant profile, and may affect the layer thickness. In use, it may be difficult to control the thickness, conductivity, and other properties of the thin silicon layer.

  [0072] According to embodiments of the present invention, silicon epitaxy on a designed substrate structure is utilized to achieve the desired properties of a single crystal silicon layer suitable for a particular device design.

  [0073] Referring to FIG. 6, an epitaxial / designed substrate structure 600 includes a designed substrate structure 610 and a silicon epitaxial layer 620 formed thereon. The designed substrate structure 610 may be similar to the designed substrate structure shown in FIGS. Typically, the substantially single crystal silicon layer 122 is about 0.5 μm after layer transfer. Using a surface conditioning process, the thickness of the single crystal silicon layer 122 can be reduced to about 0.3 μm in some processes. In order to increase the thickness of the single crystal silicon layer to about 1 μm for use in forming a reliable ohmic contact, for example, a substantial amount formed by a layer transfer process using an epitaxial process. An epitaxial single crystal silicon layer 620 is grown on the single crystal silicon layer 122. Various epitaxial growth processes including CVD, ALD, MBE, etc. can be used to grow the epitaxial single crystal silicon layer 620. The thickness of the epitaxial single crystal silicon layer 620 can range from about 0.1 μm to about 20 μm, such as between 0.1 μm and 10 μm.

  [0074] FIG. 7 is a simplified schematic diagram illustrating a III-V epitaxial layer on a designed substrate structure according to one embodiment of the invention. The structure shown in FIG. 7 can be called a double epitaxial structure, as will be described below. As shown in FIG. 7, a designed substrate structure 710 that includes an epitaxial single crystal silicon layer 620 has a III-V group epitaxial layer 720 formed thereon. In one embodiment, the III-V epitaxial layer includes gallium nitride (GaN).

  [0075] The desired thickness of the III-V epitaxial layer 720 may vary substantially depending on the desired function. In some embodiments, the thickness of the III-V epitaxial layer 720 can vary between 0.5 μm and 100 μm, for example, greater than 5 μm. The resulting breakdown voltage of the device fabricated on the III-V epitaxial layer 720 can vary depending on the thickness of the III-V epitaxial layer 720. Some embodiments provide a breakdown voltage of at least 100V, 300V, 600V, 1.2 kV, 1.7 kV, 3.3 kV, 5.5 kV, 13 kV, or 20 kV.

  [0076] A set of vias 724 are formed to provide electrical conductivity between portions of the III-V epitaxial layer 720 that may include multiple sublayers, in this example the III-V epitaxial layer 720. Passes from the upper surface of the epitaxial layer to the epitaxial single crystal silicon layer 620. Vias 724 can be aligned with an insulating layer (not shown) such that they are insulated from III-V epitaxial layer 720. As an example, these vias are used to connect a diode or transistor electrode to an underlying silicon layer by providing an ohmic contact through the via, thereby mitigating the charge stored in the device. be able to.

  [0077] When the III-V epitaxial layer is grown on the single crystal silicon layer 122, the via etching in the single crystal silicon layer 122 is terminated, for example, etching is performed to 5 μm of GaN, and the entire wafer is surely reduced to 0. Since it is difficult to terminate etching with a 3 μm silicon layer, it is difficult to form such an ohmic contact through a via. Utilizing embodiments of the present invention, it is possible to provide a single crystal silicon layer that is several microns thick, which requires high implantation energy to achieve large implantation depths. And the stripping process is difficult to use. Instead, the thick silicon layer allows applications such as the illustrated vias that allow various device designs.

  [0078] In addition to increasing the thickness of the silicon "layer" by epitaxially growing the single crystal silicon layer 620 on the single crystal silicon layer 122, other adjustments including modifications to conductivity, crystallinity, etc. This can be done with respect to the original characteristics of the single crystal silicon layer 122. For example, if a silicon layer on the order of 10 μm is desired before additional epitaxial growth of III-V layers or other materials, such thick layers can be grown according to embodiments of the present invention.

  [0079] The implantation process can affect the properties of the single crystal silicon layer 122, for example, residual boron / hydrogen atoms can affect the electrical properties of silicon, so embodiments of the invention Removes part of the single crystal silicon layer 122 before epitaxial growth of the single crystal silicon layer 620. For example, the single crystal silicon layer 122 can be thinned to form a layer having a thickness of 0.1 μm or less, and most or all of the residual boron / hydrogen atoms can be removed. Subsequent growth of the single crystal silicon layer 620 provides a single crystal material having electrical and / or other characteristics substantially independent of the corresponding characteristics of the layer formed using the layer transfer process. Used for.

  [0080] In addition to increasing the thickness of the single crystal silicon material coupled to the designed substrate structure, the electrical properties, including the conductivity of the epitaxial single crystal silicon layer 620, include that of the single crystal silicon layer 122. Can be different. Doping of the growing epitaxial single crystal silicon layer 620 can produce p-type silicon by doping boron and n-type silicon by doping phosphorus. Undoped silicon can be grown to provide high resistance silicon for use in devices having an insulating region. Insulating layers can be particularly useful in RF devices.

  [0081] The lattice constant of the epitaxial single crystal silicon layer 620 can be adjusted to be different from the lattice constant of the single crystal silicon layer 122 during growth to produce a strained epitaxial material. In addition to silicon, other elements can be epitaxially grown to provide a layer including a strained layer, a layer including silicon germanium, and the like. For example, a buffer layer can be grown on the single crystal silicon layer 122, the epitaxial single crystal silicon layer 620, or between layers to enhance subsequent epitaxial growth. These buffer layers may include strained III-V layers, silicon germanium strained layers, and the like. Further, the buffer layer and other epitaxial layers can be varied in mole fraction, dopant, polarity, and the like. Those skilled in the art will recognize many variations, modifications, and alternatives.

  [0082] In some embodiments, strain present in the single crystal silicon layer 122 or the epitaxial single crystal silicon layer 620 can be relaxed during the growth of subsequent epitaxial layers including III-V epitaxial layers.

  [0083] FIG. 8 is a simplified flowchart illustrating a method of manufacturing a designed substrate according to another embodiment of the present invention. The method includes forming a support structure by providing a polycrystalline ceramic core (810) and forming a first adhesive layer coupled to at least a portion of the polycrystalline ceramic core (812). The first adhesive layer can include a tetraethylorthosilicate (TEOS) layer. The method also includes forming a conductive layer coupled to the first adhesive layer (814). The conductive layer can be a polysilicon layer. The first adhesive layer can be formed as a single layer of TEOS. The conductive layer can be formed as a single layer of polysilicon.

  [0084] The method also includes forming a second adhesion layer coupled to at least a portion of the conductive layer (816) and forming a barrier shell (818). The second adhesive layer can be formed as a single layer of TEOS. The barrier shell can be formed as a single layer of silicon nitride or as a series of sublayers that form the barrier shell.

  [0085] Once the support structure is formed by processes 810-818, the method may include bonding a bonding layer (eg, a silicon oxide layer) to the support structure (820), a substantially monocrystalline silicon layer, or a substantially single crystal layer. Bonding the crystalline layer to the silicon oxide layer (822). Bonding the bonding layer can include deposition of a bonding material followed by a planarization process as described herein.

  [0086] A substantially single crystal silicon layer 122 can be bonded to the bonding layer 120 using a layer transfer process. In some embodiments, a silicon wafer (eg, a silicon (111) wafer) is implanted to form a cleavage plane. After the wafer bonding, the silicon substrate can be removed together with a part of the single crystal silicon layer under the cleavage plane, and as a result, the peeled single crystal silicon layer 122 shown in FIG. 1 is obtained. The thickness of the substantially single crystal silicon layer 122 can be varied to meet various application specifications. Further, the crystal orientation of the substantially single crystal layer 122 can be varied to meet the application specifications. Further, the doping level and profile in the substantially single crystal layer 122 can be varied to meet the specifications of a particular application. In some embodiments, the substantially single crystal silicon layer 122 can be smoothed as described above.

  [0087] The method shown in FIG. 8 also forms an epitaxial silicon layer by epitaxial growth on the substantially monocrystalline silicon layer (824) and an epitaxial III-V layer by epitaxial growth on the epitaxial silicon layer (826). Forming. In some embodiments, the epitaxial III-V layer can include gallium nitride (GaN).

  [0088] It should be understood that the specific steps shown in FIG. 8 provide a specific method of manufacturing a designed substrate according to another embodiment of the present invention. According to another embodiment, another series of steps can be performed. For example, alternative embodiments of the present invention can perform the steps outlined above in a different order. Further, the individual steps shown in FIG. 8 may include multiple sub-steps that may be performed in various orders as appropriate for the individual steps. Furthermore, additional steps can be added or deleted depending on the particular application. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0089] Also, the examples and embodiments described herein are for illustrative purposes only, and various modifications or changes in light of this will be suggested to those skilled in the art and within the spirit and scope of this application. And within the scope of the appended claims.

Claims (40)

A support structure,
A polycrystalline ceramic core;
A first adhesive layer bonded to the polycrystalline ceramic core;
A conductive layer coupled to the first adhesive layer;
A second adhesive layer bonded to the conductive layer;
A support structure comprising: a barrier layer bonded to the second adhesive layer;
A silicon oxide layer bonded to the support structure;
A substantially single crystal silicon layer bonded to the silicon oxide layer;
A substrate comprising: an epitaxial III-V layer coupled to the substantially single crystal silicon layer.   The substrate of claim 1, wherein the polycrystalline ceramic core comprises aluminum nitride.   The substrate of claim 2, wherein the epitaxial III-V layer comprises an epitaxial gallium nitride layer.   The substrate of claim 3, wherein the epitaxial gallium nitride layer has a thickness of about 5 μm or more.   The substrate of claim 1, wherein the substantially single crystal silicon layer comprises a release silicon layer having a thickness of about 0.5 μm.   The substantially single crystal silicon layer includes a release silicon layer and an epitaxial silicon layer grown on the release silicon layer, wherein the substantially single crystal silicon layer has a thickness of about 0.5 μm. The substrate described in 1. The first adhesive layer includes a first tetraethylorthosilicate (TEOS) layer encapsulating the polycrystalline ceramic core;
The conductive layer includes a polysilicon layer that encapsulates the first TEOS layer;
The second adhesive layer includes a second TEOS layer encapsulating the polysilicon layer;
The substrate according to claim 2, wherein the barrier layer includes a silicon nitride layer that encapsulates the second TEOS layer. The first TEOS layer has a thickness of about 1000 mm;
The polysilicon layer has a thickness of about 3000 mm;
The second TEOS layer has a thickness of about 1000 mm;
The substrate of claim 7, wherein the silicon nitride layer has a thickness of about 4000 mm. A method of manufacturing a substrate, the method comprising:
Providing a polycrystalline ceramic core,
Encapsulating the polycrystalline ceramic core in a first adhesive shell;
Encapsulating the first adhesive shell in a conductive shell;
Encapsulating the conductive shell in a second adhesive shell;
Forming a support structure by encapsulating the second adhesive shell in a barrier shell;
Bonding a bonding layer to the support structure;
Bonding a substantially single crystal silicon layer to the bonding layer;
Forming an epitaxial silicon layer on the substantially monocrystalline silicon layer by epitaxial growth;
Forming an epitaxial III-V layer on the epitaxial silicon layer by epitaxial growth;
Including a method.   The method of claim 9, further comprising forming a plurality of vias that pass from the epitaxial III-V layer to the epitaxial silicon layer.   The method of claim 9, wherein the epitaxial III-V layer comprises gallium nitride. The first adhesive shell comprises a tetraethylorthosilicate (TEOS) shell;
The conductive shell includes a polysilicon shell;
The second adhesive shell comprises a second TEOS shell;
The barrier shell includes a silicon nitride shell;
The method of claim 9, wherein the bonding layer comprises silicon oxide. The first TEOS shell includes a single layer of TEOS;
The polysilicon layer comprises a single layer of polysilicon;
The second TEOS shell comprises a single layer of TEOS;
The method of claim 12, wherein the silicon nitride shell comprises a single layer of silicon nitride. A support structure,
A polycrystalline ceramic core;
A first adhesive layer bonded to the polycrystalline ceramic core;
A conductive layer coupled to the first adhesive layer;
A second adhesive layer bonded to the conductive layer;
A support structure comprising: a barrier shell coupled to the second adhesive layer;
A bonding layer coupled to the support structure;
A substantially single crystal silicon layer bonded to the bonding layer;
A designed substrate structure comprising: an epitaxial single crystal silicon layer coupled to the substantially single crystal silicon layer. The polycrystalline ceramic core comprises polycrystalline gallium nitride;
The first adhesive layer comprises tetraethylorthosilicate (TEOS);
The conductive layer comprises polysilicon;
The second adhesive layer comprises TEOS;
The barrier shell comprises silicon nitride;
The designed substrate structure of claim 14, wherein the bonding layer comprises silicon oxide.   The designed substrate structure of claim 14, further comprising an epitaxial III-V layer coupled to the epitaxial single crystal silicon layer.   The designed substrate structure of claim 16, further comprising a plurality of vias passing from the epitaxial III-V layer to the epitaxial single crystal silicon layer.   15. The designed substrate structure of claim 14, further comprising one or more buffer layers disposed between the substantially single crystal silicon layer and the epitaxial single crystal silicon layer.   The designed substrate structure of claim 14, wherein the epitaxial single crystal silicon layer is distorted.   15. The designed substrate structure according to claim 14, wherein the epitaxial single crystal silicon layer has a thickness in the range of 1 [mu] m to 20 [mu] m. A polycrystalline ceramic core;
A first adhesive layer encapsulating the polycrystalline ceramic core;
A conductive layer enclosing the first adhesive layer;
A second adhesive layer encapsulating the conductive layer;
A barrier layer encapsulating the second adhesive layer;
A bonding layer bonded to the barrier layer;
And a substantially single crystal silicon layer bonded to the bonding layer.   The substrate of claim 21, wherein the polycrystalline ceramic core comprises polycrystalline aluminum nitride.   The substrate of claim 21, wherein the first adhesion layer comprises tetraethylorthosilicate (TEOS).   The substrate of claim 21, wherein the first adhesive layer has a thickness of about 1000 mm.   The substrate of claim 21, wherein the conductive layer comprises polysilicon.   The substrate of claim 21, wherein the conductive layer has a thickness of about 3000 mm.   The substrate of claim 21, wherein the second adhesive layer comprises tetraethylorthosilicate (TEOS).   The substrate of claim 21, wherein the second adhesive layer has a thickness of about 1000 mm.   The substrate of claim 21, wherein the barrier layer comprises silicon nitride.   The substrate of claim 21, wherein the barrier layer has a thickness of about 4000 mm.   The substrate of claim 21, wherein the substantially single crystal silicon layer comprises a release silicon layer.   The substrate of claim 21, wherein the substantially single crystal silicon layer has a thickness of about 0.5 μm. A method of manufacturing a substrate, the method comprising:
Preparing a polycrystalline ceramic core;
Encapsulating the polycrystalline ceramic core in a first adhesive shell;
Encapsulating the first adhesive shell in a conductive shell;
Encapsulating the conductive shell in a second adhesive shell;
Encapsulating the second adhesive shell in a barrier shell;
Bonding a bonding layer to the barrier shell;
Bonding a single crystal silicon layer to the bonding layer.   34. The method of claim 33, wherein the polycrystalline ceramic core comprises polycrystalline aluminum nitride.   34. The method of claim 33, wherein the first adhesive shell comprises tetraethylorthosilicate (TEOS).   34. The method of claim 33, wherein the conductive shell comprises polysilicon.   34. The method of claim 33, wherein the second adhesive shell comprises tetraethylorthosilicate (TEOS).   34. The method of claim 33, wherein the barrier shell comprises silicon nitride.   34. The method of claim 33, wherein bonding the single crystal silicon layer comprises performing a layer transfer process from a silicon-on-insulator wafer. 40. The method of claim 39, further comprising smoothing the substantially single crystal silicon layer.