TWI737852B - 以催化積層或黏著劑整合積體電路晶圓 - Google Patents

以催化積層或黏著劑整合積體電路晶圓 Download PDF

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TWI737852B
TWI737852B TW106139012A TW106139012A TWI737852B TW I737852 B TWI737852 B TW I737852B TW 106139012 A TW106139012 A TW 106139012A TW 106139012 A TW106139012 A TW 106139012A TW I737852 B TWI737852 B TW I737852B
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Taiwan
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catalytic
integrated circuit
layer
particles
resin
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TW106139012A
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TW201830528A (zh
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康斯坦丁 卡拉瓦基斯
肯尼斯Ｓ 巴爾
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美商凱特聯有限責任公司
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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Abstract

催化積層是由樹脂、纖維強化層以及催化顆粒所形成，使得催化顆粒配置成遍及催化積層，但排除催化積層的外表面。催化積層具有跡線通道和通孔，其形成以製作單一或多層催化積層的印刷電路板(PCB)。位置匹配積體電路襯墊位置的孔洞則形成於積層PCB中。積體電路接合到催化積層PCB，並且積體電路和積層都受到無電鍍，藉此將積體電路電連接到單一或多層催化積層PCB。

Description

以催化積層或黏著劑整合積體電路晶圓
本發明關於積體電路(integrated circuit，IC)封裝和積體電路對基板的附接。尤其，本發明關於積體電路晶片或晶粒對催化積層基板或催化黏著劑的電接合以形成裝置組件。
電子電路的基礎考量是電路元件的互連。典型的先前技藝互連科技是印刷電路板(printed circuit board，PCB)，其中導電跡線印刷在積層上，並且各種構件安裝在PCB上以提供電互連。一個基礎考量是：雖然新世代的積體電路持續出現愈來愈精細的製造線寬(目前是在50奈米的等級)，不過印刷電路板線寬已維持在5密耳間隔(~125微米)的等級，要比積體電路線寬粗2,500倍。據此，晶片設計實務持續使晶片的複雜度和功能性達到最大，並且使離開晶片的輸入/輸出(I/O)線數目達到最小。對於具有大量I/O連接的晶片設計來說，將晶片I/O針腳調適於PCB仍是未解的問題，因為晶片特色尺寸持續收縮而PCB線寬已維持不變。
圖1A顯示球柵陣列(ball grid array，BGA)封裝101的側視圖，其已經焊於印刷電路板102，該板具有一系列襯墊，其電連接到BGA封裝101的球114。BGA封裝101包括晶片104，其安裝於基板112，而印刷的打線接合襯墊110在頂部上、對BGA襯墊115的電跡線在底下。單獨的導線108例如藉由超音波焊接而從積體電路104的襯墊106接合到基板112的接合襯墊110。晶片104可以使用 黏著劑或其他技術而機械附接於基板112，讓襯墊106可從頂部來存取，如所示。在晶片104的襯墊和基板112的襯墊110之間做互連導線108的打線接合之後，施加例如環氧樹脂的密封劑105以保護晶片的頂部。於次要作業，單獨的球114在每個附接點115附接於基板112的底部襯墊，如此則在後續作業期間，它們在升高溫度下回焊以形成對電路板102的電連接。基板112可以是習用的印刷電路板，其遵循典型的5密耳(~125微米)寬的PCB線寬和5密耳(~125微米)的邊緣間隔，而使用印刷的銅跡線來形成，其在跡線上閃鍍(flash)或別種薄鍍覆了鎳以使材料相容於晶粒接合導線108，後者可以是鋁、金、銀或銅。於先前技藝的積體電路，單獨的裝置藉由圖案化的局部離子植入而形成到例如矽(Si)的晶片基板裡，以此達成摻雜而形成半導體裝置，並且半導體裝置使用一系列金屬性互連(金屬化層)而互連，該互連是由鋁或銅所形成，以及可選用的中介性絕緣或阻障層。晶片互連觸墊(或襯墊)典型而言使用相同於金屬化層的的材料來提供，低複雜度/密度的晶片經常使用鋁，而高複雜度/密度的晶片經常使用銅。
圖1B顯示圖1A的俯視圖，其結構使用圖1A的參考數字來辨識，就如本申請案全篇也這樣做。
圖1A的先前技藝系統受限於PCB線寬，其顯著粗於晶片線寬。附帶而言，圖1A的打線接合方法從晶片104導入了不想要的引線電感到PCB 102，這限制了所得電路的高頻訊號傳播能力。雖然使用參考接地平面則有可能維持印刷電路板跡線的高頻傳輸線特徵，但不可能提供此種連續阻抗或連續接地參考給例如108的接合導線，其也感應耦合於其他接合導線，尤其隨著傳遞到傳輸線的切換頻率增加更是如此。
PCB科技的一個考量是可製造性和可服務性，包括如果發現裝置有缺陷則置換單獨裝置。於圖1A的BGA封裝科技，當晶片是有缺陷時，局部化的熱可以施加到101 BGA晶片組件，直到電路基板112和PCB 102之間的BGA球 熔化為止，之後則移除BGA晶片組件101，並且可以安裝置換的BGA晶片組件101。附帶而言，對於高價值BGA組件101來說，有可能使用局部加熱和助焊劑而重新球化(安裝新的焊球114)和重新附接BGA封裝101到PCB 102，直到球114熔化(回焊)到相鄰之上和下表面上的襯墊上為止。
為了解決BGA封裝的低封裝密度和引線電感，圖2A所示的「覆晶」(flip chip)封裝法併入了翻轉的晶片基板202，而讓晶片電路和觸墊面朝下；相較來看，圖1A之BGA晶片封裝的晶片觸墊指向是面朝上。於覆晶做法，晶片202具有互連觸墊，其形成在底表面上(典型而言在銅中)，以及具有絕緣遮罩層204，其避免焊球208遷移並且使相鄰的互連層電隔離。覆晶互連涉及比較高的工具化成本和設備成本，所以通常用於高體積和高密度的封裝方法，例如消費性行動電話。圖2B顯示覆晶的仰視圖以與圖2A的側視圖做比較。
先前技藝的一個問題是：BGA晶片接合導入了引線電感，這以覆晶法所解決，代價是高工具化成本以及難以重製或移除覆晶裝置。先前技藝封裝的另一問題是：可能會需要將幾個晶片和電路整合到PCB上以用於代理商所管制的的組件，其中晶片模組是由管制代理商所檢視和認證。此種代理商所管制的組件範例包括藍牙(Bluetooth®)或802.11無線區域網路(wireless local area network，WLAN)模組，其中管制代理商以公告的標準來檢視模組的射頻(RF)發射，並且證明模組符合該發射標準。使用這形式的預先認證模組則允許模組的使用者改變他們的互連PCB設計而不需重新認證；如果預先認證模組中的先前認證設計併入其PCB中，則會另外需要重新認證。
發明人已發現高密度封裝設備和方法，其提供要比先前技藝的PCB製造方法還精細幾倍的PCB線寬，而增加的工具化成本達到最小。據此，想要提供一種封裝方法，其能夠將積體電路晶片直接安裝到電路板或基板而用於低體積、對成本敏感的應用，並且其提供連續電連接而用於高速作業及改善訊 號完整性，但無先前技藝的感應性打線接合。
<發明目的>
本發明的第一目的是具有多個孔洞的催化基板，該催化基板具有非催化表面，並且在非催化表面下的排除深度則具有催化顆粒，使得移除表面材料(例如藉由蝕刻、擦刮、鑽鑿或其他移除手段來為之，而形成通道或孔洞)則活化(暴露)底下的催化顆粒，而催化顆粒所具有的密度足以支援無電鍍，孔洞則定位成相鄰於半導體晶片的引線附接，通道則相鄰於孔洞，使得在無電鍍期間，無電鍍的導電金屬沉積到暴露的催化顆粒、孔洞表面以及晶片觸墊附接上，藉此在晶片觸墊和基板通道與孔洞之間提供電連接性。
本發明的第二目的是在半導體晶片和基板之間提供電連接性的方法，該方法可操作在半導體晶片和催化基板上，該半導體晶片具有電附接襯墊，並且催化基板具有催化核心，該催化核心提供足夠的催化劑密度以使導電金屬無電鍍到通道和孔洞上，該等通道和孔洞已使用任何表面材料移除方法(包括機械或化學方法)而形成到催化基板裡；除非已移除表面，否則催化基板不暴露催化顆粒；該方法包括：將孔洞和可選用的跡線通道形成到催化積層裡，其深度足以暴露催化顆粒；將具有電觸墊的半導體晶片定位成對齊於催化積層中所形成的孔洞；將半導體晶片和基板浸沒到無電鍍溶液裡，直到無電鍍的導電材料沉積在半導體晶片引線附接和孔洞及可選用的互連通道之間為止。
<發明綜述>
半導體積體電路(IC)晶片具有引線附接觸墊(用於IC之電功能的輸入/輸出、電力以及接地襯墊)而定位到催化積層上，該催化積層具有催化顆粒，其分布穿過積層，但在表面上也具有排除區而沒有暴露的催化顆粒。催化 積層要求使用移除手段(例如化學或機械蝕刻、磨蝕或鑽鑿)來移除催化顆粒排除深度以下的表面材料以暴露底下的催化顆粒。移除表面材料則暴露催化顆粒，並且提供適合由溶液做導電材料(例如銅)之無電鍍的表面以形成導電跡線。孔洞例如藉由鑽孔或打孔而形成於催化積層中，該等孔洞對應於晶片觸墊，而可選用的跡線通道也可形成於催化基板中。其他的跡線通道、襯墊以及孔洞可以支撐催化基板上的其他構件、跡線、晶片，並且跡線通道可以形成在基板的一側或二側上。無電鍍步驟導致導電跡線僅形成在相鄰於孔洞的跡線通道、孔洞、晶片觸墊(電襯墊)，藉此專門在已移除催化積層表面的所選區域中形成導體跡線和附接。
於本發明的另一範例，半導體晶片具有用於電附接的觸墊，該半導體晶片在具有觸墊的表面上披覆了催化黏著劑，該催化黏著劑後續在足以讓樹脂中的催化顆粒在表面下移動的凝膠點、停留溫度、停留時間而固化，藉此生成的催化黏著劑在表面上沒有暴露的催化顆粒，而在催化黏著劑的排除深度以下則有催化顆粒。固化的黏著劑具有形成在表面上的通道，其在排除深度以下延伸，並且也具有形成的孔洞，其延伸到觸墊的深度。於後續的無電鍍銅沉積步驟，銅沉積於具有暴露之催化顆粒的區域，例如孔洞壁和通道壁，並且沉積到觸墊上，而提供催化顆粒或銅鍍覆，這任一者將在無電鍍銅沉積期間形成導電連接。
101‧‧‧球柵陣列(BGA)封裝
102‧‧‧印刷電路板(PCB)
104‧‧‧晶片
105‧‧‧密封劑
106‧‧‧晶片襯墊
108‧‧‧導線
110‧‧‧打線接合襯墊
112‧‧‧基板
114‧‧‧球
115‧‧‧BGA襯墊
202‧‧‧翻轉的晶片基板
204‧‧‧絕緣遮罩層
208‧‧‧焊球
302‧‧‧晶片
304‧‧‧細節A
306‧‧‧基板、催化積層
310‧‧‧BGA球
312‧‧‧電路板
322‧‧‧通道
324‧‧‧孔洞
326‧‧‧晶片附接襯墊、晶片觸墊
402~410‧‧‧對基板通道和晶片觸墊進行電連接的範例性製程步驟
502‧‧‧多層板
512‧‧‧孔洞
514‧‧‧外無電鍍覆
516‧‧‧通孔
602‧‧‧電附接觸墊
603‧‧‧通道
604‧‧‧積體電路(IC)、晶粒
606‧‧‧催化黏著劑
607‧‧‧孔洞
608‧‧‧引線附接、通道
610‧‧‧導電材料、銅填充通道
612‧‧‧球
614‧‧‧遮罩層
620‧‧‧印刷電路板
702~712‧‧‧提供圖6A到6E之裝置的製程
802‧‧‧織布
803‧‧‧烘烤爐
804‧‧‧滾筒
805‧‧‧A階段預浸體
806‧‧‧催化樹脂混合物(浴液)
807‧‧‧B階段預浸體
808‧‧‧貯槽
810、811‧‧‧滾筒
814‧‧‧C階段預浸片
824‧‧‧腔室
826‧‧‧積層加壓機
828‧‧‧真空泵
830‧‧‧催化樹脂浸漬織布
902‧‧‧溫度對時間圖
904‧‧‧溫度上升時間
905‧‧‧預浸體凝膠點
906‧‧‧停留時間
908‧‧‧冷卻周期
1002~1010‧‧‧製作具有浸漬催化顆粒之預浸體積層的製程
1102‧‧‧催化預浸體
1104‧‧‧第一表面
1106‧‧‧第二表面
1108、1110‧‧‧邊界區域
1114‧‧‧催化顆粒
圖1A是焊於電路板之先前技藝BGA封裝的側視圖。
圖1B是圖1A之先前技藝BGA封裝的俯視圖。
圖2A是焊於電路板之先前技藝覆晶的側視圖。
圖2B是具有BGA球之先前技藝覆晶的仰視圖。
圖3顯示根據本發明一態樣而附接於基板之晶片的側視圖，其附 接於印刷電路板。
圖3A顯示圖3在接合製程之第一步驟的詳細側視圖。
圖3B顯示圖3A在後續處理步驟之後的側視圖。
圖4顯示具有製程步驟的流程圖。
圖5顯示接合到晶片的多層催化積層板。
圖6A、6B、6C顯示在應用一定製程步驟之後的積體電路之仰視圖。
圖6A-1、6B-1、6C-1分別顯示圖6A、6B、6C的側視圖。
圖6D和6E顯示在製程接續步驟之後的積體電路之側視圖。
圖7顯示製程步驟的流程圖。
圖8A顯示形成催化預浸體的製程。
圖8B和8C顯示用於形成催化預浸體的積層加壓機。
圖9是形成催化積層的時間和溫度圖，其排除了在表面和下面之排除區中的催化顆粒。
圖10是形成催化預浸體的流程圖。
圖11顯示催化積層的側視截面圖，而對應的圖則顯示穿過截面之催化顆粒的密度。
圖3顯示晶圓層級封裝之範例的側視圖解，其中晶片302附接於基板306，該基板具有範例性電跡線(以粗體顯示)，其從晶片302的互連襯墊連到焊於電路板312的BGA球310。有許多方式來完成本發明的引線附接，並且圖3顯示的僅在示範一具體態樣。細節A 304包括有興趣的區域，其顯示在圖3A和3B所示的附接步驟之後便從晶片302附接到基板306。
圖3A顯示催化基板306和晶片302的細節圖，而晶片附接襯墊326 形成在晶片302上以供電連接。晶片觸墊326典型而言在晶片302之製程中的最後金屬化步驟期間形成，該等引線附接襯墊的厚度為了清楚而垂直放大許多以區分IC 302的引線附接觸墊326。基板306採取幾種不同方式中的一種而由催化積層所形成，但製作基板之多樣形式的共同特徵是：基板是由催化顆粒、樹脂、織造或非織造的織布黏結劑(例如玻璃纖維)之混合物所形成的催化積層，其中催化積層所具有的性質是催化顆粒分散遍及積層，但具有當中不存在催化顆粒的表面排除深度。於本發明的一個範例，催化顆粒的最長尺度小於25微米，並且催化顆粒的表面排除深度近似於催化顆粒最長尺度之最大尺度的一半。圖3A顯示催化積層306，其沒有暴露的表面催化顆粒，但在表面已移除到排除深度下面的區域，例如通道322和孔洞324，則在這些區域暴露出催化顆粒。孔洞324定位成對應於晶片附接觸墊326，並且晶片302固定於基板306而讓襯墊326和孔洞324彼此對齊。
圖3B顯示在無電沉積步驟之後的基板306和晶片302觸墊326，該步驟沉積導電金屬於跡線通道322、孔洞324壁、襯墊326，藉此形成導電跡線和對晶片302之襯墊326的附接。於本發明的另一範例，BGA球在無電鍍之後可以定位在孔洞324底下，而有或沒有通道322或連帶的通道跡線。
圖4顯示對基板通道和晶片觸墊進行電連接的範例性製程步驟。步驟402關於形成催化基板，其描述於2016年8月18日申請的美國專利申請案第15/240,133號，其併於此以為參考。步驟402的催化基板包括可變厚度的基板，其可以具有一或更多層的織造纖維(例如玻璃纖維)而提供機械強度和可撓性，玻璃纖維則浸漬了催化樹脂，該樹脂則由混合了最長尺度小於25微米、平均催化顆粒間隔是在催化顆粒最大長度的等級(舉例而言為25微米或更小)之催化顆粒的樹脂所形成。形成催化基板的製程包括將壓力和溫度維持在催化積層之凝膠點(而固態和液態樹脂平衡達凝膠點持續時間)的製程步驟，而足以讓催化顆粒從 催化積層的外表面遷移離開，如此則不需要表面遮罩來避免無電鍍於尚未移除的原生表面區域。以這方式，則催化積層的外表面沒有暴露的催化顆粒，並且催化積層的外表面必須移除(至少達到近似1/2催化顆粒尺度之催化排除區的深度)，以便讓催化積層能夠做無電沉積。
製程步驟404提供在催化積層中形成圖3A的孔洞324。步驟406是可選用的步驟，其將跡線通道(例如圖3A的通道322)形成到催化積層裡。在附接孔洞和跡線通道形成於催化積層之後，晶片於步驟408定位在催化積層的表面上，而使晶片襯墊對齊於催化積層中的孔洞。跡線通道可以形成於催化積層306的頂面或底面，然而跡線經常不定位於直接在晶片302和基板306之間的區域，因為晶片302會抑制被相鄰於任何基板302通道(在其底下)的晶片所隱藏之通道的無電沉積。於步驟410，晶片302和基板306定位在一起，可選用而言乃彼此接合，並且放入無電鍍槽裡，而形成的導體沉積到跡線通道、孔洞、晶片襯墊。
圖5顯示本發明的另一具體態樣，其中具有催化積層的多層板502接合到晶片302的襯墊326。多層板502在接合作業之前可以用許多不同的方式來製造，舉例而言PCB 502可以由一系列催化積層所形成，每一者受到無電鍍，例如2016年8月18日申請之美國專利申請案第15/240,133號所述的幾種製造多層板之技術中的任一種。於最後步驟，通孔516和孔洞512可以鑽鑿穿過板，而晶片302如先前所述的附接，並且進行最後的無電鍍步驟，而提供外無電鍍覆514，其將襯墊326電連接到多層電路板502，並且也提供PCB 502的外跡線層。
圖6A顯示積體電路604的仰視圖，其具有形成在外金屬化層上的電附接觸墊602。積體電路604典型而言包括單獨的電晶體和其他單獨的裝置，其藉由半導體材料的摻雜來形成裝置，而單獨的裝置藉由交替的金屬化層和絕緣層所互連。金屬化層和裝置經由一系列的圖案化步驟而形成，摻雜步驟則是以離子植入來進行，並且金屬化層是以導電材料(例如鋁或金)的圖案化氣相沉積 所形成。於另一範例，積體電路604是半導體裝置，例如高功率的場效電晶體(field effect transistor，FET)，或是在相對為大的晶粒604上具有少量電觸墊602的其他裝置。積體電路觸墊602典型而言形成在金屬化的最後外層上。觸墊金屬化的材料典型而言相同於內金屬化層，例如鋁(Al)，或在某些情形下為金(Au)。圖6A-1顯示圖6A之積體電路604的側視圖。
於本發明的一個範例，積體電路觸墊602閃鍍了例如鎳的過渡材料，其中散播了催化顆粒，或者催化顆粒是在鎳閃鍍步驟之後才添加，而提供用於後續無電鍍的支架，如所將描述。
圖6B顯示在催化黏著劑606材料已例如藉由滾軋、噴灑或任何其他施加方法而施加到積體電路604之後的仰視圖。催化黏著劑604包括催化顆粒和樹脂的混合物，而在凝膠溫度下固化所達到的持續時間足以使催化顆粒從排除區(例如離催化黏著劑的表面有12微米)撤出。於本發明的一個範例，表面排除區是催化顆粒之最長尺度的1/2，其小於25微米。在施加和固化催化黏著劑606之後，表面沒有催化顆粒，如先前針對催化積層所述，並且觸墊602隔離於催化黏著劑606底下，直到進行後續作業為止。
圖6C顯示後續步驟，其中形成了一系列深孔洞607(其穿過催化黏著劑606到積體電路604的觸墊602)以及一系列淺通道603和淺引線附接608。圖6C-1顯示圖6的放大側截面圖，其中顯示了積體電路604和催化黏著劑606，並且通道608和深孔洞607穿過催化黏著劑606的完整厚度而到積體電路604的觸墊602。在移除形成了通道608、襯墊、孔洞607的表面之前，催化黏著劑606的催化顆粒在表面底下維持著首先形成催化黏著劑之時的固化和烘烤製程所造成的排除區。由於通道603、引線608、孔洞602都延伸於稍早固化製程所形成的催化顆粒表面排除區底下，故通道和孔洞的內表面提供適合促進無電鍍的催化顆粒。如先前所述，積體電路觸墊602可以閃鍍了鎳、然後閃鍍了銅，或者觸墊602 可以披覆了催化材料，使得觸墊602以相同於催化黏著劑中之通道和孔洞的方式來吸引溶液中的銅離子。
圖6D顯示製程中的後續步驟，其中圖6C-1的裝置放入無電鍍浴液裡，並且例如銅的導電材料沉積610到通道608和孔洞607裡以形成互連導電跡線。
圖6E顯示二個可選用之最後的後處理步驟，其中可以添加遮罩層614來隔離銅填充通道610和可以靠近印刷電路板620的跡線。對於BGA安裝來說，球612可以定位在端子處以用於未來的表面裝焊作業。替代選擇而言，本發明可以實施成在表面層上沒有側向跡線，使得球612可以在無電鍍之後直接定位在孔洞607底下，而有或沒有互連跡線或通道608/610。
圖7顯示根據本發明而提供圖6到6E之裝置的流程圖。於步驟702和704，將IC或晶片的導電襯墊或觸墊加以鍍覆以提供對於無電鍍製程的相容性。舉例而言，如果最後的金屬化層和I/O、電力、接地觸墊是鋁，則一範例性沉積會是鎳閃鍍，其包括步驟704之暴露的催化顆粒。替代選擇而言，鎳鍍覆層或可施加於鋁金屬化觸墊上，並且催化顆粒形成無電鍍的位置，或者銅鍍覆層做連續的無電鍍(對於銅作為無電鍍材料的情況而言)。催化顆粒的處理或孔洞區域中的相容鍍覆層會透過無電鍍而提供令人滿意的連接性。步驟706關於形成孔洞(例如圖6C-1的607)和跡線通道(例如608)。步驟708提供無電鍍銅沉積而導致圖6D所示的跡線610，步驟710和712則提供圖6E之可選用的遮罩614和BGA球612。
本發明的催化積層和催化黏著劑可以採取幾種方式來形成。圖8A顯示製造預浸體(預先浸滲之纖維的基質而包含於樹脂中)的範例性製程。許多不同的材料可以用於預浸體的纖維，包括織造的玻璃纖維布、碳纖維或其他纖維；並且各式各樣不同的材料可以用於樹脂，包括環氧樹脂、聚亞醯胺樹脂、氰酸酯樹脂、聚四氟乙烯(PTFE)(鐵氟龍Teflon®)摻合樹脂或其他樹脂。本發明的 一態樣是印刷電路板積層，其能夠支援等級為1密耳(25微米)之精細間距的導電跡線；雖然本敘述針對使用無電鍍銅的催化劑來形成銅跡線，不過要了解本發明的範圍可以延伸到適合無電鍍和電鍍的其他金屬。對於無電沉積銅(Cu)通道來說，偏好元素態鈀(Pd)作為催化劑，雖然選擇週期表之過渡金屬元素的任一者都可以使用作為催化顆粒，例如9到11族的鉑(Pt)、銠(Rh)、銥(Ir)、鎳(Ni)、金(Au)、銀(Ag)、鈷(Co)、或銅(Cu)，或這些的其他化合物，包括其他金屬，例如鐵(Fe)、錳(Mn)、鉻(Cr)、鉬(Mo)、鎢(W)、鈦(Ti)、錫(Sn)、或以上的混合物或其鹽類。本候選條列打算是範例性的而非廣泛綜合的，此技藝也知道可以使用其他的催化劑來吸引銅離子。於本發明的一個範例，催化顆粒是均質的催化顆粒。於本發明的另一範例，催化顆粒是無機顆粒或抗高溫的塑膠顆粒，其披覆了幾埃(angstrom)厚度的催化金屬，藉此形成異質的催化顆粒，其具有包封非催化內顆粒的薄催化外表面。這配方對於較大的催化顆粒來說(例如最長尺度在25微米等級)可以是想要的。這配方的異質催化顆粒可以包括無機、有機或惰性填充物，例如二氧化矽(SiO2)、無機黏土(例如高嶺土)、或高溫塑性填充物，而表面上披覆了催化劑(例如鈀)，其例如藉由氣相沉積或化學沉積而吸附到填充物的表面上。催化顆粒僅需要幾個原子層的催化劑便具有助於無電鍍所想要的性質。
於形成異質催化顆粒的一範例，(有機或無機)填充物的浴液以尺寸來篩選，以包括尺寸小於25微米的顆粒；這些經篩選的無機顆粒混合到貯槽裡的水浴液、加以攪拌、然後引入鈀鹽(例如PdCl，或任何其他的催化劑，例如銀鹽或其他催化劑)以及酸(例如HCl)和還原劑(例如水合肼)，混合物藉此還原出金屬性Pd，其披覆無機顆粒而提供披覆在填充物上之幾埃厚度的Pd，藉此生成異質的催化顆粒，其具有均質Pd顆粒的催化性質，但相較於使用均質的Pd金屬性顆粒而言卻大大減少Pd的體積需求。然而，對於等級在幾個奈米的極小催化顆粒來說，可以偏好均質的催化顆粒(例如純的Pd)。
範例性無機填充物包括黏土礦物質，例如水合葉矽酸鋁，其可以包含可變量的鐵、鎂、鹼金屬、鹼土金屬和其他陽離子。這範例性無機填充物的家族包括二氧化矽、矽酸鋁、高嶺土(Al2Si2O5(OH)4)、聚矽酸鹽、或屬於高嶺土或瓷黏土家族的其他黏土礦物質。範例性有機填充物包括PTFE(Teflon)和抗高溫的其他聚合物。
鈀鹽的範例為：BrPd、CL2Pd、Pd(CN)2、I2Pd、Pd(NO3)2˙2H2O、Pd(NO3)2、PdSO4、Pd(NH3)4Br2、Pd(NH3)4Cl2H2O。本發明的催化粉末也可以包含以下的混合物：異質的催化顆粒(舉例而言，催化材料披覆在無機填充顆粒上)、均質的催化顆粒(例如元素態鈀)、非催化顆粒(選自無機填充物家族)。於本發明的一個範例，催化粉末的組成物是一摻合範圍的催化顆粒(鈀或其他活性催化劑)而混合了無機填充物，其餘是樹脂(以重量計)。摻合範圍包括5%的活性催化顆粒加18%的無機填充物(77重量%的樹脂)到對應範圍之13%的催化顆粒加13%的無機填充物(74重量%的樹脂)。普通而言，雖然增加無機填充物的比率則減少對催化顆粒比率的需求，但是5%到13%的活性催化顆粒範圍和13%到18%的無機填充顆粒範圍代表範例性範圍，可以使用其他濃度而不限於本發明的操作。
在催化劑當中，鈀是偏好的催化劑，因為比較經濟、可獲得性、機械性質，但可以使用其他的催化劑。
圖8A顯示催化積層的形成，其中饋入一卷織布802(例如織造的玻璃纖維)而經過多組滾筒，其將織布導入貯槽808裡，該貯槽填充了環氧樹脂，其摻合了催化顆粒並且混合了揮發性液體以減少黏滯度，藉此形成A階段(液態)預浸體。
樹脂可以是聚亞醯胺樹脂、環氧樹脂和氰酸酯(其提供在升高溫度之固化)的摻合物、或任何其他適合的樹脂配方，其在披覆期間具有可選擇的黏滯度和在冷卻之後的熱固性質。可以添加阻燃劑，舉例而言以符合可燃性標 準，或者相容於某一標準FR系列預浸體，例如FR-4或FR-10。高速電路的額外要求是：介電常數ε(電容率)，其通常近似於4並且掌控形成在介電質上之傳輸線的特徵阻抗；以及損失正切δ，其是在一距離而與頻率相關之能量吸收的度量，藉此損失正切是介電質如何與高頻電場交互作用而不利的減少訊號振幅的度量，即每公分的傳輸線長度有多少可計算量的分貝(dB)。樹脂摻合了催化顆粒，其已做尺寸篩選。於一範例性配方，催化顆粒包括以下至少一者：均質的催化顆粒(金屬性鈀)或異質的催化顆粒(鈀披覆在無機顆粒或高溫塑膠上)；對任一配方來說，催化顆粒較佳而言具有小於25微米的最大程度，並且50%的顆粒數尺寸在12微米和25微米之間，或者範圍為1~25微米或更小。這些是範例性催化顆粒類型和尺寸的具體態樣，而不打算限制本發明的範圍。於一範例性具體態樣，(均質的或異質的)催化顆粒之尺寸範圍在1微米~25微米。於本發明的另一範例，均質的催化顆粒形成如下：把金屬性鈀研磨成顆粒，並且使所得顆粒通過具有25微米矩形篩口的篩網。於另一範例，催化樹脂混合物806形成如下：將均質的或異質的催化顆粒依重量比率而摻合到預浸體樹脂裡，例如比率為實質上12重量%的催化顆粒對樹脂的重量。催化顆粒在樹脂混合物中的重量比率範圍替代選擇而言可以是5~16%的催化顆粒重量對樹脂的總重量。要了解也可以使用其他的摻合比率，並且可以較佳的是使用較小的顆粒。於本發明的一個範例，催化顆粒密度選擇成在催化顆粒之間提供等級在3微米到5微米的平均距離。
在織布浸沒到具有滾筒804的催化樹脂浴液806裡之後，催化樹脂所浸滲的布則導引到滾筒810，其建立未固化之液態A階段預浸體805的厚度，這也建立樹脂在樹脂/玻璃+樹脂的百分比率。A階段預浸體805然後通過烘烤爐803，其驅走A階段預浸體的有機物和其他揮發性化合物，並且大大減少液體含量，而形成無黏性的B階段預浸體807，其由滾筒811所傳遞。於範例性具體態樣，烤爐803從約80%之溶劑比率的A階段預浸體將揮發性化合物乾燥而成小於約 0.1%之溶劑比率的B階段預浸體。所得的B階段預浸體807提供給材料操持811，並且可以切割成片以易於操持和儲存；稍後則放入圖8B的積層加壓機826裡，其在真空下施加壓力而跨越諸片表面，並且遵循圖9所示的溫度圖902，而當預浸體核心是在積層加壓機中之時來改變溫度輪廓。於本發明的一個範例，為了生成富含樹脂的表面，定位靠近外表面的預浸片(其稍後將移除表面以暴露底下的催化顆粒)則選擇成具有大於65%的樹脂，例如玻璃106(71%的樹脂)、玻璃1067或玻璃1035(65%的樹脂)，並且內預浸片(其不受到表面移除)選擇成具有小於65%的樹脂。附帶而言，為了減少玻璃纖維出現在靠近催化預浸體之表面的可能性，織造的玻璃纖維可以用於內預浸層，並且平坦未織造的玻璃纖維可以用於富含樹脂的外預浸層。富含樹脂的預浸體和外表面層上平坦而未織造的玻璃纖維之組合則導致在外表面和包封玻璃纖維之間有0.7密耳(17微米)到0.9密耳(23微米)的排除區。玻璃型號106、1035、1067乃偏好用於富含樹脂的外表面上，因為玻璃纖維厚度(1.3~1.4密耳/33~35微米)小於典型預浸片中所見而大於65%的樹脂用在積層中央區域的玻璃纖維厚度，後者例如玻璃型號2116，其具有3.7密耳(94微米)的纖維。給出這些數值作為範例，而預期市售可得的最小玻璃纖維直徑會持續減少。本發明設計溫度對時間圖902以使催化顆粒和玻璃纖維從積層的外表面遷移離開，其在凝膠點溫度的液態期間被環氧樹脂的表面張力所排斥。在圖902的冷卻周期之後，將固化的C階段預浸片卸下814。形成固化C階段預浸片的製程可以使用單一或多片的纖維織布以變化完成的厚度，其可以從2密耳(51微米)變化到60密耳(1.5毫米)。
圖10顯示製作具有浸漬催化顆粒但預浸體外表面除外之預浸體積層的流程圖。步驟1002是將催化顆粒摻合到樹脂裡，通常添加了有機揮發物以降低混合物黏滯度，而形成放置於貯槽808中的催化樹脂806。步驟1004是將催化樹脂浸漬到例如圖8滾筒804的織布裡而可以提供形成A階段預浸體，並且步 驟1006是先以例如滾筒810捲起催化樹脂所浸漬的織布而成為B階段預浸體，步驟1007是烘烤步驟以移除有機溶劑而形成B階段預浸體，並且步驟1008是在積層加壓機826中將催化樹脂浸漬織布830加壓成催化C階段預浸片，其遵循圖902的溫度周期，而真空泵828在整個積層製程中將腔室824抽空以移除來自環氧樹脂的氣泡，並且減少可以形成於環氧樹脂中的任何氣孔。冷卻完成的催化C階段預浸片則切割和儲存供稍後使用。
圖9的溫度對時間圖902顯示預浸體在積層加壓機812中的溫度輪廓，這對於催化預浸體的形成是關鍵的，其所具有的表面性質是催化顆粒排除在富含樹脂的外表面外，而恰出現在富含樹脂的外表面底下。樹脂在貯槽808中是液態，並且預浸體在樹脂浸滲到玻璃纖維裡並且通過滾筒810之後是在A階段。預浸體在烘烤8010之後是在B階段，其中烘烤掉揮發性有機物並且伴隨著樹脂初始硬化，而在積層周期結束時(例如圖9的冷卻期)將B階段預浸體轉變成C階段預浸體。B階段預浸體放入積層加壓機中，並且導入真空以避免捕陷的空氣形成在積層之間。在溫度上升時間904期間加熱以達成溫度和壓力所決定的預浸體凝膠點905而達等級在10~15秒的持續時間(凝膠點定義為液態和固態接近彼此平衡的狀態)，這對於催化顆粒遷移離開表面的製程是關鍵的；之後預浸體的溫度維持在停留溫度和停留時間906，後者範圍可以是60~90分鐘，接著則是冷卻周期908。停留溫度和凝膠點溫度乃取決於壓力和樹脂，範例性範圍為120℃(用於環氧樹脂)到350℃(用於鐵氟龍/聚亞醯胺樹脂)。維持預浸體在凝膠點905的持續時間太短則將導致催化顆粒或玻璃纖維不利的出現在完成之預浸體的表面。
圖11顯示所得的催化預浸體1102，其由圖8A、8B、8C、9、10的製程所形成，其中催化顆粒1114均勻分布在預浸體1102的中央區域裡，但不存在於第一表面1104底下的邊界區域1108下或第二表面1106底下的邊界區域1110下。對於顆粒小於25微米的顆粒分布來說，催化顆粒邊界典型而言是在表面底 下10~12微米(顆粒尺寸之一半的等級)；據此，必須移除這深度或更大的表面材料以使嵌入的催化顆粒可用於無電鍍。
先前技藝的催化積層具有活化表面，其必須加以遮罩來避免催化積層的活化表面上有不要的無電鍍。相對來看，本發明的催化積層在厚度程度上從第一表面1104到第一邊界1108和從第二表面1106到第二邊界1110來排除催化顆粒，提供的好處是不需要像先前技藝之無電鍍的分開遮罩層來避免接觸催化顆粒。據此，從第一表面1104到邊界層1108的深度或更深來移除表面材料，或者從第二表面1106到第二邊界1110來移除表面材料，則導致暴露了可以用於無電鍍的催化材料。對於提供富含樹脂之表面的製程來說，也想要的是不僅排除催化劑，也還排除纖維織布，因為後續步驟移除表面層若導致暴露了纖維，則需要額外的清潔步驟；據此，偏好的是表面移除的僅有樹脂，如此以暴露底下的催化顆粒。這使用富含樹脂的外預浸體層和外側層上具有較小直徑纖維之平坦未織造的玻璃纖維層的組合來完成。使用無電鍍而在通道中形成跡線的額外優點在於跡線乃機械支持於三側上，這大大改善了跡線對於介電積層的附著。
本發明依賴移除表面材料以暴露底下的催化顆粒。有許多的方式來進行這表面移除而達到排除深度的程度。移除表面材料可以藉由雷射燒蝕來為之，其中催化預浸體的溫度立即升高，直到催化預浸體被氣化為止，而同時留下周圍的預浸體在結構上未改變，而讓催化顆粒暴露出來。可以較佳的是所使用的雷射波長對於要被燒蝕的預浸體材料來說具有這光學波長的低反射率和高吸收率，例如紫外線(ultraviolet，UV)波長。此種UV雷射的範例是UV準分子雷射或釔鋁石榴石(yttrium-aluminum-garnet，YAG)雷射，因為有窄的光束範圍和可有高功率來形成精確之機械深度和良好界定之側壁的通道，所以這類雷射也是良好的選擇。範例性雷射可以移除0.9~1.1密耳(23微米到28微米)直徑寬度的材料，其深度則由雷射功率和移動跨越表面的速度所掌控。另一種形成通道和孔 洞的表面移除技術則是電漿蝕刻，其可以局部進行，或者以從表面層排除電漿的圖案化遮罩來製備表面，該遮罩例如是乾膜光阻或其他遮罩材料，其相較於催化預浸體的蝕刻速率而具有低的蝕刻速率。光阻厚度典型而言基於環氧樹脂/光阻的蝕刻選擇性來選擇(使得電漿蝕刻到移除固化環氧樹脂所要的深度，而在蝕刻結束時留下足夠的光阻)；或者在使用光阻作為電鍍遮罩的情形，厚度根據所要的沉積厚度來選擇。典型的乾膜厚度範圍在0.8~2.5密耳(20~64微米)。適合蝕刻富含樹脂之表面的電漿包括氧(O)和CF4的混合物電漿，其混合了惰性氣體例如氮(N)，或者可以添加氬(Ar)作為用於反應性氣體的載氣。遮罩圖案也可以由乾膜遮罩、金屬遮罩、或具有孔洞之任何其他類型的遮罩來形成。若使用機械遮罩，則可以使用光微影術、網版印刷、鏤版化、橡膠滾筒、或任何施加蝕刻阻劑之方法中的任一者來施加蝕刻阻劑。另一種移除預浸體之表面層的方法是機械研磨，例如線性或旋轉切割工具。於這範例，預浸體可以固定於真空夾板，並且旋轉切割器(或具有可移動之真空板的固定切割器)可以繞行一界定軌跡的圖案，例如由吉勃(Gerber)格式光檔的x、y座標對所界定。於移除表面材料的另一範例，可以使用水切割工具，其中水流裡夾帶研磨顆粒的噴射水柱可以打在表面上，藉此移除在第一排除深度邊界底下的材料。這些方法中的任一者可以分開或組合使用以移除表面材料並且在催化預浸體中形成通道，該通道較佳而言延伸於排除深度邊界底下。據此，最小通道深度是暴露底下之催化顆粒所需的深度，其為固化之預浸體的特徵。由於催化材料均勻分散穿過固化的預浸體而在排除邊界底下，故最大通道深度受限於織造纖維(例如玻璃纖維)織布的深度，其傾向於讓通道清潔變得複雜，因為纖維可以斷掉並且再次沉積於打算做無電鍍的通道中，或者另外干擾後續的製程步驟。典型的通道深度是1密耳(25微米)到2密耳(70微米)。在移除表面材料以形成通道之後的最後步驟則是清掉被移除的任何材料顆粒，這可以使用超音波清潔、混合了界面活性劑的噴射水柱、 或不導致包圍通道的表面材料被移除的任何其他清潔手段來完成。
一範例性無電鍍銅浴液配方使用以下的混合物：羅謝爾(Rochelle)鹽(作為錯合劑)、硫酸銅(作為銅金屬來源)、甲醛(作為還原劑)、氫氧化鈉(作為反應物)。於這範例，偏好酒石酸鹽(羅謝爾鹽)浴液，因為容易處理廢料；羅謝爾鹽不像例如乙二胺四乙酸(EDTA)或乙二胺(quadrol)的替代選擇者螯合得那麼強烈。於這範例，酒石酸鹽(羅謝爾鹽)是完全劑，硫酸銅是金屬來源，甲醛是還原劑，氫氧化鈉是反應物。可能有其他的無電鍍配方，給出這範例以供參考。無電鍍起初形成於暴露之催化顆粒的表面上。隨著無電鍍繼續便進行銅沉積，直到填充了通道和孔洞為止，可選用而言在催化積層的表面上方。替代選擇而言，當導體跡線是連續且夠厚以抵抗可以讓跡線斷裂的機械衝擊或其他環境因素時，無電鍍就可以停止，如無電鍍技藝所已知。
蝕刻於催化材料中之通道做無電鍍的關鍵優點在於無電鍍一次進行於所有三側上，相較於電鍍來看，後者僅從底層(初始鍍覆)來進行。
如果需要的話，可以想要的是在無電鍍之後將表面平坦化，如果無電鍍提供不平坦的表面。表面平滑化可以採取許多不同的方式來完成，舉例而言使用420到1200號的研磨砂礫，其以溫和壓力而施加在平坦表面上，並且在板和平坦表面之間做線性或旋轉攪拌以提供研磨作業。可以使用其他將表面平坦化的方法，包括使用化學製程、機械製程的磨軋或車削、或其他形成平坦表面的方法。
本發明之添加性製程的優點在於：對於使用先前技藝製程所形成的跡線來說，該製程蝕刻所有的銅，而所要的跡線銅除外，表面上的表面汙染物則使相鄰的跡線短路，因為若汙染物存在於銅表面上則維持了銅橋接物，而這不發生在本發明的添加性無電鍍。
催化黏著劑可以如先前針對催化樹脂所述的形成，其使用5~16% 之催化劑重量對樹脂重量的比率，而12%是偏好的數值。所得的催化黏著劑可以施加到晶片基板，並且烘烤以使催化黏著劑固化。於一施加方法，催化黏著劑施加到機械化橡膠滾筒的前緣，該滾筒包括可撓性刀片而載有催化黏著劑，並且通過晶片的表面上，晶片是從完整晶圓切出來的單獨晶片晶粒或是完整的晶圓，而壓力與可撓性刀片和晶片或晶圓之間的間隔則調整成催化積層所要的厚度，以在橡膠滾筒的單次通過中使之均勻配置於晶片表面上。典型的催化黏著劑厚度是12~75微米厚。催化黏著劑的厚度應比最大催化顆粒還厚至少2倍，以確保催化顆粒維持在催化黏著劑的表面底下。
前面敘述僅要提供本發明的範例來理解背後所用的機制和結構，並且不打算使本發明僅限於所示的特殊方法或結構。舉例而言，圖6C-1、6D、6E的順序顯示單一側架構，而跡線通道僅切割於下表面上並且晶片僅在上表面上，然而相同的結構和方法可以應用到相反表面，而不失其一般性，因為無電鍍步驟可以在單一步驟中應用到在板二側上的通道或暴露的催化劑。附帶而言，跡線層606可以形成為單獨層，其後續積層在一起而成單一板，其具有催化預浸體和非催化預浸體的混合層，並且在最後步驟鑽孔以在板的一或二側上做一或多個晶片的無電鍍。據此，催化基板應了解是包括「多層催化基板」(multilayer catalytic substrate)以包括此種架構。
於本說明書，「近似」(approximately)要了解乃意謂或多或少小於4倍，「實質」(substantially)要了解乃意謂或多或少於2倍。數值的「數量級」(order of magnitude)所包括的範圍是從0.1倍的數值到10倍的數值。
前面已是本發明之較佳具體態樣的描述。將體會可以做出偏差和修改，而不偏離本發明由附上之請求項所界定的範圍。
302‧‧‧晶片
326‧‧‧晶片附接襯墊、晶片觸墊
502‧‧‧多層板
512‧‧‧孔洞
514‧‧‧外無電鍍覆
516‧‧‧通孔

Claims (19)

  1. 一種積體電路封裝，其包括：催化積層，其具有第一表面和相對於該第一表面的第二表面，該第二表面具有用於電附接的觸墊，該催化積層具有催化顆粒，其分散於該第一表面及該第二表面之每一者以下的排除深度；多個孔洞，其在該催化積層中，至少一該孔洞的位置相鄰於用於附接之積體電路的觸墊；多個通道，其形成於該催化積層的該第二表面上，該通道的深度大於該排除深度，至少一該通道從相鄰於該積體電路的該觸墊的孔洞延伸；該多個通道、該孔洞以及該積體電路的該觸墊具有暴露的催化顆粒，使得無電沉積銅所形成的導體將該積體電路的該觸墊、該通道以及該第二表面的該觸墊互連。
  2. 如申請專利範圍第1項的積體電路封裝，其中該催化積層是由包括以下至少一者的催化顆粒所形成：鈀(Pd)、鉑(Pt)、銠(Rh)、銥(Ir)、鎳(Ni)、金(Au)、銀(Ag)、鈷(Co)或銅(Cu)、或其之其他化合物或其鹽類。
  3. 如申請專利範圍第1項的積體電路封裝，其中該催化顆粒包括以催化劑披覆的填充物，並且該填充物是以下至少一者：黏土礦物質、水合葉矽酸鋁(hydrous aluminum phyllosilicate)、二氧化矽、高嶺土、聚矽酸鹽、該高嶺土或瓷黏土家族的成員或高溫塑膠。
  4. 如申請專利範圍第1項的積體電路封裝，其中該排除區域近似催化顆粒之最長尺度的1/2。
  5. 如申請專利範圍第1項的積體電路封裝，其中該催化積層包括混合了催化顆粒的樹脂，其中該催化顆粒對該樹脂的重量比率範圍在5%到16%，並且其中該催化積層在凝膠點溫度下經過凝膠點停留時間而固化，足以使該催 化顆粒在該催化積層之該第一表面及該第二表面之每一者下的排除深度以下遷移。
  6. 如申請專利範圍第5項的積體電路封裝，其中該樹脂包含以下至少一者：環氧樹脂、聚亞醯胺樹脂、氰酸酯樹脂、或鐵氟龍(Teflon®)摻合樹脂。
  7. 如申請專利範圍第1項的積體電路封裝，其中該織布是織造或未織造的玻璃纖維。
  8. 如申請專利範圍第1項的積體電路封裝，其中該積體電路的該觸墊具有一層相容於無電鍍的過渡金屬，其中該層具有暴露的催化顆粒，或者該層是由銅所形成。
  9. 一種形成積體電路封裝的製程，該製程可操作在積體電路和催化積層上，該積體電路具有導電觸墊，並且該催化積層具有第一表面和相對於該第一表面的第二表面，該第一表面及該第二表面之每一者在該催化積層之該第一表面及該第二表面之每一者下的排除深度則具有減少的催化顆粒密度，該製程包括：將孔洞形成到該催化積層裡，而位置對應於該觸墊，該孔洞藉此暴露該催化積層的該催化顆粒；將通道形成至該排除深度以下的深度，而通到該孔洞並且也通到該第二表面上的連接區域；進行無電鍍作業，直到該通道和孔洞電接觸該觸墊為止。
  10. 如申請專利範圍第9項的製程，其中該無電鍍金屬是銅，並且該催化劑是鈀。
  11. 如申請專利範圍第9項的製程，其中該觸墊是由銅所形成，或是由表面沉積了銅或催化顆粒的鎳閃鍍(nickel flash)所形成。
  12. 如申請專利範圍第9項的製程，其中該催化積層具有混合了無機 填充物的催化顆粒。
  13. 如申請專利範圍第9項的製程，其中該催化積層具有濃度範圍在5重量%到16重量%的催化顆粒，其在該催化積層之該第一表面及該第二表面之每一者以下的排除深度。
  14. 如申請專利範圍第9項的製程，其中該催化積層具有範圍在5%到13%的活性催化顆粒以及具有對應範圍在18%到13%的無機填充顆粒。
  15. 一種積體電路封裝，其包括：積體電路晶片，其具有導電觸墊；催化樹脂，其施加到該積體電路，該催化樹脂包括混合了催化顆粒的樹脂；該催化樹脂固化至該積體電路，進行該固化使得該催化樹脂的表面在該表面下的排除深度沒有暴露的催化顆粒；該催化樹脂具有多個孔洞，該孔洞定位成相鄰於該觸墊；多個裝置電附接，該通道配置成提供從該觸墊到該封裝端子的互連路徑，其中該通道和該孔洞在以無電鍍銅沉積所鍍覆之後形成導體。
  16. 如申請專利範圍第15項的積體電路封裝，其中該催化樹脂包含以下至少一者：鈀(Pd)、鉑(Pt)、銠(Rh)、銥(Ir)、鎳(Ni)、金(Au)、銀(Ag)、鈷(Co)或銅(Cu)、或其化合物或鹽類。
  17. 如申請專利範圍第15項的積體電路封裝，其中該催化樹脂包括範圍在5重量%到16重量%的催化顆粒，該催化顆粒的最長尺度小於25微米。
  18. 一種形成積體電路封裝的製程，該製程可操作在具有導電觸墊的積體電路上，該製程包括：將催化積層施加到該積體電路的表面，該催化積層在排除深度以下具有催化顆粒；將孔洞形成於該積層中而相鄰於該觸墊； 將裝置引線形成於該催化積層中；將通道形成於該積層中而可選用的將該觸墊互連於該裝置端子；無電鍍覆該積體電路封裝，藉此連接該裝置端子和該觸墊。
  19. 如申請專利範圍第18項的製程，其中該催化積層包括最長尺度小於25微米的催化顆粒，並且該催化顆粒的重量範圍在5%到16%。
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10573610B2 (en) * 2014-05-19 2020-02-25 Catlam, Llc Method for wafer level packaging
US9922951B1 (en) * 2016-11-12 2018-03-20 Sierra Circuits, Inc. Integrated circuit wafer integration with catalytic laminate or adhesive
ES2646237B2 (es) 2017-09-28 2018-07-27 Avanzare Innovacion Tecnologica S.L. Formulación para el mordentado de materiales poliméricos previo al recubrimiento de los mismos
US10290612B1 (en) * 2018-05-30 2019-05-14 Invensas Corporation Systems and methods for flash stacking
TWI792942B (zh) * 2022-03-11 2023-02-11 瑞昱半導體股份有限公司 積體電路封裝基板

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI252723B (en) * 1999-10-26 2006-04-01 Ibiden Co Ltd Multi-layer printed circuit board and method of manufacturing multi-layer printed circuit board
TW201607397A (zh) * 2014-05-19 2016-02-16 席拉電路公司 印刷電路板中的通孔

Family Cites Families (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3269891A (en) 1965-08-31 1966-08-30 American Cyanamid Co Fixing dry strength resin on fibers by alum in the presence of a buffer
US3546009A (en) 1967-01-03 1970-12-08 Kollmorgen Corp Metallization of insulating substrates
GB1164591A (en) * 1968-01-03 1969-09-17 Photocircuits Corp mprovements in Metallization of Insulating Substrates
CA939831A (en) * 1969-03-27 1974-01-08 Frederick W. Schneble (Jr.) Plated through hole printed circuit boards
US3907621A (en) * 1971-07-29 1975-09-23 Photocircuits Corp Method of sensitizing substrates for chemical metallization
US3925138A (en) 1973-11-27 1975-12-09 Formica Int Process for preparing an insulating substrate for use in printed circuits
US4001466A (en) 1973-11-27 1977-01-04 Formica International Limited Process for preparing printed circuits
US4287253A (en) 1975-04-08 1981-09-01 Photocircuits Division Of Kollmorgen Corp. Catalytic filler for electroless metallization of hole walls
US4167601A (en) 1976-11-15 1979-09-11 Western Electric Company, Inc. Method of depositing a stress-free electroless copper deposit
EP0003801B1 (en) * 1978-02-17 1982-06-09 E.I. Du Pont De Nemours And Company Use of photosensitive stratum to create through-hole connections in circuit boards
JPS5830760B2 (ja) 1980-10-09 1983-07-01 株式会社日立製作所 プリント回路板の製法
US4354895A (en) 1981-11-27 1982-10-19 International Business Machines Corporation Method for making laminated multilayer circuit boards
US4585502A (en) 1984-04-27 1986-04-29 Hitachi Condenser Co., Ltd. Process for producing printed circuit board
US4859571A (en) 1986-12-30 1989-08-22 E. I. Du Pont De Nemours And Company Embedded catalyst receptors for metallization of dielectrics
US5260170A (en) 1990-01-08 1993-11-09 Motorola, Inc. Dielectric layered sequentially processed circuit board
US5252195A (en) * 1990-08-20 1993-10-12 Mitsubishi Rayon Company Ltd. Process for producing a printed wiring board
US5162144A (en) 1991-08-01 1992-11-10 Motorola, Inc. Process for metallizing substrates using starved-reaction metal-oxide reduction
US5371654A (en) 1992-10-19 1994-12-06 International Business Machines Corporation Three dimensional high performance interconnection package
JPH0936522A (ja) * 1995-07-14 1997-02-07 Fuji Kiko Denshi Kk プリント配線板における回路形成方法
DE19731346C2 (de) 1997-06-06 2003-09-25 Lpkf Laser & Electronics Ag Leiterbahnstrukturen und ein Verfahren zu deren Herstellung
FR2812515B1 (fr) * 2000-07-27 2003-08-01 Kermel Procede de realisation d'une circuiterie comportant pistes, pastilles et microtraversees conductrices et utilisation de ce procede pour la realisation de circuits imprimes et de modules multicouches a haute densite d'integration
JP2002261186A (ja) * 2001-03-02 2002-09-13 Hitachi Chem Co Ltd 半導体搭載用基板とその製造方法とそれを用いた半導体パッケージ並びにその製造方法
US7334326B1 (en) 2001-06-19 2008-02-26 Amkor Technology, Inc. Method for making an integrated circuit substrate having embedded passive components
JP3784368B2 (ja) * 2001-12-27 2006-06-07 三井化学株式会社 回路基板およびその製造方法
GB0212632D0 (en) 2002-05-31 2002-07-10 Shipley Co Llc Laser-activated dielectric material and method for using the same in an electroless deposition process
JP2005353837A (ja) * 2004-06-10 2005-12-22 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP4146826B2 (ja) 2004-09-14 2008-09-10 カシオマイクロニクス株式会社 配線基板及び半導体装置
TW200618705A (en) 2004-09-16 2006-06-01 Tdk Corp Multilayer substrate and manufacturing method thereof
US20060068173A1 (en) 2004-09-30 2006-03-30 Ebara Corporation Methods for forming and patterning of metallic films
US7752752B1 (en) 2007-01-09 2010-07-13 Amkor Technology, Inc. Method of fabricating an embedded circuit pattern
CN101687218A (zh) 2007-07-02 2010-03-31 3M创新有限公司 图案化基底的方法
US7632753B1 (en) 2007-10-04 2009-12-15 Amkor Technology, Inc. Wafer level package utilizing laser-activated dielectric material
KR100936078B1 (ko) 2007-11-12 2010-01-12 삼성전기주식회사 전기부재 및 이를 이용한 인쇄회로기판의 제조방법
US8246774B2 (en) 2007-12-27 2012-08-21 Alps Electric Co., Ltd. Resin bonding method by photoirradiation, method for producing resin article, resin article produced by the same method, method for producing microchip, and microchip produced by the same method
TWI384594B (zh) 2008-06-05 2013-02-01 Unimicron Technology Corp 內埋式線路結構的製程
TWI388122B (zh) 2009-04-20 2013-03-01 Unimicron Technology Corp 形成複合材料電路板結構的方法
TWI392425B (zh) 2009-08-25 2013-04-01 Unimicron Technology Corp 內埋式線路板及其製造方法
TWI423750B (zh) 2010-09-24 2014-01-11 Kuang Hong Prec Co Ltd 非導電性載體形成電路結構之製造方法
KR101215644B1 (ko) * 2010-12-01 2012-12-26 에스케이하이닉스 주식회사 반도체 칩, 반도체 패키지 및 반도체 칩 제조방법
GB2489042A (en) 2011-03-18 2012-09-19 Conductive Inkjet Technology Ltd Photo-patternable structure
US9105628B1 (en) * 2012-03-29 2015-08-11 Valery Dubin Through substrate via (TSuV) structures and method of making the same
CN102931098B (zh) * 2012-11-08 2015-06-03 南通富士通微电子股份有限公司 芯片封装方法
JP2015057812A (ja) * 2013-08-09 2015-03-26 太陽インキ製造株式会社 プリント配線基板の製造方法、それに用いられる積層体、積層フィルム、及び非硬化性樹脂組成物並びに前記製造方法により得られるプリント配線基板
US9631279B2 (en) * 2014-05-19 2017-04-25 Sierra Circuits, Inc. Methods for forming embedded traces
US9706667B2 (en) 2014-05-19 2017-07-11 Sierra Circuits, Inc. Via in a printed circuit board
US10573610B2 (en) 2014-05-19 2020-02-25 Catlam, Llc Method for wafer level packaging
US9380700B2 (en) 2014-05-19 2016-06-28 Sierra Circuits, Inc. Method for forming traces of a printed circuit board
KR20190049736A (ko) * 2016-08-18 2019-05-09 씨에라 써킷스 인코포레이티드 트레이스 및 비아를 갖는 플라스마 에칭 촉매 라미네이트
US9706650B1 (en) * 2016-08-18 2017-07-11 Sierra Circuits, Inc. Catalytic laminate apparatus and method
US9922951B1 (en) * 2016-11-12 2018-03-20 Sierra Circuits, Inc. Integrated circuit wafer integration with catalytic laminate or adhesive
US10349520B2 (en) * 2017-06-28 2019-07-09 Catlam, Llc Multi-layer circuit board using interposer layer and conductive paste

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI252723B (en) * 1999-10-26 2006-04-01 Ibiden Co Ltd Multi-layer printed circuit board and method of manufacturing multi-layer printed circuit board
TW201607397A (zh) * 2014-05-19 2016-02-16 席拉電路公司 印刷電路板中的通孔

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