TWI737384B - Display device and driving method thereof and gate driving circuit - Google Patents

Abstract

Embodiments of the present disclosure relates to a display device and a driving method thereof and a gate driving circuit capable of solving problems with insufficient charging time or image abnormalities by controlling supply timing of two gate signals, i.e., scan signals and sense signals. The gate driving circuit comprises first gate driving circuit configured to supply first scan signal having an interval of turn-on level voltage to first scan signal line electrically connected to gate node of scan transistor in first subpixel included in a plurality of subpixels arranged on display panel; and a second gate driving circuit configured to supply first sense signal having an interval of turn-on level voltage, which is delayed from the interval of turn-on level voltage of the first scan signal by a predetermined sense shift time, to first sense signal line electrically connected to gate node of sense transistor in the first subpixel.

Description

Display device and its driving method and gate driving circuit

The embodiment of the present invention relates to a display device and a driving method thereof, and a gate driving circuit.

The development of society based on information has brought about an increasing demand for various display devices for displaying images. Recently, various display devices such as liquid crystal display screens, plasma display screens, and organic diode screens have been used.

This type of display device can charge the capacitors of a plurality of sub-pixels placed on its display panel, and can use the same method to drive a display. However, in some examples of existing display devices, the image quality may be deteriorated due to insufficient charging of individual sub-pixels. In addition, existing display devices may have unclear images and dragged images, or there may be a difference in brightness between lines and lines, which may reduce the quality of the image due to changes in the light emission period.

The embodiments of the present invention can provide a display device and a driving method thereof, and a gate driving circuit, which can improve the charging rate by superimposing driving on the sub-pixels, thereby improving the image quality.

In addition, the embodiments of the present invention can provide a display device and a driving method thereof, and a gate driving circuit, by avoiding the phenomenon of unclear images and being dragged, or avoiding the insertion and driving of false data, the display of multiple real The phenomenon of the brightness difference between multiple sub-pixel lines caused by intermittent insertion of false images (such as black images, low grayscale images, etc.) between images to improve image quality.

In addition, the embodiments of the present invention can provide a display device and a driving method thereof, and a gate driving circuit, which can obtain the advantages of both overlap driving and dummy data insertion driving through advanced overlap driving, even in the case of overlap driving. During the period, the dummy data is inserted into the driver, and the overlapped driver will not change the characteristics of the overlapped driver due to the dummy data inserted into the driver.

In addition, embodiments of the present invention can provide a display device and a driving method thereof, and a gate driving circuit. Even if dummy data is inserted into the driver during the overlapping driving period, it can avoid image abnormalities in time before the dummy data is inserted into the driver. (Such as the phenomenon of specific line brightness).

Furthermore, the embodiments of the present invention can provide a display device and a driving method thereof, and a gate driving circuit. In addition to advanced overlapping driving, it can also increase the channel width of the sensing transistor to the channel length. Ratio to compensate for the reduction in charging time.

Embodiments of the present invention may provide a gate-operated circuit including: a scan clock signal generator for receiving a first reference scan clock signal and a second reference scan clock signal, and for generating and outputting A scanning clock signal; a sensing clock signal generator for receiving a first reference sensing clock signal and a second reference sensing clock signal, and for generating and outputting a sensing clock signal ; And a gate signal output device for outputting a scan signal based on the scan clock signal with a turn-on level voltage interval, and for outputting a turn-on level voltage interval based on the sensing clock signal Sense signal

After the first reference scan clock signal rises and falls, the second reference scan clock signal can rise and fall. After the first reference sensing clock signal rises and falls, the second reference sensing clock signal can rise and fall.

A high-level gate voltage interval of the sensing clock signal can be delayed by a predetermined sensing offset time from a high-level gate voltage interval of the scanning clock signal. Accordingly, the turn-on level voltage interval of the sensing clock signal can be delayed by the predetermined sensing offset time from the turn-on level voltage interval of the scanning clock signal.

The scan clock signal generator can be used to generate and output the scan clock signal. The scan clock signal rises at a rise time of the first reference scan clock signal, and when the second reference scan clock signal rises Decrease at a fall time.

The sensed clock signal generator can be used to generate and output the sensed clock signal, the sensed clock signal rising at a rising time of the second reference sensed clock signal, instead of the first reference The sensing clock signal rises during a rising time, and the sensing clock signal falls after a falling time of the second reference sensing clock signal passes a predetermined delay time.

A time interval between the rising time of the first reference sensing clock signal and the rising time of the second reference sensing clock signal can correspond to the predetermined sensing offset time.

The rising time of the first reference sensing clock signal may be the same as the rising time of the first reference scanning clock signal.

The rising time of the second reference sensing clock signal may precede a rising time of the second reference scanning clock signal.

A length of time during which the scanning clock signal and the sensing clock signal overlap each other may correspond to a value obtained by subtracting the predetermined delay time from a time length of the conduction level voltage interval of the sensing signal .

The scanning clock signal generator may include: a scanning logic unit for receiving the first reference scanning clock signal and the second reference scanning clock signal, and generating the rise in the first reference scanning clock signal The scan clock signal that rises in time and falls at the fall time of the second reference scan clock signal; and a scan level shifter for outputting a gate voltage that rises to a high level and falls to a level The scan clock signal of the low-level gate voltage.

The sensing clock signal generator may include: a sensing logic unit for receiving the first reference sensing clock signal and the second reference sensing clock signal, and generating the sensing clock signal, the The sense clock signal rises at the rise time of the second reference sense clock signal, instead of rising at the rise time of the first reference sense clock signal, and the sense clock signal rises at the rise time of the first reference sense clock signal The falling time of the second reference sensing clock signal falls after the predetermined delay time; a delay device is used to delay the rising time of the sensing clock signal so that the sensing clock signal is in the second reference The sensing clock signal rises at the rising time of the clock signal, instead of rising at the rising time of the first reference sensing clock signal; and a sensing level shifter for outputting the gate rising to the high level Voltage and drop to the low-level gate voltage of the sensing clock signal, and the sensing clock signal has the predetermined sensing offset time delayed from the high-level gate voltage interval of the scanning clock signal High-level gate voltage range.

The delay device may include one or more resistive elements.

In one aspect, an embodiment of the present invention can provide a display device including: a display panel including a plurality of data lines, a plurality of scanning signal lines, a plurality of sensing signal lines, a plurality of reference lines, and a plurality of sub-pixels, wherein Each of the sub-pixels includes: a light-emitting element; a driving transistor for driving the light-emitting element; a scanning transistor for controlling one of the data lines and one of the driving transistors according to a scan signal A connection between the first node; a sensing transistor for controlling the connection between one of the reference lines and a second node of the driving transistor according to a sensing signal; and a capacitor, connected Between the first node and the second node of the driving transistor. The display device also includes a data driving circuit for driving the data lines; a first gate driving circuit for supplying a first scan signal to a first scan signal line, wherein the first scan signal line is electrically Is electrically connected to a gate node of the scanning transistor in a first sub-pixel included in the sub-pixels, and the first scanning signal has an interval of a turn-on level voltage; and a second gate driver A circuit for supplying a first sensing signal to a first sensing signal line, wherein the first sensing signal line is electrically connected to a gate node in the sensing transistor of the first sub-pixel, the The first sensing signal has an interval of a turn-on level voltage, and the interval of the turn-on level voltage of the first sensing signal line is delayed from the interval of the turn-on level voltage of the first scan signal line A predetermined sensing offset time.

The interval of the turn-on level voltage of the first sensing signal may include: among them, the interval of the turn-on level voltage of the first sensing signal overlaps the turn-on level voltage of the first scan signal A period of the interval of the interval; and among them, the interval of the conduction level voltage of the first sensing signal does not overlap a period of the interval of the conduction level voltage of the first scan signal.

The period in which the interval of the turn-on level voltage of the first sensing signal overlaps the interval of the turn-on level voltage of the first scan signal may correspond to a programming period in which image data is programmed To the first sub-pixel.

A starting point of the interval of the turn-on level voltage of the first sensing signal may be delayed by the predetermined sensing offset time from a starting point of the interval of the turn-on level voltage of the first scanning signal.

The predetermined sensing offset time may correspond to a half of the interval of the turn-on level voltage of the first scan signal.

The sub-pixels may further include a second sub-pixel and a third sub-pixel, wherein the first sub-pixel, the second sub-pixel, and the third sub-pixel include drains of the sensing transistors The node or multiple source nodes are electrically connected to the same reference line.

When a second scanning signal with a turn-on level voltage is supplied to a gate node of the scanning transistor of the second sub-pixel, and when a second sensing signal with a turn-on level voltage is supplied to When a gate node of the sensing transistor of the second sub-pixel, there may be a point in time when the sensing transistor of the first sub-pixel and the sensing transistor system of the third sub-pixel are turned off at the same time .

During the period in which the i-th ("i" is a natural number equal to or greater than 1) scan signal having a conduction level voltage is supplied to the i-th scan signal line of the scan signal lines, it has a conduction level The voltage of the (i+1)-th scan signal is supplied to the (i+1)-th scan signal line of the scan signal lines in a period between which is a fake data that is different from the voltage of a real image data The voltage can be supplied to a plurality of sub-pixels arranged in k ("k" is a natural number equal to or greater than 1) sub-pixel lines.

On the other hand, an embodiment of the present invention may provide a gate driving circuit, including: a first gate driving circuit for supplying a first scan signal to a first scan signal line, wherein the first scan signal line A gate node of a scanning transistor that is electrically connected to a first sub-pixel included in a plurality of sub-pixels, and the first scan signal has an interval of a turn-on level voltage, and the sub-pixels are placed in a display Panel; and a second gate driving circuit for supplying a first sensing signal to a first sensing signal line, wherein the first sensing signal line is electrically connected to a sensing circuit of the first sub-pixel A gate node of the crystal, the first sensing signal has an interval of a turn-on level voltage, and the interval of a turn-on level voltage of the first sensing signal line is greater than that of the first scan signal line The interval of the level voltage is delayed by a predetermined sensing offset time.

The sub-pixels may further include a second sub-pixel and a third sub-pixel, wherein the first sub-pixel, the second sub-pixel, and the third sub-pixel include a plurality of drains of the sensing transistors The node or multiple source nodes are electrically connected to the same reference line.

When a second scanning signal with a turn-on level voltage is supplied to a gate node of the scanning transistor of the second sub-pixel, and when a second sensing signal with a turn-on level voltage is supplied to When a gate node of the sensing transistor of the second sub-pixel, there may be a point in time when the sensing transistor of the first sub-pixel and the sensing transistor system of the third sub-pixel are turned off at the same time .

On the other hand, an embodiment of the present invention may provide a method for driving a display device, including: supplying a first scan signal to a first scan signal line, wherein the first scan signal line is electrically connected to a plurality of sub-pixels. A gate node of a scanning transistor in a first sub-pixel of, and the first scanning signal has an interval of a turn-on level voltage, so that a picture supplied from a data line is transmitted through the scanning transistor Image data voltage to a first node of a driving transistor of the first sub-pixel; supply a first sensing signal to a first sensing signal line, wherein the first sensing signal line is electrically connected to the first A gate node in a sensing transistor of a sub-pixel, the first sensing signal has an interval of a turn-on level voltage, so that through the sensing transistor, a reference voltage supplied from a reference line is transmitted to A second node of the driving transistor, wherein the interval of the conduction level voltage of the first sensing signal line is delayed by a predetermined sensing deviation than the interval of the conduction level voltage of the first scanning signal line Shifting time; and supplying the first scan signal with an interval of a turn-off level voltage to the first scan line and supplying the first sensing signal with an interval of a turn-off level voltage to the first Sensing signal line.

The interval of the turn-on level voltage of the first sensing signal may include: among them, the interval of the turn-on level voltage of the first sensing signal overlaps the turn-on level voltage of the first scan signal A period of the interval of the interval; and among them, the interval of the conduction level voltage of the first sensing signal does not overlap a period of the interval of the conduction level voltage of the first scan signal.

A starting point of the interval of the conduction level voltage of the first sensing signal may be delayed by the predetermined sensing offset time than a starting point of the interval of the conduction level voltage of the first scanning signal, and The predetermined sensing offset time may correspond to a half of the interval of the turn-on level voltage of the first scan signal.

The sub-pixels may further include a second sub-pixel and a third sub-pixel, wherein the first sub-pixel, the second sub-pixel, and the third sub-pixel include drains of the sensing transistors The node or multiple source nodes are electrically connected to the same reference line.

When a second scanning signal with a turn-on level voltage is supplied to a gate node of the scanning transistor of the second sub-pixel, and when a second sensing signal with a turn-on level voltage is supplied to When a gate node of the sensing transistor of the second sub-pixel, there may be a point in time when the sensing transistor of the first sub-pixel and the sensing transistor system of the third sub-pixel are turned off at the same time .

During the period in which the i-th ("i" is a natural number equal to or greater than 1) scan signal having a conduction level voltage is supplied to the i-th scan signal line of the scan signal lines, it has a conduction level The voltage of the (i+1)-th scan signal is supplied to the (i+1)-th scan signal line of the scan signal lines in a period between which is a fake data that is different from the voltage of a real image data The voltage can be supplied to a plurality of sub-pixels arranged in k ("k" is a natural number equal to or greater than 1) sub-pixel lines.

According to the embodiment of the present invention, the charging rate can be improved by superimposing driving on the sub-pixels, so that the quality of the image can be improved.

In addition, according to the embodiments of the present invention, it can avoid the phenomenon that the image is unclear and dragged, or to avoid inserting the drive due to false data (intermittently inserting false images between the displayed multiple real images, such as Black images, low grayscale images, etc.) caused by the phenomenon of brightness differences between multiple sub-pixel lines, it is possible to improve the image quality.

In addition, according to the embodiment of the present invention, even if dummy data is inserted into the drive during the overlap drive, control can still be performed so that the characteristics of the overlap drive will not be changed immediately before the dummy data is inserted into the drive through the advanced overlap drive. Among them, in the advanced overlap driving, the voltage interval of the on-level voltage of the sensing signal in the two gate signals (scan signal and sensing signal) is controlled to be longer than the voltage interval of the on-level voltage of the scan signal. Delay.

Therefore, in the case of inserting dummy data into the driving during the overlapping driving, it is possible to avoid image abnormalities (such as specific line brightness phenomenon) occurring in the sub-pixel row in time before the dummy data is inserted into the driving.

Furthermore, the embodiments of the present invention can provide a display device and a driving method thereof, and a gate driving circuit. In addition to advanced overlapping driving, it can also increase the channel width of the sensing transistor to the channel length. Ratio to compensate for the reduction in charging time.

In the following description of the embodiments or embodiments of the present invention, reference will be made to the accompanying drawings, in which specific embodiments or embodiments that can be implemented are shown schematically, even though the same reference numbers and symbols are shown in different drawings. The same reference numbers and signs may also be used to designate the same or similar components, even if they show different components from each other in different drawings. Furthermore, in the following description of the embodiments or embodiments of the present invention, when detailed descriptions of conventional functions and components may make the content of certain embodiments of the present invention quite unclear, the description will be omitted. The terms used here, such as "include", "have", "include", "constitute" and "constitute" are generally used to allow the addition of other components, unless these terms are used together with the term "only". The singular form used here is intended to include the plural form, unless the context clearly indicates that it is different.

Terms such as "first", "second", "A", "B", "(a)", "(b)" or "(a)" can be used herein to describe elements of the present invention. Any of these terms is not used to define the essence, order, or number of elements, etc., but only to distinguish the corresponding element from other elements.

When it is mentioned that the first element and the second element are "connected or coupled", "overlapped", etc., it should be understood that not only the first element can be "directly connected or coupled" or "directly overlapped" with the second element, but also the third element It can also be "interspersed" between the first element and the second element, or the first element and the second element can be "connected or coupled" or "overlapped" with each other through the fourth element. Here, the second element may be included in at least one of two or more elements, and these elements are "connected or coupled", "overlapped", etc., with each other.

When using time-relative terms, such as "after", "next", "next", "before", etc. to describe the process or operation of an element or configuration, or the process or step in an operation, processing, or manufacturing method, These terms can be used to describe non-continuous or non-sequential processes or operations, unless terms such as "directly" or "immediately" are used together.

In addition, when referring to any size, relative size, etc., the value of the element or feature or the corresponding information (such as level, range, etc.) should be considered, including various factors (such as process factors, internal or external influences, noise Etc.) The tolerance or error range caused by it should be considered even if the relevant description is not specified. In addition, words such as "可", "能", and "may" completely contain all the meanings of "may".

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a system configuration diagram of a display device 100 according to an embodiment of the present invention.

1, the display device 100 of the embodiment of the present invention may include a display panel 110, a data driving circuit 120, a first gate driving circuit 130, a second gate driving circuit 140, etc., and may further include a Controller 150.

The display panel 110 may include multiple data lines DL, multiple scan signal lines SCL, multiple sensing signal lines SENL, multiple reference lines RL, multiple sub-pixels SP, and so on. The display panel 110 may include a display area and a non-display area. A plurality of sub-pixels SP for displaying images can be arranged in the display area. The driving circuits 120, 130, and 140 can be electrically connected or installed in the non-display area, and a pad portion can be provided therein.

The data driving circuit 120 is used to drive the data lines DL, and can supply a data voltage to the data lines DL.

The first gate driving circuit 130 sequentially supplies a plurality of scan signals SCAN to the scan signal lines SCL as a kind of gate lines.

The second gate driving circuit 140 sequentially supplies a plurality of sensing signals SENSE to the sensing signal lines SENL as a kind of gate lines.

The controller 150 can control the data driving circuit 120, the first gate driving circuit 130 and the second gate driving circuit 140.

The controller 150 supplies various driving control signals DCS and GCS to the data driving circuit 120, the first gate driving circuit 130 and the second gate driving circuit 140, thereby controlling the data driving of the data driving circuit 120 and the first gate driving circuit 130 and the gate driving of the second gate driving circuit 140.

The controller 150 starts scanning according to the time point when each frame is executed, converts the input image data input from the outside into a format that conforms to the data signal used by the data driving circuit 120, outputs the converted image data DATA, and performs The time controls the data drive according to the scanning situation.

The controller 150 receives various timing signals from the outside (such as a host system) including a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, an input data enable (DE) signal, a clock signal CLK, etc., and the input image data .

The controller 150 converts the input image data input from the outside into a format conforming to the data signal used by the data drive circuit 120, and outputs the converted image data, and in order to control the data drive circuit 120 and the first gate drive circuit 130 and the second gate driving circuit 140. The controller 150 further receives, for example, a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, a data enable (DE) signal, a clock signal CLK, etc. The timing signal generates various control signals DCS and GCS, and outputs these control signals to the data driving circuit 120, the first gate driving circuit 130, and the second gate driving circuit 140.

For example, in order to control the first and second gate driving circuits 130 and 140, the controller 150 outputs a variety of gate control signals GCS, including a gate start pulse (GSP) and a gate offset Clock (gate shift clock, GSC), a gate output enable signal (GOE), etc.

In this case, the gate start pulse (GSP) controls the operation start time point of one or more gate drive integrated circuits constituting each of the first and second gate drive circuits 130 and 140. The gate shift clock (GSC), which is a clock signal commonly input to one or more gate drive integrated circuits, controls the shift time point of a scan signal (gate pulse). The gate output enable signal (GOE) specifies the timing information of one or more gate drive integrated circuits.

In addition, in order to control the data driving circuit 120, the controller 150 outputs a variety of driving control signals DCS, including a source start pulse (SSP), a source sampling clock (SSC), and a source Output enable signal (source output enable signal, SOE), etc.

In this case, the source start pulse (SSP) controls the data sampling start time point of one or more source drive integrated circuits constituting the data drive circuit 120. The source sampling clock (SSC) is a clock signal used to control the sampling data at each source drive integrated circuit. The source output enable signal (SOE) controls the output time point of the data driving circuit 120.

The controller 150 may be implemented as a separate component of the data driving circuit 120, or may be integrated with the data driving circuit 120 into an integrated circuit.

The data driving circuit 120 receives the image data DATA from the controller 150 and supplies a data voltage to the data lines DL, thereby driving the data lines DL. Here, the data driving circuit 120 can also be referred to as a “source driving circuit”.

The data driving circuit 120 may be implemented in a manner including one or more source-driven integrated circuits (SDICs).

Each source driver integrated circuit (SDIC) can include an offset register, a latch circuit, a digital-to-analog converter (DAC), an output buffer, etc. .

Each source drive integrated circuit (SDIC) may further include an analog-to-digital converter (ADC) in some cases.

Each source drive integrated circuit (SDIC) can be connected to the display panel 110 by tape automated bonding (TAB) or chip-on-glass (COG) A bonding pad may be directly placed on the display panel 110, and in some cases, the source drive integrated circuit (SDIC) may be integrated and placed on the display panel 110. In addition, each source drive integrated circuit (SDIC) can be implemented by flip-chip bonding technology (chip-on-film, COF), and in this case, each source drive integrated circuit (SDIC) can Installed on a film connected to the display panel 110.

The first gate driving circuit 130 sequentially drives the scan signal lines SCL by sequentially supplying a plurality of scan signals to the scan signal lines SCL. Under the control of the controller 150, the first gate driving circuit 130 can output a scan signal with a turn-on level voltage or a scan signal with a turn-off level voltage.

The second gate driving circuit 140 sequentially drives the sensing signal lines SENL by sequentially supplying a plurality of sensing signals to the sensing signal lines SENL. Under the control of the controller 150, the second gate driving circuit 140 can output a sensing signal with a turn-on level voltage or a sensing signal with a turn-off level voltage.

The scanning signal lines SCL and the sensing signal lines SENL are equivalent to multiple gate lines. The scanning signal and the sensing signal are equivalent to a plurality of gate signals applied to a gate node of a transistor.

The first and second gate driving circuits 130 and 140 may be implemented by including at least one gate driver integrated circuit (GDIC). Each gate drive integrated circuit (GDIC) may include an offset register, a level shifter, and so on.

Each gate drive integrated circuit (GDIC) can be connected to the display panel 110 by tape automated bonding (TAB) or chip-on-glass (COG) A bonding pad may be directly placed on the display panel 110 in the form of a GIP circuit (gate in panel), and in some cases, the gate drive integrated circuit (GDIC) may be integrated and placed on the display panel 110. In addition, each gate drive integrated circuit (GDIC) can be implemented by flip-chip bonding technology (chip-on-film, COF), and in this case, each gate drive integrated circuit (GDIC) can be Installed on a film connected to the display panel 110.

When a specific scan signal line SCL is turned on by the first gate driving circuit 130, the data driving circuit 120 converts the image data DATA received from the controller 150 into an analog data voltage and supplies the analog data voltage to the data lines DL.

The data driving circuit 120 may be placed on only one side (for example, the upper side or the lower side) of the display panel 110, or in some cases may be placed on both sides (for example, the upper side and the lower side) of the display panel 110, depending on a driving Method, one-panel design method, etc.

The first and second gate driving circuits 130 and 140 can be placed on only one side of the display panel 110 (such as the left side or the right side), or in some cases can be placed on both sides of the display panel 110 (such as the left side and the right side) ), depending on a driving method, a panel design method, etc.

The controller 150 may be a timing controller used in general display technology, or may be a control device including the timing controller and capable of performing other control functions including the timing controller. Optionally, the controller 150 may be a control device outside the timing controller, or may be a circuit in the control device. The controller 150 can be, for example, an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), an Various circuits or electronic components such as processors are implemented.

The controller 150 can be installed on a printed circuit board, a flexible printed circuit board, etc., and can be electrically connected to the data drive circuit 120, the first gate drive circuit 130, and the second gate drive circuit 130 through the printed circuit board, the flexible printed circuit board, etc. Gate driving circuit 140.

The controller 150 can use one or more predetermined interfaces to transmit multiple signals to the data drive circuit 120 and receive multiple signals from the data drive circuit 120. For example, the interfaces may include a low-voltage differential signaling (LVDS) interface, an embedded panel interface (EPI), and a serial peripheral interface (SPI) Wait.

The controller 150 can use one or more predetermined interfaces to transmit multiple signals to the first gate drive circuit 130 and the second gate drive circuit 140, and receive from the first gate drive circuit 130 and the second gate drive circuit 140 Multiple signals. For example, the interfaces may include a low-voltage differential signaling (LVDS) interface, an embedded panel interface (EPI), and a serial peripheral interface (SPI) Wait. The controller 150 may include a storage unit such as one or more registers.

The display device 100 according to the embodiment of the present invention may be any type of display including a light-emitting unit in one sub-pixel SP. For example, the display device 100 according to the embodiment of the present invention may be an OLED display, and in this case, a light-emitting unit in the sub-pixel SP includes an organic light-emitting diode (OLED), or may be It is an LED display. At this time, a light-emitting unit in the sub-pixel SP includes a light-emitting diode (LED).

FIG. 2 is an iso-calibration circuit diagram of the sub-pixel SP placed on the display panel 110 of the display device 100 according to an embodiment of the present invention.

Referring to FIG. 2, each of the plurality of sub-pixels SP may include a light-emitting unit EL, three transistors DT, SCT, and SENT, and a capacitor Cst. This sub-pixel structure is called "3T (tansistors) 1C (capacitor) structure".

The three transistors DT, SCT, and SENT may include a driving transistor DT, a scanning transistor SCT, and a sensing transistor SENT.

The light emitting unit EL may include a first electrode, a second electrode, and so on. In the light-emitting unit EL, the first electrode may be an anode or a cathode, and the second electrode may be a cathode or an anode. In the light-emitting unit EL of FIG. 2, the first electrode is an anode corresponding to a pixel electrode provided in each sub-pixel SP, and the second electrode is a cathode electrode, which is applied with a voltage corresponding to a common voltage Reference voltage EVSS.

For example, the light emitting unit EL may be an organic light emitting diode (OLED) including a first electrode, a light emitting layer and a second electrode, or may be implemented by a light emitting diode (LED) or the like .

The driving transistor DT is a transistor used to drive the light-emitting unit EL, and may include a first node N1, a second node N2, a third node N3, and so on.

The first node N1 of the driving transistor DT can be a gate node, and can be electrically connected to a source node or a drain node of the scanning transistor SCT.

The second node N2 of the driving transistor DT can be a source node or a drain node, can be electrically connected to a source node or a drain node of the sensing transistor SENT, and can also be electrically connected to the light emitting The first electrode of the cell EL.

The third node N3 of the driving transistor DT can be electrically connected to a driving voltage line DVL that supplies a driving voltage EVDD.

The scanning transistor SCT can be turned on or off according to a plurality of scanning signals SCAN supplied by the scanning signal line SCL, thereby controlling a connection relationship between the data line DL and the first node N1 of the driving transistor DT.

The scanning transistor SCT can be turned on by a scanning signal SCAN having a turn-on level voltage, and can then transmit the data voltage Vdata supplied through the data line DL to the first node N1 of the driving transistor DT.

The sensing transistor SENT can be turned on or off according to a plurality of sensing signals SENSE supplied by the sensing signal line SENL, thereby controlling a connection relationship between the reference line RL and the second node N2 of the driving transistor DT.

The sensing transistor SENT can be turned on by a sensing signal SENSE having a turn-on level voltage, and thus the reference voltage Vref supplied through the reference line RL can be transmitted to the second node N2 of the driving transistor DT.

In addition, the sensing transistor SENT can be turned on by a sensing signal SENSE having a turn-on level voltage, and can transmit the voltage of the second node N2 of the driving transistor DT to the reference line RL.

The function of the sensing transistor SENT to transmit the voltage of the second node N2 of the driving transistor DT to the reference line RL can be used to sense multiple characteristic values of the driving transistor DT (such as a threshold voltage, carrier mobility, etc.) ). In this case, the voltage transmitted to the reference line RL can be used to calculate the characteristic value of the driving transistor DT.

The function of the sensing transistor SENT to transmit the voltage of the second node N2 of the driving transistor DT to the reference line RL can also be used to sense multiple characteristic values (such as a threshold voltage) of the light-emitting unit EL. In this case, the voltage transmitted to the reference line RL can be used to calculate the characteristic value of the light-emitting unit EL.

The driving transistor DT, the scanning transistor SCT and the sensing transistor SENT can each be an n-type transistor or a p-type transistor. After this, for the convenience of description, we assume that the driving transistor DT, the scanning transistor SCT, and the sensing transistor SENT are each an n-type transistor.

The capacitor Cst can be connected between the first node N1 and the second node N2 of the driving transistor. The capacitor Cst has a plurality of charges corresponding to the voltage difference between the two plates, and plays a role of maintaining the voltage difference between the two plates for a predetermined frame time. Accordingly, a corresponding sub-pixel SP can emit light for a predetermined time.

The capacitor Cst can be an external capacitor deliberately designed outside the driving transistor DT, rather than a parasitic capacitance of an internal capacitor existing between the source node and the drain node of the driving transistor (such as Cgs or Cgd). ).

FIG. 3 is a schematic diagram of the display device 100 according to an embodiment of the present invention.

Referring to FIG. 3, each gate drive integrated circuit GDIC can be mounted on a thin film GF connected to the display panel 110. In this case, the flip chip bonding technology (COF) is used to implement.

Each source drive integrated circuit SDIC can be mounted on a thin film SF connected to the display panel 110. In this case, the flip chip bonding technology (COF) is used to implement.

In order to connect multiple source drive integrated circuits SDIC and multiple other devices, the display device 100 may include at least one source printed circuit board SPCB and a control printed circuit board CPCB, on which multiple control parts and All kinds of electronic devices.

The film SF on which the source drive integrated circuit SDIC is mounted can be connected to at least one source printed circuit (SPCB). That is, the film SF on which the source drive integrated circuit SDIC is mounted can be electrically connected to the display panel 110 on one side, and can be electrically connected to the source printed circuit board SPCB on the other side.

The controller 150 used to control the operation of the data driving circuit 120, the gate driving circuit 130, etc., is used to supply various voltages or currents to the display panel 110, the data driving circuit 120, the gate driving circuit 130, or to control various types of A power management integrated circuit (PMIC) 310 for supplying voltage or current can be mounted on the control printed circuit board CPCB.

The at least one source printed circuit board SPCB and the control printed circuit board CPCB can be connected in the circuit through at least one connector. Here, the connecting member may be, for example, a flexible printed circuit (FPC), a flexible flat circuit (FFC), etc.

At least one source printed circuit board SPCB and control printed circuit board CPCB can be integrated into a single printed circuit board.

The display device 100 may further include a setting board 330 electrically connected to the control printed circuit board CPCB. The setting board 330 may also be referred to as a "power board".

The setting board 330 may have a main power management circuit (M-PMC) 320 for managing the overall power of the display device 100.

The power management integrated circuit 310 manages the power of a display module, the display module includes the display panel 110, the driving circuits 120, 130 and 140, etc., and the main power management circuit 320 manages the overall power including the display module, and It can be interlocked with the power management integrated circuit 310.

FIG. 4 shows a fake data insertion (FDI) drive of the display device 100 according to an embodiment of the present invention. FIG. 5 and FIG. 6 are the driving timing diagrams of the dummy data insertion driving and the overlapping driving of the display device 100 according to the embodiment of the present invention.

The plurality of sub-pixels SP may be arranged on the display panel 110 in the form of a matrix. That is, the display panel 110 has a plurality of sub-pixel rows...R(n+1), R(n+2), R(n+3), R(n+4), R(n+5)..., displaying The panel 110 has a plurality of straight rows.

The sub-pixel rows...R(n+1), R(n+2), R(n+3), R(n+4), R(n+5)... can be scanned sequentially.

In the case that each sub-pixel SP has the 3T1C structure, the scanning signal line SCL for transmitting the scanning signal SCAN and the sensing signal line SENL for transmitting the sensing signal SENSE can each be arranged in the sub-pixel rows... Each column of R(n+1), R(n+2), R(n+3), R(n+4), R(n+5)...

The display panel 110 may have a plurality of sub-pixels in a row, and the data line DL may be arranged in a row in each sub-pixel in a one-to-one correspondence. In some cases, a data line DL may be arranged in a straight line for every two or three rows of sub-pixels.

As the above-mentioned sub-pixel driving operation, when the sub-pixel rows...R(n+1), R(n+2), R(n+3), R(n+4), R(n+5)... When the (n+1)th sub-pixel row R(n+1) is driven, a scan signal SCAN and a sensing signal SENSE are applied to the (n+1)th sub-pixel row R( n+1) the sub-pixels SP, and through the data lines DL, a plurality of image data voltages Vdata are supplied to the (n+1)th sub-pixel row R(n+1) arranged These sub-pixels SP.

Subsequently, the (n+2)th sub-pixel row R(n+2) located after the (n+1)th sub-pixel row R(n+1) is driven. A scanning signal SCAN and a sensing signal SENSE are applied to the sub-pixels SP arranged in the (n+2)th sub-pixel row R(n+2), and through the data lines DL, multiple images The image data voltage Vdata is supplied to the sub-pixels SP arranged in the (n+2)th sub-pixel row R(n+2).

In this way, the sub-pixels are arranged in sequence...R(n+1), R(n+2), R(n+3), R(n+4), R(n+5)... Perform image data writing operations. This image data writing operation is a procedure in an image data writing step in the above-mentioned sub-pixel driving operation.

According to the above-mentioned sub-pixel driving operation, the sub-pixel rows...R(n+1), R(n+2), R(n+3), R( n+4), R(n+5)...Execute image data writing step, boosting step and light emitting step.

At the same time, as shown in Figure 4, in a single frame time, according to the sub-pixel rows...R(n+1), R(n+2), R(n+3), R(n+ 4) The light-emission period EP of the light-emission step of the sub-pixel driving operation performed by each of R(n+5)... does not last to the end. Here, the light-emitting period EP can be referred to as a "real image period".

The real display drive can be executed in part of the single frame time, and the fake display drive can be executed in the remaining part of the single frame time in these sub-pixel rows...R(n+1), R(n+2), R( n+3), R(n+4), R(n+5)...

In a single frame time, a sub-pixel SP emits light through the actual display drive (image data writing step, boosting step, and light emitting step) during the light emitting period EP corresponding to a part of the single frame time, and then emits light in the single frame During the remaining period other than the light-emitting period EP during the time, no light is emitted through the false display driving. The period during which the sub-pixel SP does not emit light within a single frame time can be referred to as a "non-light emitting period NEP".

The fake display drive system is used to display multiple images (multiple fake images), which is different from the real display drive used to display multiple real images. Fake display driving can be realized by inserting multiple fake images between multiple real images. Therefore, the fake display driver can also be called "fake data insertion (FDI) driver". After that, the fake display driver will be described as "fake data insertion driver".

During the real display driving period, a plurality of image data voltages Vdata corresponding to a plurality of real images are supplied to the sub-pixels SP to display a plurality of real images. On the other hand, during the fake data insertion drive, the fake data voltage Vfake corresponding to a fake image is supplied to one or more sub-pixels SP, wherein the fake image has no relationship with the real image.

That is, the image data voltage Vdata supplied to the sub-pixels SP during the normal real display driving period may vary depending on the frame or the images. As for the supply to one or more sub-pixels during the dummy data insertion driving period The false data voltage Vfake of the pixel SP can remain unchanged, and does not change depending on the frame or the images.

As one of the above-mentioned dummy data insertion driving methods, dummy data insertion driving can be performed for one sub-pixel row first, and then for a subsequent sub-pixel row.

Alternatively, as another method of dummy data insertion driving described above, dummy data insertion driving can be performed on multiple sub-pixel rows at the same time, and then can be performed on subsequent multiple sub-pixel rows. In other words, the dummy data insertion drive can be performed on multiple units of sub-pixel rows at the same time. For example, the number (k) of a plurality of sub-pixel rows simultaneously performing dummy data insertion driving may be 2, 4, 8, etc.

4-6, a real image data writing operation sequentially performs sub-pixel rows R(n+1), R(n+2), R(n+3) and R(n+4) After that, a dummy data writing operation can be performed on the k sub-pixel rows arranged before the sub-pixel row R(n+1) and in which a predetermined light-emitting period EP has passed.

Sequentially, after the real image data writing operation is sequentially performed on the sub-pixel rows R(n+5), R(n+6), R(n+7) and R(n+8), you can A dummy data writing operation is simultaneously performed on the k sub-pixel rows arranged before the sub-pixel row R(n+5) and in which a predetermined light-emitting period EP has passed.

The multiple numbers (k) of the multiple sub-pixel rows that are driven by the dummy data insertion at the same time may be the same or different. For example, the dummy data insertion drive can be performed on the first two sub-pixel rows at the same time, and then can be performed on the unit of 4 sub-pixel rows at the same time. For another example, the dummy data insertion drive can be simultaneously performed on the first 4 sub-pixel rows, and then can be simultaneously performed on the unit of 8 sub-pixel rows.

By displaying the real image data and the fake data on the same frame through the fake data insertion driver, it is possible to avoid the blurring phenomenon of multiple unclear and dragged images, thereby improving the image quality.

During the above-mentioned dummy data insertion drive, a real image data writing operation and a dummy data writing operation can be performed through the data line DL.

In addition, as mentioned above, the dummy data writing operation can be performed on multiple sub-pixel rows at the same time, thereby compensating for the brightness difference caused by the difference in the emission period EP between the positions of the multiple sub-pixel rows, and saving image data writing time.

At the same time, by adjusting the time point at which the dummy data is inserted and driven, the length of the light-emitting period EP can be adjusted adaptively depending on the image.

Through the control of the gate drive, there may be changes in the time point of image data writing and the time point of false data writing.

For example, the fake data voltage Vfake can be a black data voltage Vblack or a low grayscale data voltage.

If the dummy data voltage Vfake is a black data voltage Vblack, the dummy data insertion driving can also be referred to as "black data insertion (BDI) driving". In the case of fake data being inserted into the drive, the fake data writing can be referred to as "black data writing".

The period during which the k rows of sub-pixels do not emit light due to false data insertion driving can be referred to as "non-light emitting period NEP" or "black image period".

At the same time, when the time overlaps in a predetermined period, the sub-pixel rows can be...R(n+1), R(n+2), R(n+3), R(n+4), Each of R(n+5)... performs the gate drive in sequence.

Referring to Fig. 6, in the overlapping driving, each of these sub-pixel rows is included...R(n+1), R(n+2), R(n+3), R(n+4), R( n+5)... The scanning transistor SCT and the sensing transistor SENT can be turned on or off at the same time. In other words, in an overlapping drive, each is applied to each of the sub-pixel rows...R(n+1), R(n+2), R(n+3), R(n+4) , R(n+5)... Among the scanning transistor SCT and the sensing transistor SENT, a scanning signal SCAN and a sensing signal SENSE can be the same in a range with a conduction level voltage at the same time Gate signal.

According to the embodiment of FIG. 5 and FIG. 6, it is supplied to each of the sub-pixel rows...R(n+1), R(n+2), R(n+3), R(n+4), R The length of the interval of the turn-on level voltages of the gate signals SCAN and SENSE of (n+5)... can be, for example, 2 hours (H).

According to the embodiment of FIG. 5 and FIG. 6, it is supplied to each of the sub-pixel rows...R(n+1), R(n+2), R(n+3), R(n+4), R (n+5)... The intervals of the on-level voltages of the two gate signals SCAN and SENSE can overlap with each other.

The gate signal supplied to each of these sub-pixel rows...R(n+1), R(n+2), R(n+3), R(n+4), R(n+5)... The length of this interval of the on-level voltages of SCAN and SENSE can both be 2H.

The interval ( 2H), which can be connected to the scan signal SCAN and the conduction position of the sensing signal SENSE of the scanning transistor SCT and the sensing transistor SENT respectively applied to the sub-pixels SP arranged in the sub-pixel row R(n+2) The quasi-voltage interval (2H) overlaps 1H.

The interval ( 2H), which can be connected to the scan signal SCAN and the conduction position of the sensing signal SENSE of the scanning transistor SCT and the sensing transistor SENT respectively applied to the sub-pixels SP arranged in the sub-pixel row R(n+3) The quasi-voltage interval (2H) overlaps 1H.

The interval ( 2H), which can be connected to the scanning signal SCAN and the conduction position of the sensing signal SENSE of the scanning transistor SCT and the sensing transistor SENT respectively applied to the sub-pixels SP arranged in the sub-pixel row R(n+4) The quasi-voltage interval (2H) overlaps 1H.

According to the embodiments of FIGS. 5 and 6, the intervals of the on-level voltages of the two gate signals SCAN and SENSE in each sub-pixel row may be 2H, and the two-gate signals of two adjacent sub-pixel rows The intervals of the on-level voltages of SCAN and SENSE can overlap each other by 1H.

The above gate driving method is called "overlapping driving", and if the turn-on level voltages of the two gate signals SCAN and SENSE in each sub-pixel row are 2H, as shown in Figures 5 and 6, this It can also be called "2H overlap drive".

In addition to the 2H overlap drive, the overlap drive can be modified in any form.

As another embodiment of overlapping driving, the intervals of the on-level voltages of the two gate signals SCAN and SENSE in each sub-pixel row may be 3H, and the two gates in two adjacent sub-pixel rows The intervals of the conduction level voltages of the signals SCAN and SENSE can overlap each other by 2H.

As another embodiment of overlapping driving, the intervals of the on-level voltages of the two gate signals SCAN and SENSE in each sub-pixel row may be 3H, and the two gates in two adjacent sub-pixel rows The intervals of the on-level voltages of the signals SCAN and SENSE can overlap each other by 1H.

As another embodiment of overlapping driving, the intervals of the on-level voltages of the two gate signals SCAN and SENSE in each sub-pixel row may be 4H, and the two gates in two adjacent sub-pixel rows The intervals of the conduction level voltages of the signals SCAN and SENSE can overlap each other by 3H.

Although the above-mentioned overlapping driving may be different, for the convenience of description hereinafter, 2H overlapping driving will be used as an example of description.

During the above 2H overlapping driving period, each sub-pixel row...R(n+1), R(n+2), R(n+3), R(n+4), R(n+5)... The front part (with a length of 1H) of the interval (with a length of 2H) of the conduction level voltages of the two gate signals SCAN and SENSE is used for a gate signal part of the precharge (PC) drive. In the gate signal part, a data voltage (which serves as a precharge data voltage) is applied to the corresponding sub-pixel. The rear part of the interval (with a length of 1H) of the on-level voltages of the two gate signals SCAN and SENSE in each sub-pixel row is a gate signal part that enables an image data writing operation. In the gate signal part, a real image data voltage Vdata is applied to the corresponding sub-pixel.

Through the above-mentioned overlapping driving, it is possible to improve the charging rate of each sub-pixel, thereby improving the image quality.

If the above-mentioned dummy data insertion driving and overlapping driving are both performed, the interval of the on-level voltages of the two gate signals SCAN and SENSE of the sub-pixel row R(n+3) overlaps the sub-pixel row R(n+4) The range of the conduction level voltage of the two gate signals SCAN and SENSE.

In this case, the interval of the on-level voltages of the two gate signals SCAN and SENSE in the sub-pixel row R(n+3) with 1H overlaps the subsequent sub-pixel row R(n+4) The interval of the on-level voltages of the two gate signals SCAN and SENSE, in which the image data is written to the sub-pixel row R(n+3). In the sub-pixel row R(n+4), the front part of the interval of the on-level voltages of the two gate signals SCAN and SENSE with 1H corresponds to a precharge driving period. In addition, before the dummy data insertion drive is performed, the image data writing operation is performed on the sub-pixel rows R(n+3) and R(n+4).

In addition, the interval between the on-level voltages of the two gate signals SCAN and SENSE in the sub-pixel row R(n+5) and the on-level voltage of the two-gate signals SCAN and SENSE in the sub-pixel row R(n+6) The voltage intervals overlap.

In this case, the turn-on level voltages of the two gate signals SCAN and SENSE in the sub-pixel row R(n+5) have 1H at the back of the sub-pixel row R(n+6). In this interval of the on-level voltages of the two gate signals SCAN and SENSE, one of the image data writing operations is performed in the sub-pixel row R(n+5). The front part of the interval with the 1H of the turn-on level voltages of the two gate signals SCAN and SENSE in the sub-pixel row R(n+6) corresponds to a precharge driving period. In addition, before the dummy data insertion drive is performed, the image data writing operation is performed on the sub-pixel rows R(n+5) and R(n+6).

However, the interval between the on-level voltages of the two gate signals SCAN and SENSE in the sub-pixel row R(n+4) and the on-state of the two gate signals SCAN and SENSE in the subsequent sub-pixel row R(n+5) The intervals of the level voltage do not overlap.

In the sub-pixel row R(n+4), the interval of the on-level voltages of the two gate signals SCAN and SENSE with 1H corresponds to the image data writing operation to the sub-pixel row R(n+4) Period.

In the sub-pixel row R(n+4), the interval of the turn-on level voltages of the two gate signals SCAN and SENSE has a 1H back period, and it will not match the subsequent sub-pixel row R(n+5) Carry out pre-charge drive.

Based on the dummy data insertion period, immediately before the dummy data insertion driving, the image data writing operation is performed on the sub-pixel row R(n+4), and immediately after the dummy data insertion driving, the sub-pixel row R (n+5) Perform image data writing operation.

The interval between the on-level voltages of the two-gate signals SCAN and SENSE in the sub-pixel row R(n+4) and the on-level voltages of the two-gate signals SCAN and SENSE in the subsequent sub-pixel row R(n+5) The voltage interval is divided by the period during which the dummy data is inserted and driven.

In FIGS. 5 and 6, the graph labeled Vg shows the voltage of the first node N1 of the driving transistor DT of the sub-pixels included in the sub-pixel row, and shows that the voltage of the first node N1 in the sub-pixel driving operation is entered. The change of the voltage state before the step.

Referring to FIGS. 5 and 6, the graph labeled Vs shows the voltage of the first node N2 of the driving transistor DT of the sub-pixels included in the sub-pixel row, and shows the voltage before entering the boosting step of the sub-pixel driving operation The voltage state changes.

Referring to the graphs marked Vg in FIG. 5 and FIG. 6, in the remaining period other than the period during which the dummy data insertion driving is performed, the first driving transistors DT of the sub-pixels included in the sub-pixel rows The voltage Vg of a node N1 becomes the image data voltage Vdata according to the image data writing operation.

However, while the dummy data insertion driving is in progress, the voltage Vg of the first node N1 of the driving transistor DT of the sub-pixels included in the sub-pixel row becomes the dummy data voltage Vfake, and the dummy data insertion driving the sub-pixels Performed in rows.

At the same time, as mentioned above, the turn-on level voltages of the two gate signals SCAN and SENSE in each of the sub-pixel rows R(n+1), R(n+2), and R(n+3) The latter period of the interval overlaps the front period of the interval of the on-level voltages of the two gate signals SCAN and SENSE in the subsequent sub-pixel row. However, the on-level voltages of the two gate signals SCAN and SENSE in the sub-pixel row R(n+4) are different from the two-gate signal SCAN in the sub-pixel row R(n+5) in the latter period of the interval. And the on-level voltage of SENSE overlap the front period of the interval.

Therefore, in each sub-pixel row R(n+1), R(n+2), and R(n+3), the interval of the on-level voltages of the two gate signals SCAN and SENSE is included in each sub-pixel row. The voltage Vs of the second node N2 of the driving transistor DT of a plurality of sub-pixels in a sub-pixel row R(n+1), R(n+2) and R(n+3) becomes similar to that of image data writing The voltage Vref+∆V of the reference voltage Vref in the step. At this time, the potential difference Vgs between the first node N1 and the second node N2 of each driving transistor DT is Vdata-(Vref+ΔV).

In the 1H period immediately before the dummy data insertion period, that is, in the rear period of the interval of the on-level voltages of the two gate signals SCAN and SENSE in the sub-pixel row R(n+4) (which does not overlap the sub-pixel In the first period of the interval between the on-level voltages of the two gate signals SCAN and SENSE in the row R(n+5), the driving circuits of the plurality of sub-pixels included in the sub-pixel row R(n+4) The voltage Vs of the second node N2 of the crystal DT can become a voltage Vref+∆(V/2) lower than the voltage Vref+∆V.

Therefore, compared to the potential difference {Vdata-(Vref+∆V)} in the previous period, the potential difference Vgs{Vgs(4)} between the first node N1 and the second node N2 of each drive transistor DT is increased to Vdata- [Vref+∆(V/2)].

FIG. 7 is a schematic diagram illustrating the brightness defect that occurs on a specific line when the display device 100 of the embodiment of the present invention performs dummy data insertion driving and overlapping driving.

As mentioned above, when overlapping driving and dummy data insertion driving are performed at the same time, the potential difference Vgs between the first node N1 and the second node N2 of each driving transistor DT is suddenly in the sub-pixel rows (for example, R(n) +4), R(n+8), etc.). Overlapping driving can’t be placed in these sub-pixel rows (for example, R(n+4), R(n+8), etc.) immediately before the dummy data is inserted into the drive. ).

Therefore, as shown in FIG. 7, the sub-pixel rows (for example, R(n+4), R(n+8), etc.) that perform the image data writing operation immediately before the dummy data insertion drive are abnormal Is presented in the form of a bright line 700.

According to the above-mentioned embodiments of the present invention, even if the false data insertion drive can avoid the blurring of the screen, and the overlap drive can improve the charging rate of each sub-pixel, if the false data insertion drive and the overlap drive are performed at the same time, it cannot be expected. As a side effect, brightness defects will be observed on multiple specific lines.

The analysis confirmed that the brightness defect of a specific circuit is caused by the following substantial reasons. The substantial cause of the brightness defect of a specific line will be described with reference to FIG. 8.

FIG. 8 is a schematic diagram illustrating the cause of the brightness defect that occurs on a specific line when the display device 100 of the embodiment of the present invention performs false data insertion driving and overlapping driving.

FIG. 8 is a drawing of the first sub-pixel Spa placed in the sub-pixel row R(n+3), the second sub-pixel Spb placed in the sub-pixel row R(n+4) and the placement in FIG. 5 and FIG. A schematic diagram of the driving operation of the third sub-pixel Spc in the sub-pixel row R(n+5).

Referring to FIG. 8, the first sub-pixel Spa placed in the sub-pixel row R(n+3), the second sub-pixel Spb placed in the sub-pixel row R(n+4), and the sub-pixel row R( The third sub-pixels Spc of n+5) are arranged in the same straight row, and are electrically connected to the same data line DL and the same reference line RL.

In other words, the first sub-pixel Spa placed in the sub-pixel row R(n+3), the second sub-pixel Spb placed in the sub-pixel row R(n+4), and the sub-pixel row R( In general, the drain nodes or source nodes of the third sub-pixel Spc of n+5) can be electrically connected to the data line DL.

Referring to FIGS. 5, 6 and 8, when the image data writing operation is performed on the first sub-pixel Spa placed in the sub-pixel row R(n+3), the scanning included in the first sub-pixel Spa The transistor SCT is turned on by the scan signal SCAN having a turn-on level voltage. Therefore, the image data voltage Vdata supplied to the data line DL is transmitted to the first node N1 corresponding to the gate node of the driving transistor DT through the turned-on scanning transistor SCT.

At this time, the sensing transistor SENT included in one of the sub-pixels Spa is turned on by the sensing signal SENSE having a turn-on level voltage, so that the reference voltage Vref supplied to the reference line RL passes through the turned-on The sensing transistor SENT is transmitted to the second node N2 corresponding to the source node of the driving transistor DT.

When the image data writing operation is performed on the first sub-pixel Spa placed in the sub-pixel row R(n+3) according to the 2H overlap drive, the second sub-pixel Spa placed in the subsequent sub-pixel row R(n+4) A pre-charge driving can be performed on the sub-pixel Spb.

That is, when the image data writing operation is performed on the first sub-pixel Spa placed in the sub-pixel row R(n+3), the scan signal SCAN of the on-level voltage is applied to the first sub-pixel Spa placed in the sub-pixel row. The second sub-pixel Spb of R(n+4), and the image data voltage Vdata supplied to the data line DL is used as a precharge voltage, and is applied to the first node N1 through the turned-on scanning transistor SCT. A node N1 is a gate node of the driving transistor DT of the second sub-pixel Spb.

At this time, the sensing transistor SENT included in the second sub-pixel Spb placed in the sub-pixel row R(n+4) is combined with the scanning transistor SCT through the sensing signal SENSE having a turn-on level voltage Is turned on, so that the reference voltage Vref supplied to the reference line RL is transmitted to the second node N2 corresponding to the source node of the driving transistor DT through the turned-on sensing transistor SENT.

When an image data writing operation is performed on the first sub-pixel Spa placed in the sub-pixel row R(n+3), a current id supplied to the first sub-pixel Spa and supplied to the second sub-pixel Spb The combined current 2id formed by the combination of a current id flows through the reference line RL.

Therefore, the line capacitance provided in the data line RL can be charged by the current 2id flowing through the reference line RL, thereby increasing the voltage of the reference line RL. The increased voltage of this reference line RL can be transmitted to the second node N2 of the driving transistor DT of the first sub-pixel Spa through the sensing transistor SENT, wherein the sensing transistor SENT is placed in the sub-pixel row R( n+3) is turned on in the first sub-pixel Spa, and at the same time, the increased voltage of the reference line RL can be transmitted to the second sub-pixel Spb's driving transistor DT through the sensing transistor SENT Two nodes N2, in which the sensing transistor SENT is turned on in the second sub-pixel Spb placed in the sub-pixel row R(n+4).

Therefore, the voltage Vs of the second node N2 of the driving transistor DT in the first sub-pixel Spa provided in the sub-pixel row R(n+3) for performing the image data writing operation increases.

At the same time, after the image data write operation performed on the first sub-pixel Spa placed in the sub-pixel row R(n+3), the sub-pixel row R(n+4) can be written The second sub-pixel Spb in the image data write operation.

When performing an image data writing operation on the second sub-pixel Spb placed in the sub-pixel row R(n+4), it is placed in the second sub-pixel Spb placed in the sub-pixel row R(n+4) The scanning transistor SCT is turned on by a scanning signal SCAN with a turn-on level voltage. Therefore, the image data voltage Vdata supplied to the data line DL is transmitted to the first node N1 corresponding to the gate node of the driving transistor DT through the turned-on scanning transistor SCT.

At this time, the sensing transistor SENT included in the second sub-pixel Spb placed in the sub-pixel row R(n+4) is combined with the scanning transistor SCT through the sensing signal SENSE having a turn-on level voltage Is turned on, so that the reference voltage Vref supplied to the reference line RL is transmitted to the second node N2 corresponding to the source node of the driving transistor DT through the turned-on sensing transistor SENT.

When the image data writing operation is performed on the second sub-pixel Spb placed in the sub-pixel row R(n+4), the precharge drive will not be placed in the sub-pixel row R(n+5) The third sub-pixel Spc is performed because the image data writing operation is performed on the second sub-pixel Spb placed in the sub-pixel row R(n+4), which corresponds to the execution of the dummy data insertion drive immediately The previous period.

Accordingly, when the image data writing operation is performed on the second sub-pixel Spb placed in the sub-pixel row R(n+4), only the current id from the second sub-pixel Spb flows through the reference line RL .

Therefore, immediately before the dummy data insertion driving, the driving transistor of the second sub-pixel Spb included in the sub-pixel row R(n+4) that performs the image data writing operation without performing overlapping driving The voltage Vs of the second node N2 of DT increases. However, the voltage increase value of the second node N2 of the second node N2 of the driving transistor DT of the second sub-pixel Spb included in the sub-pixel row R(n+4), which is not overlap-driven immediately before the dummy data insertion driving is performed The voltage increase value of the second node N2 of the driving transistor DT of the first sub-pixel Spa included in the sub-pixel row R(n+3) is smaller than that, wherein the reference line RL is caused by the decrease in the current flowing through the reference line RL The voltage increase value decreases, so the overlap driving is normally performed in the sub-pixel row R(n+3).

Therefore, immediately before the dummy data voltage Vfake is applied to the data line DL according to the dummy data insertion driving (that is, immediately before the dummy data insertion driving), the second sub-pixel row R(n+4) is placed The potential difference between the first node N1 and the second node N2 of the driving transistor DT of the pixel Spb increases rapidly.

The above-mentioned rapid increase of the potential difference Vgs may cause the bright line 700 to be displayed on the sub-pixel rows (for example, R (n+4)R, (n+12)R, (n+20)... etc.). An advanced overlapping driving method to avoid this phenomenon will be detailed below.

After that, in order to explain the advanced overlapping driving method, an example in which a plurality of sub-pixels SP and a plurality of signal lines SCL, SENL, DL, and RL are arranged on the display panel 110 will be described preferably.

9 is a drawing of a plurality of sub-pixels Sprc (r=1 to 6 and c=1 to 4) and a plurality of signal lines SCLr, DLc and RL (r=1 To 6 and c=1 to 4).

Referring to FIG. 9, 24 sub-pixels SPrc (r=1 to 6 and c=1 to 4) can be arranged in 6 horizontal columns and 4 vertical rows on the display panel 110. In other words, the 24 sub-pixels SPrc (r=1 to 6 and c=1 to 4) are arranged as 6 sub-pixel rows R(n+1), R(n+2),..., R(n+6).

Referring to FIG. 9, the 6 scan signal lines SCLr (r=1 to 6) can be arranged into 6 sub-pixel rows R(n+1), R(n+2),..., R(n+6) and correspond. The 6 sensing signal lines SENLr (r=1 to 6) can be arranged into 6 sub-pixel rows R(n+1), R(n+2),..., R(n+6) to correspond to them.

The 6 scan signal lines SCLr (r=1 to 6) supply scan signals SCANr (r=1 to 6) to 6 sub-pixel rows R(n+1), R(n+2),..., R(n +6). The 6 sensing signal lines SENLr (r=1 to 6) supply the sensing signal SENSEr (r=1 to 6) to 6 sub-pixel rows R(n+1), R(n+2),..., R (n+6).

According to the above-mentioned overlapping driving with reference to FIGS. 5 and 6, the two gate signals SCAN and SENSE supplied to the same sub-pixel row have an interval of on-level voltage at the same time.

For example, in the first sub-pixel row R(n+1), a first scan signal SCAN1 supplied to a first scan signal line SCL1 and a first scan signal SCAN1 supplied to a first sensing signal line SENL1 The sensing signal SENSE1 has a turn-on level voltage interval at the same time. In addition, in the second sub-pixel row R(n+2), a second scanning signal SCAN2 supplied to a second scanning signal line SCL2 and a second sensing signal supplied to a second sensing signal line SENL2 The signal SENSE2 has a turn-on level voltage interval at the same time. Furthermore, in the third sub-pixel row R(n+3), a third scan signal SCAN3 supplied to a third scan signal line SCL3 and a third scan signal SCAN3 supplied to a third sensing signal line SENL3 The sensing signal SENSE3 has a turn-on level voltage interval at the same time.

According to the advanced overlapping driving described later, the two gate signals SCAN and SENSE supplied to the same sub-pixel row can have a turn-on level voltage interval at different times.

Referring to FIG. 9, the 4 data lines DLc (c=1 to 4) can each be arranged in 4 sub-pixels in a straight row.

Referring to FIG. 9, a single reference line RL can supply a reference voltage Vref to the sub-pixels arranged in a straight row of 4 sub-pixels. This means that 4 sub-pixels running straight can share a reference line RL.

The following description and illustrations will be based on or follow the arrangement of the sub-pixels SPrc (r=1 to 6 and c=1 to 4) and the signal lines SCLr, SENLr, DLc and RL (c=1 to 4) in FIG. 9.

FIG. 10 is a driving timing diagram of the advanced overlapping driving of the display device 100 according to an embodiment of the present invention.

10, the plurality of sub-pixels SP may include a first scan signal line SCL1 connected to transmit a first scan signal SCAN1 and a first sensing signal line connected to transmit a first sensing signal SENSE1 A first sub-pixel SP1 of SENL1 is connected to a second scan signal line SCL2 for transmitting a second scan signal SCAN2 and to a second sensing signal line SENL2 for transmitting a second sensing signal SENSE2 Of a second sub-pixel SP2 connected to a third scan signal line SCL3 for transmitting a third scan signal SCAN3, and connected to a third sensing signal line SENL3 for transmitting a third sensing signal SENSE3 A third sub-pixel SP3...etc.

In FIG. 10, the first sub-pixel SP1 represents a plurality of sub-pixels SPrc (r=1 and c=1 to 4) arranged in the first sub-pixel row R(n+1) in FIG. 9. In FIG. 10, the second sub-pixel SP2 represents a plurality of sub-pixels SPrc (r=2 and c=1 to 4) arranged in the second sub-pixel row R(n+2) in FIG. 9. In FIG. 10, the third sub-pixel SP3 represents a plurality of sub-pixels SPrc (r=3 and c=1 to 4) arranged in the third sub-pixel row R(n+3) in FIG. 9.

Accordingly, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 are sequentially arranged in a linear direction.

9 and 10, the plurality of scan signal lines SCL may include a first scan signal SCAN1, a second scan signal SCAN2, and a third scan signal corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The scan signal SCAN3, wherein the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 are sequentially arranged on the display panel 110.

9 and 10, the plurality of sensing signal lines SENL may include a first sensing signal SENSE1 and a second sensing signal SENSE2 corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively And the third sensing signal SENSE3, wherein the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 are sequentially arranged on the display panel 110.

The drain node (or source node) of the sensing transistor SENT included in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be electrically connected to the same reference line RL.

Referring to FIG. 10, the display device 100 according to an embodiment of the present invention can perform an advanced overlap driving to control the time point of the driving period of two adjacent sub-pixel rows, so as to control the overlap of the two adjacent sub-pixel rows. The point in time or mode during driving.

Referring to FIG. 10, the display device 100 according to an embodiment of the present invention performs an advanced overlap driving to control the respective conduction levels of the scan signal SCAN and the sensing signal SENSE of the two gate signals supplied to a sub-pixel row The timing of the voltage interval.

Referring to FIG. 10, according to the advanced overlap driving, the two gate signals SCAN and SENSE supplied to the same sub-pixel row can have a turn-on level voltage interval at different times.

For example, during the advanced overlap driving period, in association with the first sub-pixel row R(n+1), the first scan signal SCAN1 supplied to the first scan signal line SCL1 and the first scan signal SCAN1 supplied to the first sensing signal line The first sensing signal SENSE1 of SENL1 does not have an interval of on-level voltage at the same time.

In addition, during the advanced overlap driving, associated with the second sub-pixel row R(n+2), the second scan signal SCAN2 supplied to the second scan signal line SCL2 and the second scan signal SCAN2 supplied to the second sensing signal line SENL2 The second sensing signal SENSE2 does not have an interval of on-level voltage at the same time.

In addition, during the advanced overlapping driving period, in association with the third sub-pixel row R(n+3), the third scan signal SCAN3 supplied to the third scan signal line SCL3 and the third scan signal SCAN3 supplied to the third sensing signal line SENL3 The third sensing signal SENSE3 does not have an interval of on-level voltage at the same time.

The characteristics of the scan signals SCAN1, SCAN2, and SCAN3 and the sensing signals SENSE1, SENSE2, and SENSE3 for advanced overlap driving will be described in detail later.

10, in the display device 100 according to an embodiment of the present invention, a first gate driving circuit 130 sequentially supplies a plurality of scan signals SCAN1, SCAN2, and SCAN3 having a turn-on level voltage interval to the array A plurality of scan signal lines SCL1, SCL2, and SCL3 on the display panel 110.

In the case that the scanning transistor SCT is an n-type transistor (a transistor with an n-type channel), as shown in Figure 10, the range of the on-level voltage of the scanning signals SCAN1, SCAN2, and SCAN3 can be the range of the high-level voltage And the interval of the turn-off level voltage of the scan signals SCAN1, SCAN2, and SCAN3 can be the interval of the low level voltage.

In the case that the scanning transistors SCT are p-type transistors (transistors with P-type channels), the intervals of the on-level voltages of the scanning signals SCAN1, SCAN2, and SCAN3 may be those of a low-level voltage. The intervals, and the intervals of the turn-off level voltages of the scan signals SCAN1, SCAN2, and SCAN3 may be the intervals of a high level voltage.

10, in the display device 100 of the embodiment of the present invention, a second gate driving circuit 140 sequentially supplies a plurality of scan signals SENSE1, SENSE2, and SENSE3 with a plurality of intervals of conduction level voltages to and A plurality of scan signal lines SENL1, SENL2, and SENL3 arranged on the display panel 110.

In the case that the sensing transistors SENT are n-type transistors (transistors with n-type channels) as shown in FIG. 10, the intervals of the turn-on level voltages of the sensing signals SENSE1, SENSE2, and SENSE3 can be a range The intervals of the high-level voltage and the turn-off level voltages of the sensing signals SENSE1, SENSE2, and SENSE3 may be the intervals of a low-level voltage.

In the case that the sensing transistors SENT are p-type transistors (transistors with p-type channels), the intervals of the turn-on level voltages of the sensing signals SENSE1, SENSE2, and SENSE3 can be a low level voltage The intervals, and the intervals of the turn-off level voltages of the sensing signals SENSE1, SENSE2, and SENSE3 may be the intervals of a high level voltage.

Referring to FIG. 10, the first gate driving circuit 130 of the display device 100 according to the embodiment of the present invention can supply the first scan signal SCAN1 in the interval with the on-level voltage to be electrically connected to the sub-pixels SP including The first sub-pixel SP1 scans the first scan signal line SCL1 of the gate node of the transistor SCT.

Referring to FIG. 10, the second gate driving circuit 140 of the display device 100 according to an embodiment of the present invention can supply the first sensing signal SENSE1 with the turn-on level voltage in the interval to be electrically connected to the first sub-pixel SP1 The first sensing signal line SENL1 of the gate node of the sensing transistor SENT. The interval is delayed from the interval of the on-level voltage of the first scan signal SCAN1 by a predetermined sensing offset time tSHIFT/SEN.

The timing of the interval of the turn-on level voltage of the first sensing signal SENSE1 can be delayed by the predetermined sensing offset time tSHIFT/SEN relative to the timing of the interval of the turn-on level voltage of the first scan signal SCAN1.

The first scan signal SCAN1 has a turn-on level voltage in advance, and therefore the scan transistor is fully turned on, so that the image data voltage Vdata is programmed. In addition, regardless of the delay in the interval of the turn-on level voltage of the first sensing signal SENSE1, by controlling the driving timing and expanding the multiple channels of the sensing transistor SENT, the sensing transistor SENT can increase the charging speed. Therefore, the charging performance can be improved.

10, the interval of the turn-on level voltage of the first sensing signal SENSE1 may include the interval of the turn-on level voltage of the first sensing signal SENSE1 overlapping the interval of the turn-on level voltage of the first scan signal SCAN1 A period OP of the first sensing signal SENSE1 and a period NOP of the period of the period of the on-level voltage of the first scanning signal SCAN1 do not overlap with the period of the on-level voltage of the first sensing signal SENSE1.

Referring to FIG. 10, the period in which the interval of the turn-on level voltage of the first sensing signal SENSE1 overlaps the interval of the turn-on level voltage of the first scan signal SCAN1 can correspond to the programming of the first sub-pixel SP1 period. "Programming" the first sub-pixel SP1 can mean that the corresponding image data is programmed onto the first sub-pixel, and it can mean that the capacitor Cst of the first sub-pixel SP1 is charged to an ideal value by the image data voltage Vdata. value.

The period in which the interval of the on-level voltage of the first sensing signal SENSE1 overlaps the interval of the on-level voltage of the first scan signal SCAN1 can correspond to the image data being programmed to a first sub-pixel SP1 TPROG during programming.

10, the start point of the interval of the turn-on level voltage of the first sensing signal SENSE1 can be delayed by the predetermined sensing offset time tSHIFT relative to the beginning point of the interval of the turn-on level voltage of the first scan signal SCAN1 /SEN.

For example, the predetermined sensing offset time tSHIFT/SEN may correspond to 1/2 of the interval of the turn-on level voltage of the first scan signal SCAN1.

Referring to FIG. 10, for example, the interval of the turn-on level voltage of the first sensing signal SENSE1 and the interval of the turn-on level voltage of the first scan signal SCAN1 have the same time length.

Accordingly, the predetermined sensing offset time tSHIFT/SEN can correspond to 1/2 of the interval of the turn-on level voltage of the first sensing signal SENSE1.

In this case, the period in which the interval of the turn-on level voltage of the first sensing signal SENSE1 overlaps the interval of the turn-on level voltage of the first scan signal SCAN1 can be offset from the predetermined sensing shift time tSHIFT/ SEN is equal.

The programming period tPROG of the first sub-pixel SP1 may be equal to the predetermined sensing shift time tSHIFT/SEN.

10, the relationship and characteristics between the second scan signal SCAN2 and the second sensing signal SENSE2 are the same as the relationship and characteristics between the first scan signal SCAN1 and the first sensing signal SENSE1 described above. The relationship and characteristics between the third scan signal SCAN3 and the third sensing signal SENSE3 are the same as the relationship and characteristics between the first scan signal SCAN1 and the first sensing signal SENSE1 described above.

Referring to FIG. 10, there may be a time point PROG2, at which time point PROG2, when the second scan signal SCAN2 with a turn-on level voltage is supplied to the gate node of the scan transistor SCT in the second sub-pixel SP2, And when the second sensing signal SENSE2 with the conduction level voltage is supplied to the gate node of the sensing transistor SENT in the second sub-pixel SP2, the sensing transistor SENT in the first sub-pixel SP1 and the third The sensing transistor SENT in the sub-pixel SP3 is turned off at the same time.

In other words, there may be a time point PROG2, at which time point PROG2, during the period when the interval of the conduction level voltage of the second scan signal SCAN2 and the interval of the conduction level voltage of the second sensing signal SENSE2 overlap , The sensing transistor SENT in the first sub-pixel SP1 and the sensing transistor SENT in the third sub-pixel SP3 are simultaneously turned off.

Referring to FIG. 10, the interval of the turn-on level voltage of the first sensing signal SENSE1 can be delayed by the predetermined sensing offset time tSHIFT/SEN relative to the interval of the turn-on level voltage of the first scan signal SCAN1. The interval of the turn-on level voltage of the first sensing signal SENSE1 can be overlapped with the interval of the turn-on level voltage of the first scan signal SCAN1 through the programming period tPROG.

10, the interval of the turn-on level voltage of the second sensing signal SENSE2 can be delayed by the predetermined sensing offset time tSHIFT/SEN relative to the interval of the turn-on level voltage of the second scan signal SCAN2. The interval of the turn-on level voltage of the second sensing signal SENSE2 can be overlapped with the interval of the turn-on level voltage of the second scan signal SCAN2 through the programming period tPROG.

Referring to FIG. 10, the interval of the turn-on level voltage of the second scan signal SCAN2 may overlap with the interval of the turn-on level voltage of the first scan signal SCAN1. The interval of the turn-on level voltage of the second scan signal SCAN2 may be delayed from the interval of the turn-on level voltage of the first sensing signal SENSE1 by a predetermined scan offset time tSHIFT/SCAN.

Referring to FIG. 10, the interval of the turn-on level voltage of the second sensing signal SENSE2 may not overlap with the interval of the turn-on level voltage of the first scan signal SCAN1.

Referring to FIG. 10, during the period in which the interval of the on-level voltage of the second scan signal SCAN2 overlaps with the interval of the on-level voltage of the second sensing signal SENSE2, the third sensing signal SENSE3 may have a pass Break level voltage.

During the programming period tPROG of the second sub-pixel SP2, the third sensing signal SENSE3 may have the turn-off level voltage.

The first sensing signal SENSE1 can be switched from the on-level voltage to the off before the end of the period in which the interval of the on-level voltage of the second scan signal SCAN2 and the interval of the on-level voltage of the second sensing signal SENSE2 overlap. Break level voltage.

According to the above description, both the first sensing signal SENSE1 and the third sensing signal SENSE3 can overlap in the interval of the on-level voltage of the second scan signal SCAN2 and the interval of the on-level voltage of the second sensing signal SENSE2. This period (ie, the programming period tPROG of the second sub-pixel SP2) has the turn-off level voltage at a specific point PROG2.

In other words, the sensing transistor SENT in the first sub-pixel SP1 and the sensing transistor SENT in the third sub-pixel SP3 can both be in the same interval as the second sensing transistor SENT in the turn-on level voltage of the second scan signal SCAN2. The specific point PROG2 in the period (ie, the programming period tPROG of the second sub-pixel SP2) during which the period of the on-level voltage of the signal SENSE2 overlaps is in an off state.

Accordingly, when the target for programming is the second sub-pixel SP2, the second sub-pixel SP2 to be programmed among the first to third sub-pixels SP1, SP2, and SP3 is turned on. The induction transistor SENT is electrically connected to the second node N2 of the driving transistor DT and the reference line RL.

At this time, since among the first to third sub-pixels SP1, SP2, and SP3, the sensing transistor SENT in the first sub-pixel SP1 located near the second sub-pixel SP2 being programmed is in the off state, the driving power is The second node N2 of the crystal DT and the reference line RL are not electrically connected to each other. Similarly, in the first to third sub-pixels SP1, SP2, and SP3, the sensing transistor SENT in the third sub-pixel SP3 located near the second sub-pixel SP2 that is being programmed is in the off state, so the driving power The second node N2 of the crystal DT and the reference line RL are not electrically connected to each other.

The back part of the interval of the conduction level voltage of the first scan signal SCAN1 overlaps the front part of the interval of the conduction level voltage of the second scan signal SCAN2.

The back part of the interval of the turn-on level voltage of the first sensing signal SENSE1 overlaps the front part of the interval of the turn-on level voltage of the second sensing signal SENSE2.

The interval of the on-level voltage of the first sensing signal SENSE1 and the interval of the on-level voltage of the second scanning signal SCAN2 overlap to a large extent.

According to the embodiment of FIG. 10, 1H corresponds to one horizontal time. The interval of the turn-on level voltage of the first, second, and third scan signals SCAN1, SCAN2, or SCAN3 is 1.6H. The interval of the on-level voltage of the first, second, and third sensing signals SENSE1, SENSE2, or SENSE3 is 1.6H.

The predetermined sensing offset time tSHIFT/SEN is 0.8H. The interval of the turn-on level voltage of the first sensing signal SENSE1 starts when the interval of the turn-on level voltage of the first scan signal SCAN1 is delayed by 0.8H corresponding to the sensing offset time tSHIFT/SEN.

The period during which the interval of the turn-on level voltage of the first scan signal SCAN1 and the interval of the turn-on level voltage of the first sensing signal SENSE1 overlap is 0.8H. The programming period tPROG of the first sub-pixel SP1 is 0.8H.

The interval of the turn-on level voltage of the second sensing signal SENSE2 is delayed from the interval of the turn-on level voltage of the second scan signal SCAN2 to the interval of the turn-on level voltage corresponding to 0.8H of the sensing offset time tSHIFT/SEN Start.

The period during which the interval of the turn-on level voltage of the second scan signal SCAN2 and the interval of the turn-on level voltage of the second sensing signal SENSE2 overlap is 0.8H. The programming period tPROG of the second sub-pixel SP2 is 0.8H.

The interval of the turn-on level voltage of the third sensing signal SENSE3 starts when the interval of the turn-on level voltage of the third scan signal SCAN3 is delayed by 0.8H corresponding to the sensing offset time tSHIFT/SEN.

The period during which the interval of the turn-on level voltage of the third scan signal SCAN3 and the interval of the turn-on level voltage of the third sensing signal SENSE3 overlap is 0.8H. The programming period tPROG of the third sub-pixel SP3 is 0.8H.

The predetermined scan shift time tSHIFT/SCAN is 0.2H. The interval of the turn-on level voltage of the second scan signal SCAN2 is delayed from the interval of the turn-on level voltage of the first sensing signal SENSE1 by 0.2H corresponding to the predetermined scan offset time tSHIFT/SCAN.

The interval of the turn-on level voltage of the first scan signal SCAN1 overlaps the interval of the turn-on level voltage of the second scan signal SCAN2 by 0.6H. The interval of the turn-on level voltage of the first sensing signal SENSE1 overlaps the interval of the turn-on level voltage of the second sensing signal SENSE2 by 0.6H.

When the interval of the turn-on level voltage of the first sensing signal SENSE1 is 1.6H, and when the interval of the turn-on level voltage of the second scan signal SCAN2 is 1.6H, the turn-on level voltage of the first sensing signal SENSE1 The period during which the interval of and the interval of the on-level voltage of the second scan signal SCAN2 overlap is 1.4H. Accordingly, the period (1.4H) during which the interval of the on-level voltage of the first sensing signal SENSE1 and the interval of the on-level voltage of the second scan signal SCAN2 overlap is equivalent to the total period (1.6H) of each interval 87.5% (=1.4/1.6).

FIG. 11 is a driving timing diagram of the display device 100 according to an embodiment of the present invention when performing black data insertion driving and advanced overlapping driving. FIG. 12 is a schematic diagram showing the states of the third sub-pixel SP3 and adjacent sub-pixels SP2 and SP4 during the programming period of the third sub-pixel SP3. FIG. 13 is a schematic diagram showing the state of the fourth sub-pixel SP4 and its neighboring sub-pixels SP3 and SP5 during the programming period of the fourth sub-pixel SP4 before the black data insertion driving is started. FIG. 14 is a schematic diagram showing the state of the fifth sub-pixel SP5 and its neighboring sub-pixels SP4 and SP6 during the programming period of the fifth sub-pixel SP5 after the black data insertion driving is finished.

11, the plurality of sub-pixels SP may include a fourth scan signal line SCL4 connected to transmit a fourth scan signal SCAN4 and a fourth sensing signal line connected to transmit a fourth sensing signal SENSE4 A fourth sub-pixel SP4 of SENL4, connected to a fifth scan signal line SCL5 for transmitting a fifth scan signal SCAN5, and connected to a fifth sensing signal line SENL5 for transmitting a fifth sensing signal SENSE5 A fifth sub-pixel SP5 connected to a sixth scanning signal line SCL6 for transmitting a sixth scanning signal SCAN6, and a sixth sensing signal line SENL6 for transmitting a sixth sensing signal SENSE6 A sixth sub-pixel SP6...etc.

In FIG. 11, the fourth sub-pixel SP4 represents a plurality of sub-pixels SPrc (r=4 and c=1 to 4) arranged in the fourth sub-pixel row R(n+4) in FIG. 9. In FIG. 11, the fifth sub-pixel SP5 represents a plurality of sub-pixels SPrc (r=5 and c=1 to 4) arranged in the fifth sub-pixel row R(n+5) in FIG. 9. In FIG. 11, the sixth sub-pixel SP6 represents a plurality of sub-pixels SPrc (r=6 and c=1 to 4) arranged in the sixth sub-pixel row R(n+6) in FIG. 9.

Referring to FIG. 11, the fourth sensing signal SENSE4 is in the period during which the interval of the turn-on level voltage of the third scan signal SCAN3 overlaps with the interval of the turn-on level voltage of the third sensing signal SENSE3 (that is, the third sub-pixel SP3 The programming period tPROG) has a turn-off level voltage.

Before the end of the period (that is, the programming period tPROG of the third sub-pixel SP3) in which the interval of the turn-on level voltage of the third scan signal SCAN3 and the interval of the turn-on level voltage of the third sensing signal SENSE3 overlaps, the second The sensing signal SENSE2 switches from the on-level voltage to the off-level voltage at a time point PROG3.

12, in the third sub-pixel SP3 programming period tPROG when the interval of the turn-on level voltage of the third scan signal SCAN3 and the interval of the turn-on level voltage of the third sensing signal SENSE3 overlap, the third sub-pixel SP3 Both the scanning transistor SCT and the sensing transistor SENT are in a conducting state.

The second node N2 of the driving transistor DT in the third sub-pixel SP3 is electrically connected to the reference line RL through the sensing transistor SENT that is turned on during the programming period tPROG of the third sub-pixel SP3.

During the programming period tPROG of the third sub-pixel SP3, the sensing transistor SENT in the fourth sub-pixel SP4 can be in an off state by the fourth sensing signal SENSE4 having a turn-off level voltage. Accordingly, the reference line RL that is electrically connected to the second node N2 of the driving transistor DT in the third sub-pixel SP3 through the turned-on sensing transistor SENT of the third sub-pixel SP3 is not affected by the fourth sub-pixel SP4.

The sensing transistor SENT in the second sub-pixel SP2 can be in the off state by the second sensing signal SENSE2 having the off-level voltage at the time point PROG3 of the third sub-pixel SP3 during the programming period tPROG. Accordingly, the reference line RL that is electrically connected to the second node N2 of the driving transistor DT in the third sub-pixel SP3 through the turned-on sensing transistor SENT of the third sub-pixel SP3 is not affected by the second sub-pixel SP2.

According to the above-mentioned advanced overlap driving, there is a time point PROG3, in which all the sensing transistors SENT in the sub-pixels SP2 and SP4 adjacent to the third sub-pixel SP3 are programmed in the third sub-pixel SP3 at the time point PROG3 During the period tPROG, it is turned off. Therefore, the third sub-pixel SP3 may not be affected by the adjacent sub-pixels SP2 and SP4, and may perform a normal programming operation, thereby emitting light of ideal brightness.

Referring to FIG. 11, the fifth sensing signal SENSE5 is in the period during which the interval of the turn-on level voltage of the fourth scan signal SCAN4 overlaps with the interval of the turn-on level voltage of the fourth sensing signal SENSE4 (that is, the fourth sub-pixel SP4 During the programming period tPROG), there is a turn-off level voltage.

Before the end of the period (that is, the programming period tPROG of the fourth sub-pixel SP4) in which the interval of the turn-on level voltage of the fourth scan signal SCAN4 and the interval of the turn-on level voltage of the fourth sensing signal SENSE4 overlaps, the third The sensing signal SENSE3 switches from the on-level voltage to the off-level voltage at a time point PROG4.

Referring to FIG. 13, during the programming period tPROG of the fourth sub-pixel SP4, the scanning transistor SCT and the sensing transistor SENT of the fourth sub-pixel SP4 are both in a conducting state, and this period corresponds to the conducting level of the fourth scan signal SCAN4 The interval of the voltage overlaps the interval of the turn-on level voltage of the fourth sensing signal SENSE4.

The second node N2 of the driving transistor DT in the fourth sub-pixel SP4 is electrically connected to the reference line RL through the sensing transistor SENT turned on during the programming period of the fourth sub-pixel SP4 tPROG.

During the programming period tPROG of the fourth sub-pixel SP4, the sensing transistor SENT in the fifth sub-pixel SP5 can be turned off by the fifth sensing signal SENSE5 having a turn-off level voltage. Accordingly, the sensing transistor SENT is electrically connected to the reference line RL of the second node N2 of the driving transistor DT in the fourth sub-pixel SP4 in which tPROG is turned on during the programming period of the fourth sub-pixel SP4. The impact of SP5.

The sensing transistor SENT in the third sub-pixel SP3 can be turned off by the third sensing signal SENSE3 having a turn-off level voltage during the time point PROG4 of the programming period tPROG of the fourth sub-pixel SP4. Accordingly, the sensing transistor SENT is electrically connected to the reference line RL of the second node N2 of the driving transistor DT in the fourth sub-pixel SP4 in which tPROG is turned on during the programming period of the fourth sub-pixel SP4. The impact of SP3.

According to the above-mentioned advanced overlapping driving, since there is a time point PROG4, all the sensing transistors SENT in the sub-pixels SP3 and SP5 adjacent to the fourth sub-pixel SP4 are programmed in the fourth sub-pixel SP4 at the time point PROG4 During the period tPROG, the fourth sub-pixel SP4 is not affected by the adjacent sub-pixels SP3 and SP5, and the normal programming operation can be performed to emit light of ideal brightness.

11, the sixth sensing signal SENSE6 is in the period during which the interval of the turn-on level voltage of the fifth scan signal SCAN5 overlaps with the interval of the turn-on level voltage of the fifth sensing signal SENSE5 (that is, the fifth sub-pixel SP5 During the programming period tPROG), there is a turn-off level voltage.

Before the interval of the turn-on level voltage of the fifth scan signal SCAN5 and the turn-on level voltage of the fifth sensing signal SENSE5 overlaps with the interval (that is, the programming period tPROG of the fifth sub-pixel SP5) ends, the fourth The sensing signal SENSE4 switches from the on-level voltage to the off-level voltage at a time point PROG5.

Referring to FIG. 14, during the programming period tPROG of the fifth sub-pixel SP5, the scanning transistor SCT and the sensing transistor SENT of the fifth sub-pixel SP5 are both in a conducting state, and this period corresponds to the conducting level of the fifth scan signal SCAN5 The period during which the interval of the voltage overlaps the interval of the on-level voltage of the fifth sensing signal SENSE5.

The second node N2 of the driving transistor DT in the fifth sub-pixel SP5 is electrically connected to the reference line RL through the sensing transistor SENT turned on during the programming period of the fifth sub-pixel SP5 tPROG.

During the programming period tPROG of the fifth sub-pixel SP5, the sensing transistor SENT in the sixth sub-pixel SP6 can be turned off by the sixth sensing signal SENSE6 having a turn-off level voltage. Accordingly, the sensing transistor SENT is electrically connected to the reference line RL of the second node N2 of the driving transistor DT in the fifth sub-pixel SP5 in which tPROG is turned on during the programming period of the fifth sub-pixel SP4. The impact of SP6.

The sensing transistor SENT in the fourth sub-pixel SP4 can be turned off by the fourth sensing signal SENSE4 having the turn-off level voltage during the time point PROG5 of the programming period tPROG of the fifth sub-pixel SP5. Accordingly, the sensing transistor SENT is electrically connected to the reference line RL of the second node N2 of the driving transistor DT in the fifth sub-pixel SP5 in which tPROG is turned on during the programming period of the fifth sub-pixel SP5. The impact of SP4.

According to the above-mentioned advanced overlap driving, there is a time point PROG5, in which all the sensing transistors SENT in the fifth sub-pixel SP5 in the sub-pixels SP4 and SP6 adjacent to the fifth sub-pixel SP5 are programmed at the time point PROG5 During the period tPROG, it is turned off. Therefore, the fifth sub-pixel SP5 may not be affected by the adjacent sub-pixels SP4 and SP6, and may perform a normal programming operation, thereby emitting light of ideal brightness.

Referring to FIG. 11, during the period during which the fourth scan signal SCAN4 having the on-level voltage is provided to the fourth scan signal line SCL4 and the period during which the fifth scan signal SCAN5 having the on-level voltage is provided to the fifth scan signal line SCL5 During the fake data insertion (FDI) driving period, the fake data voltage Vfake that is different from the real image data voltage Vdata can be provided to rows arranged in k ("k" is a natural number of 1 or more) A plurality of sub-pixels SP of a pixel line (sub-pixel row).

Here, false data insertion (FDI) is also referred to as "black data insertion (BDI)" in which black data is inserted therein, for example.

Summarizing the above content, the i-th ("i" is a natural number greater than 1) scan signal SCAN with a turn-on level voltage will have a turn-on bit during the period when the i-th scan signal line of the multiple scan lines is provided The quasi-voltage (i+1)th scan signal SCAN is provided to the (i+1)th scan signal line of the scan lines during the false data insertion (FDI) driving period, and the real image data voltage Vdata Different dummy data voltages Vfake can be provided to a plurality of sub-pixels SP arranged in k ("k" is a natural number of 1 or more) sub-pixel lines (sub-pixel rows).

Referring to FIG. 11, during the period during which the fourth scan signal SCAN4 having the on-level voltage is provided to the fourth scan signal line SCL4 and the period during which the fifth scan signal SCAN5 having the on-level voltage is provided to the fifth scan signal line SCL5 During the false data insertion (FDI) driving period, the data driving circuit 120 can output a false data voltage Vfake that is different from the real image data voltage Vdata to all or part of the data lines DL.

The dummy data voltage Vfake can be provided to the sub-pixels SP arranged in k (k is a natural number of 1 or more) sub-pixel lines (sub-pixel rows).

For example, the fake data voltage Vfake can be a black data voltage Vblack, a low grayscale data voltage, and so on. When the fake data voltage Vfake is the black data voltage Vblack, the fake data insertion (FDI) drive is called "black data insertion (BDI) drive".

Referring to FIG. 11, the precharge driving period tPC can follow the dummy data insertion driving period tFDI.

Referring to FIG. 11, after the data driving circuit 120 outputs the dummy data voltage Vfake during the dummy data insertion driving period tFDI, it can output a precharge data voltage Vpre to all or part of the data lines DL during the precharge driving period tPC.

Referring to FIG. 11, after the data driving circuit 120 starts to output the precharge data voltage Vpre, the first gate driving circuit 130 can output the fifth scan signal SCAN5 to the fifth scan signal line SCL5 having the turn-on level voltage.

The period during which the interval of the turn-on level voltage of the fifth scan signal SCAN5 and the interval of the turn-on level voltage of the fifth sensing signal SENSE5 overlap (that is, the programming period of the fifth sub-pixel SP5) may follow the output of the data driving circuit 120 The period of precharging the data voltage Vpre (that is, the precharging driving period tPC).

FIG. 15 is a schematic diagram of a dummy data insertion driver (for example, a black data insertion driver) of the display device 100 drawn according to an embodiment of the present invention.

Referring to FIG. 15, during the dummy data insertion driving period tFDI, the dummy data voltage Vfake for dummy data insertion is applied to the plurality of first nodes N1 of the plurality of driving transistors DT of the k sub-pixel rows.

Accordingly, when the data driving circuit 120 outputs the false data voltage Vfake, all the scanning transistors SCT in the k sub-pixel rows are in a conductive state, and all the scanning transistors in the remaining sub-pixel rows outside the k sub-pixel rows The crystal SCTs are all in the off state.

When the data driving circuit 120 outputs the false data voltage Vfake, all the sensing transistors SENT in all the sub-pixels SP including the k sub-pixel rows and the remaining sub-pixel rows are in the off state.

In other words, the first gate driving circuit 130 can output the data to the scan signal lines SCL corresponding to the k sub-pixel lines during the dummy data insertion driving period tFDI during which the data driving circuit 120 outputs the dummy data voltage Vfake. The scan signal with the turn-on level voltage is turned on, and the scan signal with the turn-off level voltage can be output to the remaining scan signal lines. The second gate driving circuit 140 can output a sensing signal with a turn-off level voltage to all the plurality of sensing signal lines SENL.

FIG. 16 is a schematic diagram of the pre-charge driving of the display device 100 according to an embodiment of the present invention.

Referring to FIG. 16, during the precharge driving period tPC in which the data driving circuit 120 outputs the precharge data voltage Vpre, the first gate driving circuit 130 may output the scan signal SCAN with the turn-off level voltage to the full scan signal line SCL, and The second gate driving circuit 140 can output the sensing signal SENSE with the turn-off level voltage to all the sensing signal lines SENL.

In the pre-charge driving period tPC, the pre-charge data voltage Vpre is only applied to the plurality of data lines DL instead of the plurality of sub-pixels SP.

In other words, during the precharge driving period tPC, the precharge data voltage Vpre is only applied to the plurality of data lines DL, instead of being applied to the first node N1 of the driving transistor DT of each sub-pixel SP.

FIG. 17 is a schematic diagram of the setting range of the precharge data voltage Vpre of the display device 100 drawn according to an embodiment of the present invention.

Referring to FIG. 17, in addition, the precharge data voltage Vpre applied to one or more data lines DL during the precharge driving period tPC may be one of the following voltages: a first output before the output of the precharge data voltage Vpre The image data voltage Vdata1, a second image data voltage Vdata2 output after the precharge data voltage Vpre is output, the dummy data voltage Vfake, and the higher of the first image data voltage Vdata1 and the second image data voltage Vdata2 A voltage between the voltage and the fake data voltage Vfake.

Referring to FIG. 17, the precharge data voltage Vpre can be set within a set range, where the fake data voltage Vfake is the lower limit value, and the first image data voltage Vdata1 and the second image data voltage Vdata2 are relatively low. The higher voltage is an upper limit.

FIG. 18 is a schematic diagram of a scanning transistor SCT of the display device 100 according to an embodiment of the present invention, and FIG. 19 is a schematic diagram of an induction transistor SENT of the display device 100 according to an embodiment of the present invention. The circuit diagram of the sub-pixel SP shown in FIG. 2 will also be mentioned.

18, the scanning transistor SCT may include a first scan pattern 1810 as its drain node (or source node) and electrically connected to the data line DL, as its source node (or drain node) and electrically connected to the data line DL. A second scan pattern 1820, a gate electrode 1800, etc., which are electrically connected to the first node N1 of the driving transistor DT, wherein the gate electrode 1800 is connected to the first scan pattern 1810 through the contact hole CNT on one side and connected to the other side To or integrate with the second scanning pattern 1820, thereby electrically connecting the first scanning pattern 1810 to the second scanning pattern 1820 and the like.

The scan signal line SCL can be arranged to overlap with the gate electrode 1800 of the scan transistor SCT. The overlapping portion of the gate electrode 1800 of the scanning transistor SCT and the scanning signal line SCL corresponds to the channel CHc of the scanning transistor SCT. The channel CHc of the scanning transistor SCT has a channel width Wc and a channel length Lc.

The ratio Wc/Lc of the channel width Wc to the channel length Lc in the scanning transistor SCT can determine the characteristics of the channel CHc of the scanning transistor SCT. The ratio Wc/Lc of the channel width Wc to the channel length Lc in the scanning transistor SCT can determine the on-off characteristics and switching performance of the scanning transistor SCT.

19, the sensing transistor SENT may include a first pattern 1910 as its drain node (or source node) and electrically connected to the reference line RL, as its source node (or drain node) and electrically connected to the reference line RL. A second pattern 1920, a gate electrode 1900, etc., which are electrically connected to the second node N2 of the driving transistor DT, wherein the gate electrode 1900 is connected to the first pattern 1910 through the contact hole CNT on one side, and through the opposite side The other contact hole CNT of is connected to the second pattern 1920, thereby connecting the first pattern 1910 to the second pattern 1920 and so on.

The sensing signal line SENL can be arranged to overlap with the gate electrode 1900 of the sensing transistor SENT. The portion where the gate electrode 1900 of the sensing transistor SENT overlaps with the sensing signal line SENL corresponds to the channel CHs of the sensing transistor SENT. The channel CHs of the sensing transistor SENT has a channel width Ws and a channel length Ls.

The ratio Ws/Ls of the channel width Ws to the channel length Ls in the sensing transistor SENT can determine the characteristics of the channel CH of the sensing transistor SENT. The ratio Ws/Ls of the channel width Ws to the channel length Ls in the sensing transistor SENT can determine the on-off characteristics and switching performance of the sensing transistor SENT.

18 and 19, the ratio Ws/Ls of the channel width Ws to the channel length Ls of the sensing transistor SENT may be greater than the ratio Wc/Lc of the channel width Wc to the channel length Lc of the scanning transistor SCT.

According to the advanced superimposition driving, the interval of the on-level voltage of the sensing signal SENSE in any sub-pixel SP is delayed by the sensing offset time tSHIFT/SEN from the interval of the on-level voltage of the scanning signal SCAN. Therefore, For normal charging and normal programming operations, the sensing transistor SENT is required to have a turn-on speed faster than the turn-on speed of the scanning transistor SCT.

Accordingly, as described above, by designing the ratio Ws/Ls of the channel width Ws to the channel length Ls of the sensing transistor SENT to be greater than the ratio Wc/Lc of the channel width Wc to the channel length Lc of the scanning transistor SCT, When performing the above-mentioned advanced overlap driving, it can ensure that the storage capacitor Cst has sufficient charging time. Accordingly, the programming operation of the corresponding sub-pixel SP can be performed quickly and normally.

At the same time, in the case where the plurality of sub-pixels SP include a plurality of sub-pixels emitting different lights (for example, a sub-pixel emitting red light, a sub-pixel emitting green light, a sub-pixel emitting blue light, and a sub-pixel emitting white light), The multiple ratios Ws/Ls of multiple channel widths Ws of multiple sensing transistors SENT to multiple channel lengths Ls of multiple sub-pixels that emit different lights may be the same.

Optionally, in at least one of the four sub-pixels emitting different light, the ratio Ws/Ls of the channel width Ws to the channel length Ls of the sensing transistor SENT may be the same as that of the sensing transistor SENT in the remaining sub-pixels. The ratio Ws/Ls of the channel width Ws to the channel length Ls is different.

FIG. 20 is a flowchart of a driving method of the display device 100 according to an embodiment of the present invention.

Referring to FIG. 20, a driving method of a display device 100 including a plurality of sub-pixels SP may include: step S2010, providing a first scan signal SCAN1 to a first scan signal line SCL1 having a turn-on level voltage interval, wherein the first scan signal The line SCL1 is connected to the gate node of the scanning transistor SCT of the first sub-pixel SP1 among the plurality of sub-pixels SP; step S2020, providing the first sensing signal SENSE1 to the first sensing signal line SENL1 with a turn-on level voltage interval, The first sensing signal line SENL1 is electrically connected to the gate node of the sensing transistor SENT in the first sub-pixel SP1, and the turn-on level voltage of the first sensing signal SENSE1 is greater than that of the first scan signal SCAN1. The interval of the level voltage is delayed by the predetermined sensing offset time tSHIFT/SEN; step S2030, the first scan signal SCAN1 having the interval of the turn-off level voltage is provided to the first scan signal line SCL1, and the first scan signal SCAN1 is provided to the first sensing signal The line SENSE1 provides the first sensing signal SENL1 in the interval with the turn-off level voltage.

In step S2010, the display device 100 may transmit the image data voltage Vdata provided to the data line DL to the first node N1 of the driving transistor DT in the first sub-pixel SP1 through the turned-on scanning transistor SCT.

In step S2020, the display device 100 can transmit the reference voltage Vref provided to the reference line RL to the second node N2 of the driving transistor DT through the turned-on sensing transistor SENT.

In step S2030, the voltages of the first node N1 and the second node N2 in the driving transistor DT increase. Here, the second node N2 of the driving transistor DT can be electrically connected to a first electrode of the light-emitting unit EL.

In step S2030, if the voltage of the second node N2 of the driving transistor DT increases to a specific level or higher, current flows to the light-emitting unit EL, so that the light-emitting unit EL starts to emit light.

The interval of the turn-on level voltage of the first sensing signal SENSE1 may include a period OP during which the interval of the turn-on level voltage of the first sensing signal SENSE1 overlaps with the interval of the turn-on level voltage of the first scan signal SCAN1, And the interval of the turn-on level voltage of the first sensing signal SENSE1 does not overlap with the interval of the turn-on level voltage of the first scan signal SCAN1 for a period NOP.

The start point of the interval of the conduction level voltage of the first sensing signal SENSE1 may be delayed by a sensing offset time tSHIFT/SENSE than the start point of the interval of the conduction level voltage of the first scan signal SCAN1, and the The sensing offset time tSHIFT/SEN may correspond to 1/2 of the interval of the turn-on level voltage of the first scan signal SCAN1.

The plurality of sub-pixels SP may further include a second sub-pixel SP2 and a third sub-pixel SP3, and the drain nodes of the sensing transistor SENT included in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 Or the source node can be electrically connected to the same reference line.

There may be a time point PROG2. In this time point PROG2, when the second scan signal SCAN2 with the on-level voltage is supplied to the gate node of the scanning transistor SCT in the second sub-pixel SP2, and when there is a conductive When the second sensing signal SENSE2 of the level voltage is supplied to the gate node of the sensing transistor SENT in the second sub-pixel SP2, the sensing transistor SENT in the first sub-pixel SP1 and the third sub-pixel SP3 The sensing transistor SENT is turned off at the same time.

During the period in which the i-th scan signal SCAN with the on-level voltage ("i" is a natural number greater than 1) is provided to the i-th scan signal line among the multiple scan lines, and the first with the on-level voltage The (i+1) scan signal SCAN is provided to the (i+1)th scan signal line of the scan lines during the false data insertion (FDI) driving period, which is different from the real image data voltage Vdata. The data voltage Vfake can be provided to a plurality of sub-pixels SP arranged in k ("k" is a natural number of 1 or more) sub-pixel lines (sub-pixel rows).

FIG. 21 is a schematic diagram illustrating the effect of avoiding specific line brightness defects in the case of the display device of the embodiment of the present invention performing false data insertion driving and advanced overlapping driving.

As described above, in the case of superimposition driving as described with reference to FIGS. 5 and 6, if dummy data insertion driving is performed during superimposition driving, sub-pixel rows may appear immediately before the dummy data insertion driving. The specific line brightness phenomenon of the bright line 700.

However, in the case of advanced superimposition driving, even if the dummy data insertion driving is performed during the superimposition driving, the characteristics of the superimposition driving immediately before the dummy data driving will not change through the advanced superimposition driving. Among them, in the advanced superimposition driving, the interval of the on-level voltage of the sensing signal among the two gate signals (a scanning signal and one sensing signal) is controlled to be delayed from the interval of the on-level voltage of the scanning signal. In other words, according to the advanced overlap driving, all corresponding sub-pixels that are programmed are not affected by adjacent sub-pixels.

Accordingly, according to the advanced overlap drive, it is possible to prevent the sub-pixel row (for example, the fourth sub-pixel row, the eighth sub-pixel row, etc.) from showing the specific line brightness phenomenon of the bright line 700 immediately before the false data insertion drive. .

FIG. 22 is a schematic diagram of a gate driving circuit 2200 of an embodiment of the present invention, FIG. 23 is a timing diagram of driving a gate of an embodiment of the present invention, and FIG. 24 is a gate signal output of an embodiment of the present invention Schematic diagram of unit 2400.

Please refer to FIG. 22. The gate driving circuit 2200 of the embodiment of the present invention may include a level shift circuit 2210 and a gate signal outputter 2220.

Referring to FIG. 22, the level shift circuit 2210 may include a scanning clock signal generator 2211 and a sensing clock signal generator 2212.

The scan clock signal generator 2211 can receive a first reference scan clock signal GCLK_SC and a second reference scan clock signal MCLK_SC, and can generate and output a plurality of scan clock signals (such as SC_CLK1 to SC_CLK8). The scan clock signals SC_CLK1 to SC_CLK8 may have a plurality of signal waveforms shifted by a predetermined time.

The sensing clock signal generator 2212 can receive a first reference sensing clock signal GCLK_SE and a second reference sensing clock signal MCLK_SE, and can generate and output a plurality of sensing signals (for example, SE_CLK1 to SE_CLK8). The sensing clock signals SE_CLK1 to SE_CLK8 may have a plurality of signal waveforms shifted by a predetermined time.

If the gate driving circuit 2200 performs n-phase gate driving, n scanning clock signals can be generated, and n sensing clock signals can be generated. For example, as shown in FIG. 22, if the gate driving circuit 2200 performs 8-phase gate driving, eight scan clock signals SC_CLK1 to SC_CLK8 can be generated, and eight sensing clock signals SE_CLK1 to SE_CLK8 can be generated .

Referring to FIG. 22, the level shift circuit 2210 may further include a carry clock signal generator 2213.

22, the gate signal output unit 2220 can output a scan signal SCAN with a turn-on level voltage interval based on the scan clock signals SC_CLK1 to SC_CLK8, and can output the sense clock signals SE_CLK1 to SE_CLK8 based on the scan clock signals SC_CLK1 to SC_CLK8 A sensing signal with a turn-on level voltage interval.

Referring to FIG. 22, the scan signal generator 2211 may include a scan logic unit LOGIC_SC and a scan level shifter LS_SC.

The scan logic unit LOGIC_SC can receive the first reference scan clock signal GCLK_SC and the second reference scan clock signal MCLK_SC, and can generate the rise time of the first reference scan clock signal GCLK_SC and the second reference scan clock signal The falling time of MCLK_SC is the falling scan clock signals SC_CLK1 to SC_CLK8.

The scan level shifter LS_SC can change and output multiple voltage levels of the scan clock signals SC_CLK1 to SC_CLK8 generated by the scan logic unit LOGIC_SC.

The scan level shifter LS_SC can output the scan clock signals SC_CLK1 to SC_CLK8.

The sensing clock signal generator 2212 may include a sensing logic unit LOGIC_SE, a delay device DD, and a sensing level shifter LS_SE.

The sensing logic unit LOGIC_SE can receive the first reference sensing clock signal GCLK_SE and the second reference sensing clock signal MCLK_SE, and can generate the sensing clock signals SE_CLK1 to SE_CLK8 according to the signal control logic.

The sensing clock signals SE_CLK1 to SE_CLK8 generated according to the signal control logic can rise at the rising time of the second reference sensing clock signal MCLK_SE, instead of rising at the rising time of the first reference sensing clock signal GCLK_SE , And the sensing clock signals SE_CLK1 to SE_CLK8 can fall after the falling time of the second reference sensing clock signal MCLK_SE passes a predetermined delay time tDELAY.

The delay device DD can delay the rise time of the sensing clock signals SE_CLK1 to SE_CLK8, so that the sensing clock signals SE_CLK1 to SE_CLK8 rise at the rise time of the second reference sensing clock signal MCLK_SE instead of the first reference sensing The clock signal GCLK_SE rises at the rise time.

The scan level shifter LS_SE can change and output multiple voltage levels of the sensing clock signals SE_CLK1 to SE_CLK8 generated by the sensing logic unit LOGIC_SE.

The sensing level shifter LS_SE can output sensing clock signals SE_CLK1 to SE_CLK8 rising to a high-level gate voltage VGH and falling to a low-level gate voltage VGL, and the sensing clock signals SE_CLK1 to SE_CLK8 have a specific scan A high-level gate voltage interval of the clock signals SC_CLK1 to SC_CLK8 is delayed by a high-level gate voltage interval of the predetermined sensing offset time tSHIFT/SEN.

Referring to FIG. 22, for example, the delay device DD may include one or more resistive elements.

The carry clock signal generator 2213 can receive a first reference carry clock signal GCLK_CR and a second reference carry clock signal MCLK_CR, and is used to generate and output a carry clock signal CR_CLK1 to CR_CLK8.

Referring to FIG. 22, the carry clock signal generator 2213 may include a carry logic unit LOGIC_CR and a carry level shifter LS_CR.

The carry logic unit LOGIC_CR can receive the first reference carry clock signal GCLK_CR and the second reference carry clock signal MCLK_CR, and can generate a rise at a rise time of the first reference carry clock signal GCLK_CR and a second reference carry clock The carry clock signals CR_CLK1 to CR_CLK8 that fall during a fall time of the signal MCLK_CR. The carry clock signals CR_CLK1 to CR_CLK8 may have the same waveform as the scan clock signals SC_CLK1 to SC_CLK8.

The carry level shifter LS_CR can change and output multiple voltage levels of the carry clock signals CR_CLK1 to CR_CLK8 generated by the carry logic unit LOGIC_CR.

The carry level shifter LS_CR can output the carry clock signals CR_CLK1 to CR_CLK8 that rise to the high-level gate voltage and fall to the low-level gate voltage.

At the same time, the level shift circuit 2210 included in the gate drive circuit 2200 can be implemented on a single integrated circuit chip.

The gate signal outputter 2220 included in the gate driving circuit 2200 can be implemented by one or more integrated circuit chips.

Alternatively, the gate signal outputter 2220 included in the gate driving circuit 2200 may be implemented in a GIP circuit (Gate-In-Panel) type. In this case, the gate signal output 2220 can be arranged in the non-display area of the display panel 110, in which a plurality of scan lines SCL applied with a plurality of scan signals SCAN and a plurality of scan lines SCL with a plurality of sensing signals SENSE applied. The sensing lines SENL are arranged in the display panel 110.

The gate driving circuit 2200 in FIG. 22 may be a circuit implemented by including the first gate driving circuit 130 and the second gate driving circuit 140 shown in FIG. 1.

After that, the characteristics of the scan clock signals SC_CLK1 to SC_CLK8 generated by the scan clock signal generator 2211 and the characteristics of the sense clock signals SE_CLK1 to SE_CLK8 generated by the sense clock signal generator 2212 will be matched with the figure 23 Make a more detailed description. However, for ease of description, a scan clock signal SC_CLK between the scan clock signals SC_CLK1 to SC_CLK8, a sensing clock signal SE_CLK between the sensing clock signals SE_CLK1 to SE_CLK8, and a carry clock signal CR_CLK1 will be based on The example of the carry clock signal CR_CLK from CR_CLK8 to CR_CLK8 is taken as a description.

Please refer to FIG. 23, after the first reference scan clock signal GCLK_SC rises and falls, the second reference scan clock signal MCLK_SC can rise and fall.

After the first reference sensing clock signal GCLK_SE rises and falls, the second reference sensing clock signal MCLK_SE can rise and fall.

Referring to FIG. 23, the high-level gate voltage interval of the sensing clock signal SE_CLK may be delayed by a predetermined sensing offset time tSHIFT/SEN from the high-level gate voltage interval of the scanning clock signal SC_CLK.

Therefore, the on-level voltage interval of the sensing signal SENSE generated by the self-sensing clock signal SE_CLK may be delayed by the predetermined sensing offset time tSHIFT/SEN compared to the on-level voltage interval of the scan signal SCAN generated by the self-scanning clock signal SC_CLK. .

Referring to FIG. 23, the scan clock signal generator 2211 can generate and output a scan clock signal SC_CLK, where the scan clock signal SC_CLK rises at the rise time of the first reference scan clock signal GCLK_SC and at the second reference scan clock signal MCLK_SC falls during the fall time.

The sensing clock signal generator 2212 can generate and output the sensing clock signal SE_CLK, where the sensing clock signal SE_CLK rises at the rising time of the second reference sensing clock signal MCLK_SE, instead of at the first reference sensing The measurement clock signal GCLK_SE rises at the rising time, and falls after the falling time of the second reference sensing clock signal MCLK_SE passes the predetermined delay time tDELAY.

A time interval between the rising time of the first reference sensing clock signal GCLK_SE and the rising time of the second reference sensing clock signal MCLK_SE corresponds to the predetermined sensing offset time tSHIFT/SEN.

Referring to FIG. 23, the rise time of the first reference sensing clock signal GCLK_SE may be the same as the rise time of the first reference scan clock signal GCLK_SC.

In order to indicate the rise time of the sense clock signal SE_CLK, the rise time of the second reference sense clock signal MCLK_SE may be earlier than the rise time of the second reference scan clock signal MCLK_SC.

Referring to FIG. 23, the length of time (for example 0.8H) during which the scanning clock signal SC_CLK and the sensing clock signal SE_CLK overlap each other can correspond to the time length (for example 1.6H) of the conduction level voltage interval of the sensing signal SENSE minus A value obtained by removing the delay time tDELAY (for example, 0.8H).

As described above, the gate signal outputter 2220 can output multiple scan signals SCAN to multiple scan lines SCL, and can output multiple sensing signals SENSE to multiple sense lines SENL. The gate signal output unit 2220 may include multiple gate signal output units 2400 corresponding to multiple stages.

Referring to FIG. 24, each gate signal output unit 2400 can output a scan signal SCAN to a scan line SCL, and can output a sensing signal SENSE to a sensing line SENL.

Each gate signal output unit 2400 may include an output buffer circuit 2410 and a control logic circuit 2420.

The output buffer circuit 2410 may include a first pull-up transistor Tu1 and a first pull-down transistor Td1 for outputting the nth scan signal SCAN(n), and may include a first pull-down transistor Td1 for outputting the nth sensing signal SENSE(n) ) A second pull-up transistor Tu2 and a second pull-down transistor Td2, and may include a third pull-up transistor Tu3 and a third pull-down transistor Td3 for outputting the n-th carry signal CR(n) .

The first pull-up transistor Tu1 and the first pull-down transistor Td1 can be applied to a first clock signal node NH1 and a gate reference voltage GVSS to which the n-th scan clock signal SC_CLK(n) is applied. The gate reference nodes NL are connected in series.

The first connection point Nout1 where the first pull-up transistor Tu1 and the first pull-down transistor Td1 are connected to each other may be a point where the scan signal SCAN is output, and may be electrically connected to the scan line SCL.

The second pull-up transistor Tu2 and the second pull-down transistor Td2 can be applied to a second clock signal node NH2 to which the sense clock signal SE_CLK(n) of the nth phase is applied and the gate to which the gate reference voltage GVSS is applied The reference nodes NL are connected in series.

A second connection point Nout2 where the second pull-up transistor Tu2 and the second pull-down transistor Td2 are connected to each other can be a point where the sensing signal SENS is output, and can be electrically connected to the sensing line SENL.

The third pull-up transistor Tu3 and the third pull-down transistor Td3 can be applied to a third clock signal node NH3 to which the n-th phase carry clock signal CR_CLK(n) is applied and a gate reference to which the gate reference voltage GVSS is applied The nodes NL are connected in series.

A third connection point Nout3 where the third pull-up transistor Tu3 and the third pull-down transistor Td3 are connected to each other can be a point where the n-th carry signal CR(n) is output.

The n-th carry signal CR(n) may be input to the gate signal output unit 2400 at a stage after the gate signal output unit 2400 in FIG. 24 (for example, the (n+2) stage).

The gate node of the first pull-up transistor Tu1 can be electrically connected to a node Q1. The first pull-up transistor Tu1 can be controlled to be turned on and turned off according to the voltage of the node Q1.

The gate node of the second pull-up transistor Tu2 can be electrically connected to a node Q2. The second pull-up transistor Tu2 can be controlled to be turned on or turned off according to the voltage of the node Q2.

The gate node of the third pull-up transistor Tu3 can be electrically connected to a node Q3. The third pull-up transistor Tu3 can be controlled to be turned on or turned off according to the voltage of the node Q3.

The gate node of the first pull-down transistor Td1 can be electrically connected to a node QB1. The first pull-down transistor Td1 can be controlled to be turned on or turned off according to the voltage of the node QB1.

The gate node of the second pull-down transistor Td2 can be electrically connected to a node QB2. The second pull-down transistor Td2 can be controlled to be turned on or turned off according to the voltage of the node QB2.

The gate node of the third pull-down transistor Td3 can be electrically connected to a node QB3. The third pull-down transistor Td3 can be controlled to be turned on or turned off according to the voltage of the node QB3.

The control logic circuit 2420 can receive the carry signal CR(n-2), the start signal VST, and the reset signal RST of the previous stage to control the voltages of the nodes Q1, Q2, and Q3, and control the nodes QB1, QB2, and the nodes The voltage of QB3. The control logic circuit 2420 may include multiple transistors and one or more capacitors.

The node Q1, the node Q2, and the node Q3 may be electrically isolated nodes. Alternatively, all of the nodes Q1, Q2, and Q3 may be electrically connected nodes. Alternatively, the node Q1 and the node Q3 may be electrically connected, and the node Q2 may be a node electrically isolated from the node Q1 and the node Q3.

The node QB1, the node QB2, and the node QB3 may be electrically isolated nodes. Alternatively, all of the nodes QB1, QB2, and QB3 may be electrically connected nodes. Alternatively, the node QB1 and the node QB3 may be electrically connected, and the node QB2 may be a node electrically isolated from the node QB1 and the node QB3.

If the first pull-up transistor Tu1 is turned on, the first pull-down transistor Td1 can be turned off. At this time, the scan signal SCAN with a turn-on level voltage interval (for example, a high-level gate voltage interval) can be output through the first pull-up transistor Tu1 based on the scan clock signal SC_CLK(n).

If the first pull-up transistor Tu1 is turned off, the first pull-down transistor Td1 can be turned on. At this time, a scan signal SCAN having a turn-off level voltage interval (for example, a low-level gate voltage interval) can be output through the first pull-down transistor Td1 based on the gate reference voltage GVSS.

If the second pull-up transistor Tu2 is turned on, the second pull-down transistor Td2 can be turned off. At this time, a sensing signal SENSE having a turn-on level voltage interval (for example, a high-level gate voltage interval) can be output through the second pull-up transistor Tu2 based on the scan clock signal SE_CLK(n). The sensing signal SENSE may have a turn-on level voltage interval that is delayed by a predetermined sensing offset time tSHIFT/SEN from the turn-on level voltage interval of the scan signal SCAN.

If the second pull-up transistor Tu2 is turned off, the second pull-down transistor Td2 can be turned on. At this time, a scan signal SCAN having a turn-off level voltage interval (for example, a low-level gate voltage interval) can be output through the first pull-down transistor Td2 based on the gate reference voltage GVSS.

If the third pull-up transistor Tu3 is turned on, the third pull-down transistor Td3 can be turned off. At this time, a carry signal CR(n) having a turn-on level voltage interval (for example, a high-level gate voltage interval) can be output through the third pull-up transistor Tu3 based on the carry clock signal CR_CLK(n).

If the third pull-up transistor Tu3 is turned off, the third pull-down transistor Td3 can be turned on. At this time, a carry signal CR(n) having a turn-off level voltage interval (for example, a low-level gate voltage interval) can be output through the third pull-down transistor Td3 based on the gate reference voltage GVSS.

As shown in FIG. 23, the carry signal CR(n) may have the same signal change time point as the scan signal SCN.

At the same time, the level shift circuit 2210 included in the gate drive circuit 2200 can be implemented on a single integrated circuit chip.

The gate signal outputter 2220 included in the gate driving circuit 2200 can be implemented by one or more integrated circuit chips.

Alternatively, the gate signal outputter 2220 included in the gate driving circuit 2200 may be implemented in a GIP circuit (Gate-In-Panel) type. In this case, the gate signal output 2220 can be arranged in the non-display area of the display panel 110, in which the multiple scan lines SCL to which multiple scan signals SCAN are applied and the multiple to which multiple sensing signals SENSE are applied. The sensing lines SENL are arranged in the display panel 110.

The gate driving circuit 2200 in FIG. 22 may be a circuit implemented by including the first gate driving circuit 130 and the second gate driving circuit 140 shown in FIG. 1.

According to the embodiments of the present invention described above, through the overlapping driving of the sub-pixels SP, the image quality can be improved by increasing the charging rate.

In addition, according to the embodiments of the present invention, it is possible to improve the image quality by avoiding the phenomenon that the image is not clear and being dragged, or by avoiding the insertion of the driver through the fake data, the display of multiple real Fake images (such as black images, low-gray-scale images, etc.) are intermittently inserted between images, resulting in a phenomenon of brightness differences between multiple sub-pixel lines.

In addition, according to the embodiment of the present invention, even if dummy data is inserted into the drive during the overlap drive, control can still be performed so that the characteristics of the overlap drive will not change rapidly before the dummy data is inserted into the drive through the advanced overlap drive. In the overlapping driving, the voltage interval of the on-level voltage of the sensing signal in the two gate signals (scan signal and sensing signal) is controlled to be delayed compared to the voltage interval of the on-level voltage of the scan signal.

Therefore, even if the dummy data insertion driving is performed during the overlap driving, it is possible to prevent the occurrence of the sub-pixel row (for example, the fourth sub-pixel row, the 8th sub-pixel row, etc.) immediately before the dummy data insertion driving. Like abnormal situations (for example, specific line brightness phenomenon).

Furthermore, the embodiments of the present invention can provide a display device and a driving method thereof, and a gate driving circuit. In addition to advanced overlapping driving, it is also possible to increase the channel width Ws of the sensing transistor SENT to the channel The ratio of length Ls (Ws/Ls) to compensate for the decrease in charging time.

The above description is to enable anyone skilled in the art to make and use the technical ideas of the present invention, and it has been provided under specific applications and their needs. Various modifications, additions and substitutions to the described embodiments will be obvious to those skilled in the art, and the general principles defined herein can be applied to other embodiments and other embodiments without departing from the spirit and scope of the present invention. application. The above description and the accompanying drawings are merely examples of the technical idea of the present invention provided for the purpose of illustration. That is to say, the invented embodiment is to illustrate the scope of the technical idea of the present invention. Therefore, the scope of the present invention is not limited to the illustrated embodiment, but should be given the broadest scope consistent with the claims. The protection scope of the present invention should be interpreted according to the following claims, and all technical ideas within the equivalent scope should be understood as being included in the scope of the present invention.

100: display device 110: display panel 120: data drive circuit 130: The first gate drive circuit 140: The second gate drive circuit 150: Controller 310: Power management integrated circuit 320: main power management circuit 330: setting board 700: bright line 1800: gate electrode 1810: First scan pattern 1820: second scan pattern 1900: gate electrode 1910: the first pattern 1920: second pattern 2200: Gate drive circuit 2210: Level shift circuit 2211: Scanning clock signal generator 2212: Sense clock signal generator 2213: Carry clock signal generator 2220: Gate signal output device 2400: Gate signal output unit 2410: output buffer circuit 2420: control logic circuit CPCB: Control printed circuit board FFC: Flexible flat cable SDIC: source drive integrated circuit SF: Film GDIC: Gate Drive Integrated Circuit GF: Film SP: sub pixel SP1~6: Sub-pixel SP11~64: sub-pixel SCAN: Scan signal SCAN1~6: Scan signal SCL: Scan signal line SCL1~6: Scan signal line SENSE: sense signal SENSE1~6: Sense signal SENL: Sensing signal line SEN1~6: Sensing signal line DL: Data line DL1~4: Data line DATA: image data DCS: Drive control signal GCS: Gate control signal DVL: drive voltage line RL: reference line EVDD: drive voltage EVSS: Reference voltage SCT: scanning transistor SENT: sensing transistor DT: drive transistor N1: the first node N2: second node N3: third node Cst: Capacitance EL: light-emitting unit R(n+1)~R(n+8): sub-pixel row EP: during glow NEP: Non-luminous period H: Horizontal time FDI: false data insertion BDI: black data insertion Vg: voltage of the first node Vs: voltage of the second node Vgs: potential difference Vgs(4): potential difference Vdata: image data voltage Vdata1~2: image data voltage Vref: Reference voltage Vfake: Fake data voltage Vblack: black data voltage Vpre: precharge data voltage A/A: Display block Spa: the first sub-pixel Spb: second sub-pixel Spc: third sub-pixel id: current 2id: combined current tPROG: During programming tFDI: false data insertion period tPC: during precharge tSHIFT/SEN: Scheduled sensing offset time tSHIFT/SCAN: scheduled scan offset time PROG2~5: Time point Wc: Channel width Lc: channel length CHc: Channel CNT: contact hole Ws: channel width Ls: channel length CHs: Channel LOGIC_SC: Scan logic unit LS_SC: Scan level shifter GCLK_SC: The first reference scan clock signal MCLK_SC: The second reference scan clock signal SC_CLK: scan clock signal SC_CLK(n): nth phase scan clock signal SC_CLK1 to SC_CLK8: scan clock signal LOGIC_SE: Sensing logic unit LS_SE: Sensing level shifter GCLK_SE: The first reference sense clock signal MCLK_SE: The second reference sense clock signal SE_CLK: sense clock signal SE_CLK(n): nth phase sensing clock signal SE_CLK1~SE_CLK8: sense clock signal DD: Delay device LOGIC_CR: Carry logic unit LC_CR: Carry level shifter GCLK_CR: The first reference carry clock signal MCLK_CR: The second reference carry clock signal CR_CLK: Carry clock signal CR_CLK(n): Carry clock signal of the nth phase CR_CLK1~CR_CLK8: Carry clock signal VGH: High-level gate voltage VGL: Low-level gate voltage CR(n-2): Carry signal NH1: The first clock signal node NH2: The second clock signal node NH3: The third clock signal node Nout1: the first connection point Nout3: second connection point Nout3: third connection point Tu1: The first pull-up transistor Tu3: second pull-up transistor Tu3: third pull-up transistor Td1: first pull-down transistor Td3: second pull-down transistor Td3: third pull-down transistor NL: Gate reference node GVSS: Gate reference voltage Q1~Q3: Node QB1~QB3: Node 0.8H: length of time 1.6H: Length of time

The above and other aspects, features, and advantages of the present invention will be more apparent after the following embodiments are combined with the drawings, in which: FIG. 1 is a system configuration diagram of a display device according to an embodiment of the present invention. FIG. 2 is a circuit diagram of the iso-calibration circuit of the sub-pixels placed in the display panel of the display device according to the embodiment of the present invention. FIG. 3 is a schematic diagram of a display device according to an embodiment of the present invention. FIG. 4 is a drawing of the dummy data insertion drive of the display device according to the embodiment of the present invention. 5 and FIG. 6 are driving timing diagrams of dummy data insertion driving and overlapping driving of the display device according to the embodiment of the present invention. FIG. 7 is a schematic diagram illustrating the brightness defect that occurs on a specific line when the display device of the embodiment of the present invention performs dummy data insertion driving and overlapping driving. FIG. 8 is a schematic diagram illustrating the cause of the brightness defect that occurs on a specific line when the display device of the embodiment of the present invention performs false data insertion driving and overlapping driving. FIG. 9 is a schematic diagram of the sub-pixels and signal lines provided on the display panel of the display device of the embodiment of the present invention. FIG. 10 is a driving timing diagram of the advanced overlapping driving of the display device according to the embodiment of the present invention. FIG. 11 is a driving timing diagram of the display device according to the embodiment of the present invention in the case of black data insertion driving and advanced overlap driving. FIG. 12 is a schematic diagram showing the state of the third sub-pixel and its neighboring sub-pixels during the programming period of the third sub-pixel. FIG. 13 is a schematic diagram showing the state of the fourth sub-pixel and its neighboring sub-pixels during the programming period of the fourth sub-pixel before the black data insertion driving is started. FIG. 14 is a schematic diagram showing the state of the fifth sub-pixel and its neighboring sub-pixels during the programming period of the fifth sub-pixel after the black data insertion driving is finished. FIG. 15 is a schematic diagram of the black data insertion drive of the display device according to the embodiment of the present invention. FIG. 16 is a schematic diagram of the pre-charge driving of the display device according to the embodiment of the present invention. FIG. 17 is a schematic diagram showing the setting range of the precharge data voltage used in the precharge drive of the display device according to the embodiment of the present invention. FIG. 18 is a schematic diagram of the scanning transistor of the display device according to the embodiment of the present invention. FIG. 19 is a schematic diagram of the sensing transistor of the display device according to the embodiment of the present invention. FIG. 20 is a flowchart of a driving method of a display device according to an embodiment of the present invention. FIG. 21 is a schematic diagram illustrating the effect of avoiding specific line brightness defects in the case of the display device of the embodiment of the present invention performing false data insertion driving and advanced overlapping driving. FIG. 22 is a schematic diagram of a gate driving circuit according to an embodiment of the present invention. FIG. 23 is a timing diagram of the gate driving circuit of the embodiment of the present invention. FIG. 24 is a schematic diagram of a gate signal output unit according to an embodiment of the present invention.

100: display device

110: display panel

120: data drive circuit

130: The first gate drive circuit

140: The second gate drive circuit

150: Controller

SP: sub pixel

SCAN: Scan signal

SCL: Scan signal line

SENSE: sense signal

SENL: Sensing signal line

DL: Data line

DATA: image data

DCS: Drive control signal

GCS: Gate control signal

Claims (20)

A gate drive circuit includes: a scan clock signal generator for receiving a first reference scan clock signal and a second reference scan clock signal, and for generating and outputting a scan clock signal; A sensing clock signal generator for receiving a first reference sensing clock signal and a second reference sensing clock signal, and for generating and outputting a sensing clock signal; and a gate signal output The device is used for outputting a scan signal with a conduction level voltage interval based on the scan clock signal, and for outputting a sensing signal with a conduction level voltage interval based on the sensing clock signal, wherein After the first reference scan clock signal rises and falls, the second reference scan clock signal rises and falls. After the first reference sensing clock signal rises and falls, the second reference sensing clock signal rises and falls. The signal rises and falls, wherein a high-level gate voltage interval of the sensing clock signal is delayed by a predetermined sensing offset time from a high-level gate voltage interval of the scanning clock signal, and wherein the sensing time The on-level voltage interval of the pulse signal is delayed by the predetermined sensing offset time from the on-level voltage interval of the scanning clock signal. The gate driving circuit according to claim 1, wherein the scan clock signal generator is used to generate and output the scan clock signal, and the scan clock signal rises at a rise time of the first reference scan clock signal , And fall during a fall time of the second reference scan clock signal, wherein the sensing clock signal generator is used to generate and output the sensing clock signal, and the sensing clock signal is in the second reference sensing The sensing clock signal rises at a rising time, instead of rising at a rising time of the first reference sensing clock signal, and the sensing clock signal is falling at a falling of the second reference sensing clock signal The time falls after a predetermined delay time, and a time interval between the rising time of the first reference sensing clock signal and the rising time of the second reference sensing clock signal corresponds to the predetermined Sense offset time. The gate driving circuit according to claim 2, wherein the rise time of the first reference sensing clock signal is the same as the rise time of the first reference scanning clock signal, and wherein the second reference sensing time The rising time of the pulse signal precedes a rising time of the second reference scan clock signal. The gate driving circuit according to claim 2, wherein a length of time during which the scanning clock signal and the sensing clock signal overlap each other corresponds to A value of the predetermined delay time is subtracted from a time length of the conduction level voltage interval of the sensing signal. The gate driving circuit according to claim 2, wherein the scan clock signal generator includes: a scan logic unit for receiving the first reference scan clock signal and the second reference scan clock signal, and generates The scan clock signal that rises at the rise time of the first reference scan clock signal and falls at the fall time of the second reference scan clock signal; and a scan level shifter for outputting The scanning clock signal that rises to a high-level gate voltage and drops to a low-level gate voltage, and wherein the sensing clock signal generator includes: a sensing logic unit for receiving the first reference sense Detect the clock signal and the second reference sense clock signal, and generate the sense clock signal, the sense clock signal rises at the rise time of the second reference sense clock signal, instead of at The rising time of the first reference sensing clock signal rises, and the sensing clock signal falls after the falling time of the second reference sensing clock signal passes the predetermined delay time; a delay device is used Delaying the rise time of the sense clock signal, so that the sense clock signal rises at the rise time of the second reference sense clock signal instead of at the rise time of the first reference sense clock signal Rise at this rise time; and A sensing level shifter for outputting the sensing clock signal rising to the high-level gate voltage and falling to the low-level gate voltage, and the sensing clock signal has a higher value than the scanning clock signal The high-level gate voltage interval delays the high-level gate voltage interval for the predetermined sensing offset time. The gate drive circuit according to claim 5, wherein the delay device includes one or more resistance elements. The gate drive circuit of claim 1, further comprising a carry clock signal generator for receiving a first reference carry clock signal and a second reference carry clock signal, and for generating and outputting a Carry clock signal. A display device includes: a display panel including a plurality of data lines, a plurality of scanning signal lines, a plurality of sensing signal lines, a plurality of reference lines, and a plurality of sub-pixels, wherein each of the sub-pixels includes: a light-emitting element; A driving transistor for driving the light-emitting element; a scanning transistor for controlling the connection between one of the data lines and a first node of the driving transistor according to a scan signal; and a sensing The transistor is used for controlling the connection between one of the reference lines and a second node of the driving transistor according to a sensing signal; and A capacitor connected between the first node and the second node of the driving transistor; a data driving circuit for driving the data lines; a first gate driving circuit for supplying a first scan Signal to a first scan signal line, wherein the first scan signal line is electrically connected to a gate node of the scan transistor in a first sub-pixel included in the sub-pixels, and the first scan signal A time interval with a turn-on level voltage; and a second gate drive circuit for supplying a first sensing signal to a first sensing signal line, wherein the first sensing signal line is electrically connected to the A gate node in the sensing transistor of the first sub-pixel, the first sensing signal has a time interval of a turn-on level voltage, and the turn-on level voltage of the first sensing signal line is The time interval is delayed by a predetermined sensing offset time from the time interval of the conduction level voltage of the first scan signal line. The display device according to claim 8, wherein the time interval of the turn-on level voltage of the first sensing signal includes: among them, the time interval of the turn-on level voltage of the first sensing signal A period of the time interval during which the conduction level voltage of the first scan signal is overlapped; and in which, the time interval of the conduction level voltage of the first sensing signal does not overlap the time interval of the first scan signal A period of the time interval of the turn-on level voltage. The display device according to claim 9, wherein the period of the time interval of the turn-on level voltage of the first sensing signal overlaps the time interval of the turn-on level voltage of the first scan signal corresponds to a programming During the programming period, the image data is programmed to the first sub-pixel. The display device according to claim 8, wherein a start point of the time interval of the conduction level voltage of the first sensing signal is greater than a start point of the time interval of the conduction level voltage of the first scan signal The point is delayed by the predetermined sensing offset time, and the predetermined sensing offset time corresponds to one-half of the time interval of the conduction level voltage of the first scan signal. The display device according to claim 8, wherein the sub-pixels further include a second sub-pixel and a third sub-pixel, wherein the first sub-pixel, the second sub-pixel, and the third sub-pixel include the The multiple drain nodes or multiple source nodes of the sensing transistors are electrically connected to the same reference line, and when a second scan signal with a turn-on level voltage is supplied to the second sub-pixel A gate node of the scanning transistor, and when a second sensing signal with a turn-on level voltage is supplied to a gate node of the sensing transistor of the second sub-pixel At this point, there is a point in time when the sensing transistor of the first sub-pixel and the sensing transistor system of the third sub-pixel are turned off at the same time. The display device according to claim 8, wherein during the period during which the i-th scan signal having a turn-on level voltage is supplied to the i-th scan signal line of the scan signal lines, and the first scan signal with a turn-on level voltage (i+1) The scan signal is supplied to the (i+1)th scan signal line among the scan signal lines. In a period between the scan signal lines, a dummy data voltage that is different from a real image data voltage is It is supplied to a plurality of sub-pixels arranged in k sub-pixel lines, where i is a natural number equal to or greater than 1, and k is a natural number equal to or greater than 1. The display device according to claim 8, wherein the sub-pixels further include a second sub-pixel connected to a second scanning signal line for transmitting a second scanning signal, and connected to a second scanning signal line for transmitting a second scanning signal. A second sensing signal line for sensing signals, wherein the time interval of the on-level voltage of the first sensing signal is delayed by the predetermined sensing time interval from the time interval of the on-level voltage of the first scanning signal The offset time is measured, and the time interval of the turn-on level voltage of the first sensing signal overlaps the time interval of the turn-on level voltage of the first scan signal for a predetermined programming period, wherein the second When a time interval of a turn-on level voltage of the sensing signal is delayed by the predetermined sensing offset from a time interval of a turn-on level voltage of the second scan signal And the time interval of the turn-on level voltage of the second sensing signal overlaps the time interval of the turn-on level voltage of the second scan signal for the predetermined programming period, wherein the time interval of the second scan signal The time interval of the conduction level voltage overlaps the time interval of the conduction level voltage of the first scan signal, and the time interval of the conduction level voltage of the second scan signal is greater than that of the first sensing signal The time interval of the turn-on level voltage is delayed by a predetermined scan offset time, and the time interval in which the turn-on level voltage of the second sensing signal does not overlap the turn-on level voltage of the first scan signal The time interval. The display device according to claim 13, wherein the dummy data voltage is a black data voltage or a low gray-scale data voltage. The display device according to claim 8, wherein a ratio of a channel width of the sensing transistor to a channel length is greater than a ratio of a channel width of the scanning transistor to a channel length. A method for driving a display device includes: supplying a first scan signal to a first scan signal line, wherein the first scan signal line is electrically connected to a scan circuit in a first sub-pixel included in a plurality of sub-pixels A gate node of the crystal, and the first scan signal has a time interval of a turn-on level voltage, so that an image data voltage supplied from a data line is transmitted to the first sub-pixel through the scan transistor A first node of the driving transistor; Supply a first sensing signal to a first sensing signal line, wherein the first sensing signal line is electrically connected to a gate node in a sensing transistor of the first sub-pixel, and the first sensing The signal has a time interval of a turn-on level voltage, so that a reference voltage supplied from a reference line is transmitted to a second node of the driving transistor through the sensing transistor, wherein the first sensing signal line The time interval of the turn-on level voltage is delayed by a predetermined sensing offset time from the time interval of the turn-on level voltage of the first scan signal line; and a time interval with a turn-off level voltage is supplied The first scanning signal is supplied to the first scanning signal line and the first sensing signal having a time interval with a turn-off level voltage is supplied to the first sensing signal line. The method for driving a display device according to claim 17, wherein the time interval of the on-level voltage of the first sensing signal includes: among them, the time interval of the on-level voltage of the first sensing signal The time interval overlaps a period of the time interval of the conduction level voltage of the first scan signal; and in it, the time interval of the conduction level voltage of the first sensing signal does not overlap the first A period of the time interval of the turn-on level voltage of the scan signal. The method for driving a display device according to claim 17, wherein a starting point of the time interval of the on-level voltage of the first sensing signal is greater than that of the first The time interval of the turn-on level voltage of the scan signal is delayed by the sensing offset time, and the sensing offset time corresponds to half of the time interval of the turn-on level voltage of the first scan signal one. The method for driving a display device according to claim 17, wherein during the period during which the i-th scan signal having a turn-on level voltage is supplied to the i-th scan signal line of the plurality of scan signal lines, it has a turn-on level voltage During a period between when the (i+1)th scan signal is supplied to the (i+1)th scan signal line of the scan signal lines, a dummy data voltage that is different from a real image data voltage It is supplied to a plurality of sub-pixels arranged in k sub-pixel lines, where i is a natural number equal to or greater than 1, and k is a natural number equal to or greater than 1.

Images