KR101428713B1 - Gate driving circuit and liquid crystal display using thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display device. A liquid crystal display device of the present invention includes a timing controller, a level shifter, and first and second gate driving circuits. The timing controller generates an output enable signal, a gate clock, and a start signal in response to an external input signal. The level shifter generates a gate clock pulse and a gate clock bar pulse in response to the output enable signal and the gate clock, and generates a start pulse in response to the start signal. The first and second gate driving circuits output a gate clock pulse or a gate clock bar pulse in response to the start pulse as a gate driving signal to be supplied to a plurality of gate lines.

Description

TECHNICAL FIELD [0001] The present invention relates to a gate driving circuit and a liquid crystal display device using the gate driving circuit.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is a diagram showing the input / output signal relationship of the first and second level shifters shown in FIG. 1,

3 is an exemplary circuit diagram of the first level shifter shown in FIG. 2,

4 is a block diagram of the first and second gate driving circuits shown in FIG. 2,

5 is an exemplary circuit diagram of a stage of the first gate driving circuit shown in FIG.

FIG. 6A and FIG. 6B are graphs illustrating a simulation graph for comparing the operation according to the start pulse of the liquid crystal display device according to an embodiment of the present invention and the conventional liquid crystal display device,

Fig. 7 is a block diagram of other first and second gate driving circuits shown in Fig. 2, and

8A and 8B are simulation graphs for comparing the operation of a gate driving circuit of a liquid crystal display device according to another embodiment of the present invention and a conventional liquid crystal display device.

Description of the Related Art [0002]

100: liquid crystal display device 110: liquid crystal panel

120: Data driver 130: First gate driving circuit

140: second gate driving circuit 150: first level shifter

160: second level shifter 170: timing controller

180: Power supply

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device including a gate driving circuit.

In general, a liquid crystal display device includes a liquid crystal panel for displaying an image, a data driver for driving the liquid crystal panel, and a gate driver. A liquid crystal panel includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels. The pixel consists of a thin film transistor and a liquid crystal capacitor. The data driver outputs a data signal to the data line, and the gate driver outputs a gate driving signal.

The gate driver is simultaneously formed on the liquid crystal panel through the same process as the thin film transistor, and the data driver is formed in a chip form and connected to the peripheral area of the liquid crystal panel. The gate driver includes a shifter register having a plurality of stages, and each of the stages is connected to a corresponding gate line to output a gate driving signal.

The gate driving unit is connected to each other in order to sequentially output the gate driving signals to the plurality of gate lines. The input terminal of the current stage is connected to the output terminal of the previous stage and the output terminal of the next stage is connected to the control terminal of the current stage. The start signal of the first stage of the plurality of stages is input.

The gate driver is formed on the left and right sides of the liquid crystal panel so that the gate driver circuit on the left drives the odd gate lines and the gate driver on the right drives the even gate lines in the single drive scheme.

In a single-drive liquid crystal display device, a deviation occurs as the gate drive signal output from the left and right gate drive circuits goes to the end of the gate line due to gate line delay (Gate Line Delay). The deviation of the gate driving signal causes a shortage of the charging time of the pixel, thereby causing a phenomenon of horizontal line vision.

In order to solve the problem of shortage of the pixel charging time of the single driving type, a dual driving method in which the same gate control circuit is formed on the right and left sides of the liquid crystal panel and the same gate driving signal is applied to the gate lines on the left and right sides have.

However, in the conventional dual-drive type liquid crystal display device, the number of signal lines connected to the gate drive circuit is doubled as compared with the single drive type, and it is required to secure the integrated space of the liquid crystal panel. The change in the integrated space of the liquid crystal panel means a change in the size of the liquid crystal panel, which requires a change in the equipment used in the conventional liquid crystal panel manufacturing process, thereby raising the manufacturing cost of the liquid crystal panel.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a liquid crystal display device and a liquid crystal display The present invention has been made in view of the above problems.

According to an aspect of the present invention, there is provided a gate driving circuit including a plurality of gate driving pulses and a plurality of gate driving pulses, each of which is connected in dependence to one another in order to output a gate clock pulse or a gate clock bar pulse in response to one start pulse, Wherein the plurality of stages include: a circuit part having output terminals connected to corresponding to a plurality of gate lines, respectively; And a wiring portion having a start pulse wiring for receiving the start pulse from the outside and providing the start pulse wiring to the input terminals of the odd-numbered first stage and the even-numbered first stage of the plurality of stages.

Preferably, the odd-numbered stages of the plurality of stages output the gate clock pulse as the gate driving signal and the even-numbered stage outputs the gate clock bar pulse as the gate driving signal.

The plurality of stages may be configured such that each input terminal is connected to an output terminal of a previous stage, each control terminal is connected to a carry terminal of a next stage, and the first stage of the odd- It is preferable that the one start signal is input to the input terminal.

The odd-numbered stage includes a first dummy stage in which a carry terminal is connected to a control terminal of the last odd-numbered stage, and the even-numbered stage has a second dummy stage in which a carry terminal is connected to a control terminal of the last even- .

The wiring portion further includes a reset wiring connecting the carry terminal of the second dummy stage and the reset terminal of the plurality of stages.

A liquid crystal display device of the present invention includes a timing controller for generating an output enable signal, a gate clock, and a start signal in response to an external input signal; A level shifter for generating a gate clock pulse and a gate clock bar pulse in response to the output enable signal and the gate clock and generating a start pulse in response to the start signal; And first and second gate driving circuits for outputting the gate clock pulse or the gate clock bar pulse to a plurality of gate lines in response to the one start pulse.

Here, it is preferable that the first and second gate driving circuits include a plurality of stages connected to each other in a dependent manner, and the output terminals of the plurality of stages are respectively connected to the plurality of gate lines.

Further, the liquid crystal display of the present invention may further include a power supply unit for supplying the gate-on voltage and the gate-off voltage to the level shifter, wherein the level shifter is configured to apply the gate clock pulse having the gate- , A gate clock bar pulse, and a start pulse.

The level shifter may further include: a first level shifter for logically computing the output enable signal and the gate clock, amplifying the level of the voltage, and outputting the amplified voltage as the gate clock pulse; And a second level shifter for logically computing the output enable signal and the gate clock, inverting the phase, amplifying the level of the voltage, and outputting the amplified signal as the gate clock bar pulse.

It is also preferable that the first and second gate driving circuits are integrated in a liquid crystal panel having the gate lines formed therein, and the gate lines are formed at both ends of the gate lines to drive the gate lines in a dual mode.

A liquid crystal display device of the present invention includes a timing controller for generating an output enable signal, a gate clock, and a start signal in response to an external signal; A level shifter for generating a gate clock pulse, a gate clock bar pulse and a start pulse in response to the output enable signal and the gate clock; And first and second gate driving circuits for sequentially outputting a gate driving signal to the plurality of data lines, the plurality of gate lines, and the gate lines, wherein the first and second gate driving circuits generate the one start pulse And a liquid crystal panel for outputting the gate clock pulse or the gate clock bar pulse in response to the gate driving signal.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a liquid crystal display according to an embodiment of the present invention. 1, a liquid crystal display 100 according to an exemplary embodiment of the present invention includes a liquid crystal panel 110, a data driver 120, first and second gate driving circuits 130 and 140, First and second level shifters 150 and 160, a timing controller 170, and a power supply 180.

The liquid crystal panel 110 includes a thin film transistor substrate 112, a color filter substrate 114 and a liquid crystal (not shown) disposed between the thin film transistor substrate 112 and the color filter substrate 114.

The thin film transistor substrate 112 includes a display area DA and first and second peripheral areas PA1 and PA2. The display region DA includes gate lines GL1 to GLn, data lines DL1 to DLm, gate lines GL1 to GLn and data lines DL1 to & , And DLm are formed. In the first peripheral area PA1, first and second gate driving circuits 130 and 140 for driving the gate lines GL1, ..., and GLn are formed. In the second peripheral area PA2, a data driver 120 driving the data lines DL1, ..., DLm is mounted. The first peripheral area PA1 is adjacent to both ends of the gate lines GL1 through to GLn and the second peripheral area PA2 is adjacent to the one ends of the data lines DL1 through to DLm. Lt; RTI ID = 0.0 >

The pixel includes a thin film transistor TFT connected to the gate lines GL1 through to the data lines DL1 through to DLm, a liquid crystal capacitor CLC connected to the thin film transistor TFT, (CST). The gate and the source of the thin film transistor TFT are connected to the gate lines GL1 to GLn and the data lines DL1 to DLm respectively and the drain is connected to the liquid crystal capacitor CLC and the storage capacitor CST, Lt; / RTI > The liquid crystal capacitor CLC has a pixel electrode and a common electrode as two terminals, and is formed of a liquid crystal functioning as a dielectric between two terminals.

The color filter substrate 114 is formed with a black matrix for preventing light leakage, a color filter for color implementation, and a common electrode. The liquid crystal is a material having a dielectric anisotropy and rotates due to a difference in voltage applied to the common electrode and the pixel electrode to control the transmittance of light.

The first and second gate driving circuits 130 and 140 are formed by being integrated into one side of the liquid crystal panel 110 and the first peripheral area PA1 on the other side of the gate lines GL1 through to GLn, And its output is connected to each of the gate lines GL1, ..., and GLn. The first and second gate driving circuits 130 and 140 sequentially provide gate driving signals at both ends of the gate lines GL1 to GLn to simultaneously drive the gate lines GL1 to GLn .

The data driver 120 receives a data control signal and data from the timing controller 140 and selects an analog driving voltage AVDD corresponding to the data and provides the analog driving voltage AVDD to the data lines DL1 to DLm. The data driver 120 is implemented as an integrated chip and is mounted on the second peripheral area PA2 of the thin film transistor substrate 112. [ The data driver 120 is connected to the timing controller 170 and the power supply unit 180 through a flexible circuit board 102 connected to the second peripheral area PA2.

In this embodiment, the data driver 120 is mounted on the thin film transistor substrate 112 using a chip on glass (COG) method. However, the data driver 120 may be implemented using a TCP (Tape Carrier Package) structure.

The first and second level shifters 150 and 160 receive the gate control signal from the timing controller 140 and receive the driving voltage from the power supply unit 180 to drive the gate driving circuits 130 and 140 And provides it to the first and second gate driving circuits 130 and 140. [

The timing controller 140 receives data and an input control signal from the outside, generates a gate control signal and a data control signal, and provides the gate control signal and the data control signal to the first and second level shifters 150 and 160 and the data driver 120. Here, the data is an RGB video signal, and the input control signal includes a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, a main clock MCLK, and a data enable signal DE.

The power supply unit 180 generates an analog driving voltage AVDD, a common voltage VCOM, and a gate driving voltage using a power supply voltage supplied from the outside. The power supply unit 180 supplies the analog driving voltage AVDD to the data driver 120 and supplies the common voltage VCOM to the common electrode of the liquid crystal panel 110 and supplies the gate driving voltage to the first and second levels Shifters 150 and 160, respectively.

The timing controller 170, the first and second level shifters 150 and 160, and the power supply unit 180 are mounted on the control printed circuit board 104. The control printed circuit board 104 is connected to the second peripheral area PA2 of the thin film transistor substrate 112 through the flexible circuit board 102. [ The first and second gate driving circuits 130 and 140 formed on the liquid crystal panel 110 are connected to the timing controller 140 and the power supply unit 180 through the data driver 120 or through the flexible circuit board 102, Can be connected.

FIG. 2 is a diagram showing the relationship between input and output signals of the first and second level shifters shown in FIG. As shown in FIG. 2, the first and second level shifters 150 and 160 are supplied with a gate-on voltage VON and a gate-off voltage VOFF, which are gate drive voltages, from the power supply unit 180.

The first and second level shifts 150 and 160 receive the output enable signal OE, the first and second gate clocks CPV1 and CPV2 and the gate start signal STV ). Here, the second gate clock CPV2 is a clock whose phase of the first gate clock CPV1 is delayed. The phase difference between the first and second gate clocks CPV1 and CPV2 is a period in which gate drive signals provided to adjacent gate lines overlap. The gate start signal STV is a signal indicating the start of one frame.

The first and second level shifters 150 and 160 generate a start pulse STVP having a gate-on voltage VON and a gate-off voltage VOFF level in response to a gate control signal, first and second gate clock pulses CKV1 , CKV2 and first and second gate clock bar pulses CKVB1 and CKVB2. Here, the start pulse STVP causes the gate drive circuits 130 and 140 to generate the first gate drive signal of one frame. The first and second gate clock bar pulses CKVB1 and CKVB2 are signals for speeding up the driving of the gate line.

The first and second level shifters 150 and 160 generate the generated start pulse STVP and the first and second gate clock pulses CKV1 and CKV2 and the first and second gate clock bar pulses CKVB1 and CKVB2 And provides the data to the first and second gate driving circuits 130 and 140 through the data driver 120.

The first and second level shifters 150 and 160 according to the present embodiment generate one start pulse STVP in the first and second gate drive circuits 130 and 140, Circuit 130 and 140, respectively. When the start pulse STVP is input, the first and second gate drive circuits 130 and 140 generate and supply a gate drive signal to the gate line.

3 is an exemplary circuit diagram of the first level shifter shown in FIG. As shown in FIG. 3, the first level shifter 130 includes a first level shifter 132, a second level shifter 134, and a third level shifter 136.

The first level shifting unit 132 performs logic operation on the output enable signal OE and the gate clock CPV1 and amplifies the level of the voltage to generate a gate clock to be provided to the first and second gate driving circuits 130 and 140 Thereby generating the pulse CKV1. To this end, the first level shifting unit 132 includes a logic operation unit LG1, a drive inverter INV1, and a full swing inverter 133. [

The logic operation unit LG1 performs an OR operation on the output enable signal OE and the first gate clock CPV1. The drive inverter INV1 inverts the phase of the output of the logic operation unit LG1 and amplifies it to the drive level of the full swing inverter 133. [ The full swing inverter 133 generates a first gate clock pulse CKV1 having a gate-on voltage VON and a gate-off voltage VOFF level in response to the output of the drive inverter INV1.

The second level shifter 134 performs a logic operation on the output enable signal OE and the first gate clock CPV1 to amplify the level of the voltage to provide the first and second gate driving circuits 130, Thereby generating a gate clock bar pulse CKVB1. The second level shifting unit 134 includes a logic operation unit LG2, an inverting inverter INV2, a driving inverter INV3, and a full swing inverter 135 for this purpose. Here, the first gate clock bar pulse CKVB1 is a clock in which the phase of the first gate clock pulse CKV1 is inverted.

The logical operation unit LG2 performs an OR operation on the output enable signal OE and the first gate clock CPV1. The inverting inverter INV2 inverts the phase of the output of the logic operation unit LG1 and outputs it. The drive inverter INV3 inverts the phase of the output of the inverter INV2 and amplifies it to the drive level of the full swing inverter 135. [ The full swing inverter 135 generates a first gate clock bar pulse CKVB1 with a gate on voltage VON and a gate off voltage VOFF level in response to the output of the drive inverter 135.

The third level shifter 136 receives the output enable signal OE and the gate start signal STV and generates a start pulse STVP having a gate-on voltage VON and a gate-off voltage VOFF level. Here, the start pulse STVP has the same period and pulse width as the gate start pulse STV, and the voltage level has the gate-on voltage VON and the gate-off voltage VOFF level.

On the other hand, the second level shifter 140 receives a gate-on voltage VON and a gate-off voltage VOFF, which are gate drive voltages, from the power supply unit 180 and receives an output enable signal OE, The start pulse STVP of the gate-on voltage VON and the gate-off voltage VOFF level, the second gate clock pulse CKV2, and the second gate clock pulse CKV2, which are supplied with the second gate clock CPV2 and the gate start signal STV, 2 gate clock bar pulse CKVB2 and supplies it to the first and second gate driving circuits 130 and 140. [ The configuration and operation of the second level shifter 140 are similar to those of the first level shifter 130 described above, and thus a detailed description thereof will be omitted.

4 is a block diagram of the configuration of the first and second gate driving circuits shown in FIG. 4, the first and second gate driving circuits 130 and 140 are provided on both sides of the display area DA so as to drive the gate lines GL1, ..., Respectively. The first and second gate driving circuits 130 and 140 have a structure symmetrical with respect to the gate lines GL1, ..., and GLn.

The first gate driving circuit 130 includes a wiring portion 134 for receiving various signals from the data driving portion 120 and transferring the signals and a circuit portion 132 for sequentially outputting gate driving signals in response to various signals.

The circuit unit 132 is composed of a shifter register including a plurality of stages STAGE1, ..., STAGEn + 2 that are connected to each other. The first to n-th stages STAGE1, ..., STAGEn are electrically connected to the first to n-th gate lines GL1, ..., GLn to sequentially output gate driving signals. The n + 1 stage STAGEn + 1 and the n + 2 stage STAGEn + 2 are dummy stages. Where n is an even number.

Each of the plurality of stages STAGE1 to STAGEn + 2 includes first and second clock terminals CK1 and CK2, an input terminal IN, a control terminal CT, an output terminal OUT, (RE), a carry terminal (CR), and a ground voltage terminal (VSS).

The odd-numbered stages STAGE1, STAGE3, ..., STAGEn + 1 of the plurality of stages STAGE1, ..., STAGEn + 2 are connected to the first clock terminal CK1 and the second clock terminal CK2, A gate clock pulse (CKV1) or a second gate clock bar pulse (CKVB1) is provided.

More specifically, the STAGE1, STAGE5, ..., STAGEn-1 stages of the odd-numbered stages are provided with the first gate clock pulse CKV1 at the first clock terminal CK1 and the first gate clock pulse CKV1 at the second clock terminal CK2, A gate clock bar pulse (CKVB1) is provided. In the stages STAGE3, STAGE7, ..., and STAGEn + 1 of the odd-numbered stages, a first gate clock bar pulse CKVB1 is provided to the first clock terminal CK1, a first gate clock pulse CKVB1 is supplied to the second clock terminal CK2, (CKV1) is provided.

The input terminal IN of the odd-numbered stages STAGE1, STAGE3, ..., STAGEn + 1 is connected to the carry terminal CR of the previous odd-numbered stage to provide the carry signal of the odd- CT) is connected to the output terminal OUT of the next odd-numbered stage, and the output signal of the next odd-numbered stage is provided. The odd-numbered first stage STAGE1 is provided with the start pulse STVP at the input terminal IN since no previous stage exists. The carry signal output from the carry terminal CR serves to drive the next odd stage.

it is preferable that the start pulse STVP is provided to the control terminal CT of the dummy stage STAGEn + 1 which provides a carry signal to the control terminal CT of the (n-1) th stage STAGEn-1. The ground voltage VOFF is provided to the ground voltage terminal VSS of the odd-numbered stages STAGE1, STAGE3, ..., STAGEn + 1 and the output of the n + 1 stage STAGEn + 1 is supplied to the reset terminal RE. Signal is provided.

The output terminal OUT of the STAGE1, STAGE5, ..., STAGEn-1 stage outputs the first gate clock pulse CKV1 as the gate driving signal, the carry terminal CR outputs the first gate clock pulse CKV1, As a carry signal. The output terminal OUT of the STAGE3, STAGE7, ..., STAGEn + 1 stages outputs the first gate clock bar pulse CKVB1 as the gate driving signal, the carry terminal CR outputs the first gate clock pulse CKVB1, As a carry signal.

The even-numbered stages STAGE2, STAGE4, ..., STAGEn + 2 of the plurality of stages STAGE1, ..., STAGEn + 2 are connected to the first clock terminal CK1 and the second clock terminal CK2, A gate clock pulse CKV2 and a second gate clock bar pulse CKVB2 are provided.

More specifically. In the STAGE2, STAGE6, ..., and STAGEn stages of the even-numbered stages, a second gate clock pulse CKV2 is supplied to the first clock terminal CK1 and a second gate clock pulse CKVB2 is supplied to the second clock terminal CK2. Is provided. The second gate clock bar pulse CKVB2 is provided to the first clock terminal CK1 and the second gate clock pulse CKVB2 is supplied to the second clock terminal CK2. In the STAGE4, STAGE8, ..., STAGEn + (CKV2) is provided.

The input terminal IN of the even-numbered stages STAGE2, STAGE4, ..., STAGEn + 2 is connected to the carry terminal CR of the previous even-numbered stage to provide the carry signal of the previous even- CT) is connected to the output terminal OUT of the next even-numbered stage to provide the output signal of the next even-numbered stage. The even-numbered first stage STAGE1 is provided with the start pulse STVP at the input terminal IN since no previous stage exists. The carry signal output from the carry terminal CR serves to drive the next even stage.

it is preferable that the start pulse STVP is provided to the control terminal CT of the dummy stage STAGEn + 2 which provides a carry signal to the control terminal CT of the n-th stage STAGEn. The ground voltage VOFF is supplied to the ground voltage terminal VSS of the even stages STAGE2, STAGE4, ..., STAGEn + 2 and the output of the stage n + 2 stage STAGEn + 2 is supplied to the reset terminal RE. Signal is provided.

The output terminal OUT of the STAGE2, STAGE6 ... STAGEn stage outputs the second gate clock pulse CKV2 as the gate driving signal and the carry terminal CR outputs the second gate clock pulse CKV2 as the gate driving signal. Signal. The output terminal OUT of the STAGE4, STAGE8, ..., STAGEn + 2 stage outputs the second gate clock bar pulse CKVB2 as the gate driving signal, and the carry terminal CR outputs the second gate clock bar pulse CKVB2 ) As a carry signal.

The first gate driving circuit 130 is controlled such that the odd-numbered stages STAGE1, STAGE3, ..., STAGEn + 1 are synchronized with the first gate clock pulse CKV1 and the first gate clock bar pulse CKVB1 And the even-numbered stages STAGE2, STAGE4, ..., STAGEn + 2 operate in synchronization with the second gate clock pulse CKV2 and the second gate clock bar pulse CKVB1.

The output terminals OUT of the plurality of stages STAGE1 to STAGEn + 1 of the first gate driving circuit 130 are connected to the gate lines GL1 to GLn formed in the display area DA And sequentially supplies the gate driving signals to the gate lines GL1, ..., and GLn to sequentially drive the gate lines GL1, ..., and GLn.

The wiring portion 134 is formed adjacent to the circuit portion 132. The wiring portion 134 includes a start pulse wiring SL1, a first gate clock pulse wiring SL2, a first gate clock bar pulse wiring SL3, a second gate clock pulse wiring SL4, Two gate clock bar pulse wiring SL5, a ground voltage wiring SL6, a first reset wiring SL7, and a second reset wiring SL5.

The start pulse wiring SL1 receives the start pulse STVP from the first level shifter 150 and inputs it to the control terminal CT of the (n + 1) th stage STAGEn + 1 and the input terminal of the first stage STAGE1 do.

The first gate clock pulse line SL2 receives the first gate clock pulse CKV1 from the first level shifter 150 and receives the first clock CLK1 of the STAGE1, STAGE5, ..., STAGE n-1 stages of the odd- And provides it to the second clock terminal CK2 of the STAGE3, STAGE7, ..., STAGE n + 1 stages.

The first gate clock bar pulse wiring SL3 receives the first gate clock bar pulse CKVB1 from the first level shifter 150 and receives the first gate clock bar pulse CKVB1 of the first Clock terminal CK1 and provides it to the second clock terminal CK2 of the STAGE3, STAGE7, ..., STAGE n + 1 stages.

The second gate clock pulse line SL4 receives the second gate clock pulse CKV2 from the second level shifter 160 and receives the second gate clock pulse CKV2 from the first clock terminal (STAGE2, STAGE6, CK1, and provides it to the second clock terminal CK2 of the STAGE4, STAGE8, ..., STAGE n + 2 stages.

The second gate clock bar pulse wiring SL5 receives the second gate clock bar pulse CKVB2 from the second level shifter 160 and receives the first gate clock bar pulse CKVB2 of the first stage clock signal STAGE4, STAGE8, ..., STAGE n + To the clock terminal CK1, and to the second clock terminal CK2 of the STAGE2, STAGE6, ..., STAGE n stages.

The ground voltage wiring line SL6 receives the gate off voltage VOFF from the power supply unit 180 and supplies the ground voltage terminal VSS to the ground voltage terminals VSS of the first to (n + 2) th stages STAGE1 to STAGEn + do.

The first reset interconnection SL7 outputs the output signal of the output terminal OUT of the (n + 2) th stage STAGEn + 2 to the reset terminal RE of the even-numbered stages STAGE2, STAGE4 ... STAGEn + to provide.

The second reset interconnection SL8 outputs the output signal of the output terminal OUT of the (n + 1) th stage STAGE n + 1 to the reset terminal RE of the odd-numbered stages STAGE1, STAGE3, ..., STAGEn + .

The first and second gate driving circuits 130 and 140 have a structure symmetrical to each other with respect to the gate lines GL1 to GLn and are connected to the first gate driving circuit 130 to the second gate driving circuit 140, the detailed description of the second gate driving circuit 140 will be omitted.

5 is an exemplary circuit diagram of the first stage shown in FIG. The first stage shown in Fig. 4 has the same configuration as the second to (n + 2) stages, and thus explains the internal configuration of the first stage and replaces the description of the configurations of the second to .

 5, the first stage STAGE1 includes a pull-up portion 132a, a pull-down portion 132b, a driving portion 132c, a holding portion 133d, a switching portion 133e, and a carry portion 133f. .

The pull-up unit 132a pulls up the first gate clock pulse CKV1 provided through the first clock terminal CK1 and outputs it as a gate driving signal through the output terminal OUT. Up section 132a includes a first transistor NT1 whose gate is connected to the first node N1 and whose drain is connected to the first clock terminal CK1 and whose source is connected to the output terminal OUT .

The pull down portion 132b pulls down the pulled-up gate drive signal to the gate off voltage VOFF provided through the ground voltage terminal VSS in response to the carry signal from the third stage STAGE3. Pull down portion 132b includes a second transistor NT2 whose gate is connected to the control terminal CT and whose drain is connected to the output terminal OUT and whose source is connected to the ground voltage terminal VSS.

The driving unit 132c turns on the pull-up unit 132a in response to the start pulse STVP provided through the input terminal IN and turns it off in response to the carry signal of the third stage STAGE3. To this end, the driving unit 132c includes a buffer unit, a charging unit, and a discharging unit.

The buffer section includes a third transistor NT3 whose gate and drain are commonly connected to the input terminal IN and whose source is connected to the first node N1. The charging unit includes a first capacitor C1 having a first electrode connected to the first node N1 and a second electrode connected to the second node. The discharging portion includes a fourth transistor NT4 having a gate connected to the control terminal CT and a drain connected to the first node N1 and a source connected to the ground voltage terminal VSS.

When the start pulse STVP is input to the input terminal IN, the third transistor NT3 is turned on and the start pulse STVP is charged to the first capacitor C1 in response to the start pulse STVP. When the first capacitor NT1 is charged with a voltage equal to or higher than the threshold voltage of the first transistor NT1, the first transistor NT1 is turned on to supply the first gate clock pulse CKV1 supplied to the first clock terminal CK1 Output terminal OUT.

At this time, the potential of the node 1 N1 is bootstrapped by the amount of potential change of the node 2 (N2) by the coupling of the first capacitor C1 according to the sudden change of the potential of the node 2 (N2) do. Therefore, the first transistor NT1 can easily output the first gate clock pulse CKV1 applied to the drain to the output terminal OUT. The first gate clock pulse CKV1 output to the output terminal OUT becomes a gate driving signal provided to the gate line. Here, the start pulse STVP is used as a signal for preliminarily charging the first transistor NT1 to generate the first gate drive signal.

Thereafter, when the fourth transistor NT4 is turned on in response to the carry signal of the third stage STAGE3 inputted through the control terminal CT, the charge charged in the first capacitor C1 flows through the ground voltage terminal VSS And is discharged to the provided gate-off voltage (VOFF) level.

The holding unit 133d includes fifth and sixth transistors NT5 and NT6 for holding a gate driving signal at a gate-off voltage (VOFF) level. The fifth transistor NT5 has a gate connected to the third node N3, a drain connected to the second node N2, and a source connected to the ground voltage terminal VSS. The sixth transistor N6 has a gate connected to the second clock terminal CK2, a drain connected to the second node, and a source connected to the ground voltage terminal VSS.

The switching unit 133e includes the seventh, eighth, ninth and tenth transistors NT7, NT8, NT9 and NT10 and the second and third capacitors C2 and C3 to drive the holding unit 133d . The seventh transistor NT7 has a gate and a drain connected to the first clock terminal CK1 and a source connected to the third node. The eighth transistor NT8 has a drain connected to the first clock terminal CK1 and a gate connected to the drain through the second capacitor C2 and a source connected to the third node, Lt; / RTI > The ninth transistor NT9 has a drain connected to the source of the seventh transistor NT7, a gate connected to the second node N2, and a source connected to the ground voltage terminal VSS. The tenth transistor NT10 has a drain connected to the third node N3, a gate connected to the second node N2, and a source connected to the ground voltage terminal VSS.

When a high-level gate clock pulse is output to the output terminal OUT as a gate driving signal, the potential of the second node N2 rises to a high level. When the potential of the second node N2 rises to a high state, the ninth and tenth transistors NT9 and NT10 are turned on. At this time, even if the seventh and eighth transistors NT7 and NT8 are turned on by the first gate clock pulse CKV1 braked to the first clock terminal CK1, the signals output from the seventh and eighth transistors are And is discharged to the ground voltage (VOFF) through the ninth and tenth transistors NT9 and NT10. Accordingly, the third node N3 maintains the low level while the high-level gate driving signal is output, so that the fifth transistor NT5 maintains the turn-off state.

Thereafter, in response to the carry signal of the third stage STAGE3 inputted through the control terminal CT, the gate driving signal is discharged through the ground voltage terminal VSS, and the potential of the second node N2 is low Gradually descend. Accordingly, the ninth and tenth transistors NT9 and NT10 are turned off, and the potential of the third node N3 is raised to a high state by the signals output from the seventh and eighth transistors NT7 and NT8 do. As the potential of the third node N3 rises, the fifth transistor NT5 is turned on and the potential of the second node N2 is discharged to the ground voltage VOFF through the fifth transistor NT5.

In this state, when the sixth transistor NT6 is turned on by the first gate clock bar pulse CVKB1 provided to the second clock terminal CK2, the potential of the second node N2 becomes equal to the ground voltage terminal VSSS Thereby discharging it more reliably.

As a result, the fifth and sixth transistors NT5 and NT6 of the holding portion 132d hold the potential of the second node N2 at the ground voltage (VOFF) state. The switching unit 132e determines when the fifth transistor NT5 is turned on.

The carry section 133f includes an eleventh transistor NT11 having a drain connected to the first clock terminal CK1 and a gate connected to the first node N1 and a source connected to the carry terminal CR. The eleventh transistor NT11 turns on as the potential of the first node N1 rises and outputs the first gate clock pulse CKV1 input to the drain to the carry terminal CR.

Meanwhile, the first stage STAGE1 further includes a ripple prevention portion 132g and a reset portion 132h. The ripple prevention portion 132g prevents the gate drive signal, which is already held in the ground voltage (VOFF) state, from being ripple due to the noise input through the input terminal IN. To this end, the ripple prevention portion 132g includes a twelfth transistor NT12 and a thirteenth transistor NT13. The twelfth transistor NT12 has a drain connected to the input terminal IN, a gate connected to the second clock terminal CK2, and a source connected to the first node N1. The thirteenth transistor NT13 has a drain connected to the first node N1, a gate connected to the first clock terminal CK1, and a source connected to the second node N1.

The reset section 132h includes a fourteenth transistor NT14 whose drain is connected to the first node N1 and whose gate is connected to the reset terminal RE and whose source is connected to the ground voltage terminal VSS. The fourteenth transistor NT14 discharges the first node N1 to the ground voltage VOFF in response to the output signal of the (n + 1) th stage STAGEn + 1 input through the reset terminal RE. Since the output of the (n + 1) th stage STAGEn + 1 means the end of one frame, the resetting unit 132h outputs the first frame of the odd-numbered stages STAGE1, STAGE3, ..., STAGEn- And discharges the node N1.

That is, the reset unit 132h sequentially outputs the gate driving signals from the odd-numbered stages STAGE1, STAGE3, ..., STAGEn-1 to the odd-numbered stages (STAGEn + 1) The first node N1 of the odd-numbered stages STAGE1, STAGE3, ..., STAGEn + 1 is grounded to the ground voltage VOFF by turning on the fourteenth transistor NT14 of the first, . Therefore, the odd numbered stages STAGE1, STAGE3, ..., STAGEn + 1 of the circuit unit 132 can be restarted in the initialized state.

6A and 6B are simulation graphs for comparing the operation of the gate driving circuit according to the start pulse of the liquid crystal display device according to an embodiment of the present invention and the conventional liquid crystal display device.

First, the operation of the gate driving circuit according to the start pulse of the conventional liquid crystal display will be described with reference to FIG. 6A. 6A, the gate driving circuit of the conventional liquid crystal display device includes a first start pulse STVP1 for driving the first odd stage 1ST ODD stage and a first start pulse STVP1 for driving the first even stage 1ST EVEN STAGE The drive is started by the two-start pulse STVP2.

The second start pulse STVP2 is provided to the input terminal of the first even stage 1ST EVEN STAGE after the first start pulse STVP1 is provided to the input terminal of the first odd stage STST1. More specifically, assuming that the time at which the gate-on voltage (VON) voltage supplied to one gate line maintains the high level state is tON, the second start pulse STVP2 is supplied with the first start pulse STVP1, / 2 < / RTI > This is to compensate for the insufficient filling rate due to the gate line delay by superimposing the gate driving signals provided to adjacent gate lines.

On the other hand, the first and second start pulses STVP1 and STVP2 are applied to the first odd-numbered stage 1ST ODD stage and the gate of the first transistor NT1, which is the pull-up unit 132a of the first even- (1ST ODD STAGE) and the timing of the gate driving signals (G1OUT, G2OUT) output from the first even stage (1ST EVEN STAGE) are used as the preliminary signal (N1sig) This is because the gate drive signals G1OUT and G2OUT output from the first odd stage 1ST ODD stage and the first even stage 1ST stage are supplied to the first gate clock pulse CKV1 and the second gate clock pulse CKV2 Respectively.

Next, the operation of the gate driving circuit according to the start pulse of the liquid crystal display according to the embodiment of the present invention will be described with reference to FIG. 6B. 6B, a gate driving circuit of a liquid crystal display according to an embodiment of the present invention includes a first odd-numbered stage (1ST ODD STAGE) and a first even-numbered stage (1ST EVEN STAGE).

Here, the start pulse STVP may be the same pulse as the conventional first start pulse STVP1. Preferably, the rising time of the start pulse STVP is the same as the rising time of the conventional first start pulse STVP1, and the polling time is before the second gate clock pulse CKV2 is input to the input terminal of the first even- .

More specifically, the start pulse STVP is simultaneously supplied to the input terminal of the first odd-numbered stage (1ST ODD STAGE) and the input terminal of the first even-numbered stage (1ST EVEN STAGE). The first odd-numbered stage (1ST ODD STAGE) charges the first capacitor (C1) with the provided start pulse (STVP) and generates a preliminary signal (N1sig) for turning on the gate of the first transistor And outputs the gate driving signal G1OUT in synchronization with the one-gate clock pulse CKV1. The first even stage 1ST EVEN STAGE charges the provided start pulse STVP into the first capacitor C1 to generate a preliminary signal N2sig that turns on the gate of the first transistor NT1 in advance, And outputs the gate driving signal G2OUT in synchronization with the two-gate clock pulse CKV2.

At this time, the first capacitor C1 of the first even stage (1ST EVEN STAGE) starts charging at the time when the start pulse (STVP) is charged to the first capacitor (C1) of the first odd stage (1ST ODD STAGE) Thereby generating a preliminary signal N2sig which turns on the gate of the transistor NT1. That is, the first capacitor C1 of the first even stage (1ST EVEN STAGE) includes the time of charging the first capacitor of the first odd stage (1ST ODD STAGE) to generate the preliminary signal, and the second gate clock pulse CKV2) is input to the high state. The first even stage (1ST EVEN STAGE) outputs the gate drive signal (G2OUT) when the second gate clock pulse (CKV2) is inputted in a high state.

Therefore, in the liquid crystal display device according to the embodiment of the present invention, the first odd stage (1ST ODD stage) and the first even stage (1ST EVEN stage) can operate by sharing one start pulse (STVP). Thus, conventionally, the integrated space of the wiring for providing the first and second start pulses is reduced to half.

FIG. 7 is a block diagram of the configuration of the other first and second gate driving circuits shown in FIG. 2. FIG. 7, the first and second gate driving circuits 130 and 140 include a wiring portion 134 for receiving various signals from the data driver 120 and transferring the gate driving signals, And a circuit section 132 for outputting the signals sequentially.

The circuit unit 132 includes a plurality of stages STAGE1, ..., STAGEn + 2 that are connected to each other. The plurality of stages STAGE1, ..., STAGEn + 2 are provided with the output signal of the (n + 2) th stage STAGEn + 2 at the reset terminal RE.

The wiring part 134 includes a start pulse wiring SL1, a first gate clock pulse wiring SL2, a first gate clock bar pulse wiring SL3, a second gate clock pulse wiring SL4, A second gate clock bar pulse wiring SL5, a ground voltage wiring SL6, and a reset wiring SL7. The reset wiring SL7 provides the output signal of the output terminal OUT of the (n + 2) th stage STAGEn + 2 to the reset terminal RE of the plurality of stages STAGE1, .., STAGEn + 2.

In other words, the first and second gate driving circuits 130 and 140 according to another embodiment of the present invention include odd-numbered stages STAGE1, STAGE3, ..., STAGEn + 1 and even-numbered stages STAGE2, STAGE4,. .., STAGEn + 2) share a reset signal.

8A and 8B are simulation graphs for comparing the operation of a gate driving circuit of a liquid crystal display device according to another embodiment of the present invention and a conventional liquid crystal display device.

Referring to FIG. 8A, the gate driving circuit of the conventional liquid crystal display device includes odd-numbered stages STAGE1, STAGE3,... By a first reset signal RST1, which is an output signal of the (n + 1) th stage STAGEn + 1. , STAGEn + 1 are reset and the even-numbered stages STAGE2, STAGE4, ..., STAGEn + 2 are reset by the second reset signal RST2, which is the output signal of the (n + 2) do.

Referring to FIG. 8B, the gate driving circuit of the liquid crystal display according to another embodiment of the present invention includes an odd-numbered stage STAGE1 (STAGE1) by one reset signal RST, which is an output signal of the (n + 2) , STAGE3, ..., STAGEn + 1) and the even-numbered stages (STAGE2, STAGE4, ..., STAGEn + 2) are simultaneously reset.

The reset signal RST is a signal for notifying the end of one frame and discharging the first node N1 by turning on the fourteenth transistor T14 of the plurality of stages. Therefore, the odd-numbered stages STAGE1, STAGE3, ..., Stage STAGE1, STAGE3, ..., STAGEn + 1 by providing a reset signal RST to an output terminal of the (n + 2) -th stage at the reset terminal RE of the odd- No problem occurs.

Therefore, the liquid crystal display according to another embodiment of the present invention is characterized in that the odd-numbered stages STAGE1, STAGE3, ..., STAGEn + 1 and the even-numbered stages STAGE2, STAGE4, It becomes possible to operate by sharing a signal. Thus, conventionally, the integrated space of the wirings for providing the first and second reset signals is reduced to ½.

The liquid crystal display of the present invention can reduce the signal wiring connected to the gate driving circuit by sharing the start pulse of the dual gate driving circuit and the output signal of the dummy stage so that the integrated space for the signal wiring can be reduced. Reduction of the integrated space for the signal wiring can reduce the manufacturing cost of the liquid crystal panel because the conventional liquid crystal panel and the equipment used in the liquid crystal panel manufacturing process can be used as it is.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (23)

Includes a plurality of stages coupled in dependence on one another in order to output first and second gate clock pulses or first and second gate clock bar pulses in response to one start pulse to a plurality of gate lines, Wherein the plurality of stages include: a circuit part having output terminals connected to corresponding to a plurality of gate lines; And And a wiring portion in which a start pulse wiring for receiving the start pulse from outside is formed, Wherein the odd-numbered stages of the stages are connected to each other, the odd-numbered stages of the stages are connected to each other, and the start pulse is connected to the first stage of the odd- Lt; th > stage, Numbered stages outputs the first gate clock pulse as the gate driving signal, and even stages of the odd-numbered stages output a first gate clock bar pulse as the gate driving signal, and the even- Numbered stages outputs the second gate clock pulse as the gate driving signal, and even stages of the even-numbered stages output the second gate clock bar pulse as the gate driving signal, Wherein gate drive signals provided to adjacent gate lines overlap each other. delete The method of claim 1, wherein the odd- Each input terminal is connected to an output terminal of the previous stage, Each control terminal is connected to a carry terminal of the next stage, Wherein the even- Each input terminal is connected to an output terminal of the previous stage, Each control terminal being connected to a carry terminal of the next stage. The method of claim 3, The odd-numbered stages include a first dummy stage in which a carry terminal is connected to a control terminal of the last odd-numbered stage, Wherein the even-numbered stages include a second dummy stage in which the carry terminal is connected to the control terminal of the last even-numbered stage. The semiconductor device according to claim 4, wherein the wiring portion A first reset wiring connecting an output terminal of the first dummy stage to a reset terminal of the first dummy stage and a reset terminal of each of the odd-numbered stages; And And a second reset wiring for connecting an output terminal of the second dummy stage to a reset terminal of the second dummy stage and a reset terminal of each of the even-numbered stages. A timing controller for generating an output enable signal, a gate clock, and a start signal in response to an external input signal; A level shifter for generating first and second gate clock pulses and first and second gate clock bar pulses in response to the output enable signal and the gate clock and generating a start pulse in response to the start signal; And And outputting the first and second gate clock pulses or the first and second gate clock bar pulses as a gate driving signal to be provided to a plurality of gate lines in response to the one start pulse, Lt; / RTI > Wherein the first and second gate driving circuits each include a plurality of stages each of which is connected to a corresponding gate line, the odd-numbered stages of the stages being connected to each other, and the even- Wherein the start signal is provided to an input terminal of a first stage of the odd-numbered stages and a first stage of the even-numbered stages, Numbered stages outputs the first gate clock pulse as the gate driving signal, and even stages among the odd-numbered stages output the first gate clock bar pulse as the gate driving signal, and the odd- Numbered stages output the second gate clock pulse as the gate driving signal, and even stages among the even-numbered stages output the second gate clock bar pulse as the gate driving signal, And gate drive signals provided to gate lines adjacent to each other overlap each other. delete delete The method according to claim 6, The odd- Each input terminal is connected to an output terminal of the previous stage, Each control terminal is connected to a carry terminal of the next stage, Wherein the even- Each input terminal is connected to an output terminal of the previous stage, And each control terminal is connected to a carry terminal of the next stage. 10. The method of claim 9, The odd-numbered stages include a first dummy stage in which a carry terminal is connected to a control terminal of the last odd-numbered stage, Wherein the even stages include a second dummy stage in which a carry terminal is connected to a control terminal of a last even stage, The output terminal of the first dummy stage is connected to the reset terminal of the first dummy stage and the reset terminal of each of the odd-numbered stages, And the output terminal of the second dummy stage is connected to the reset terminal of the second dummy stage and the reset terminal of each of the even-numbered stages. The method according to claim 6, Further comprising a power supply for supplying a gate-on voltage and a gate-off voltage to the level shifter, The level shifter outputs the first and second gate clock pulses, the first and second gate clock bar pulses, and the start pulse having the gate-on voltage and the gate-off voltage level. 12. The level shifter according to claim 11, A first level shifter for subjecting the output enable signal and the gate clock to logical operation and amplifying a level of the voltage to output the first and second gate clock pulses; And And a second level shifter for performing logical operations on the output enable signal and the gate clock, inverting the phase, amplifying the level of the voltage, and outputting the amplified signal as the first and second gate clock bar pulses. 7. The semiconductor memory device according to claim 6, wherein the first and second gate driving circuits comprise: Wherein the gate lines are integrated in a liquid crystal panel formed with the gate lines, and the gate lines are driven in dual. A timing controller responsive to an external signal for generating an output enable signal, a gate clock, and a start signal; A level shifter for generating the first and second gate clock pulses, the first and second gate clock bar pulses, and the one start pulse in response to the output enable signal and the gate clock; And A first gate driving circuit for sequentially outputting a gate driving signal to a plurality of data lines, a plurality of gate lines, and the gate lines, wherein the first and second gate driving circuits are connected to the one start pulse And outputting the first and second gate clock pulses or the first and second gate clock bar pulses as the gate driving signal in response to the gate driving signal, Wherein the first and second gate driving circuits each include a plurality of stages each of which is connected to a corresponding gate line, the odd-numbered stages of the stages being connected to each other, and the even- Wherein the start signal is provided to an input terminal of a first stage of the odd-numbered stages and a first stage of the even-numbered stages, Numbered stages outputs the first gate clock pulse as the gate driving signal, and even stages among the odd-numbered stages output the first gate clock bar pulse as the gate driving signal, and the odd- Numbered stages output the second gate clock pulse as the gate driving signal, and even stages among the even-numbered stages output the second gate clock bar pulse as the gate driving signal, And gate drive signals provided to gate lines adjacent to each other overlap each other. delete delete delete 15. The method of claim 14, The odd- Each input terminal is connected to an output terminal of the previous stage, Each control terminal is connected to a carry terminal of the next stage, Wherein the even- Each input terminal is connected to an output terminal of the previous stage, And each control terminal is connected to a carry terminal of the next stage. 19. The method of claim 18, Wherein the odd-numbered stages include a first dummy stage in which a carry terminal is connected to a control terminal of the last odd-numbered stage, Wherein the even stages include a second dummy stage in which a carry terminal is connected to a control terminal of a last even stage, The output terminal of the first dummy stage is connected to the reset terminal of the first dummy stage and the reset terminal of each of the odd-numbered stages, And the output terminal of the second dummy stage is connected to the reset terminal of the second dummy stage and the reset terminal of each of the even-numbered stages. 15. The method of claim 14, Further comprising a power supply for supplying a gate-on voltage and a gate-off voltage to the level shifter, And the level shifter outputs the first and second gate clock pulses, the first and second gate clock bar pulses, and the start signal having the gate-on voltage and the gate-off voltage level. 21. The level shifter according to claim 20, A first level shifter for subjecting the output enable signal and the gate clock to logical operation and amplifying a level of the voltage to output the first and second gate clock pulses; And And a second level shifter for performing a logical operation on the output enable signal and the gate clock, inverting the phase, amplifying the level of the voltage, and outputting the amplified signal as the first and second gate clock bar pulses. 22. The apparatus of claim 21, wherein the first level shifting unit comprises: A logic operation unit for performing an OR operation on the output enable signal and the gate clock, A drive inverter for inverting and amplifying the phase of the output of the logic operation unit, and And a full-swing inverter for generating the first and second gate clock pulses of the gate-on voltage and the gate-off voltage level in response to the output of the drive inverter. 22. The apparatus of claim 21, wherein the second level shifting unit comprises: A logic operation unit for performing an OR operation on the output enable signal and the gate clock, An inverting inverter for inverting and outputting the phase of the output of the logic operation unit, A drive inverter for inverting and amplifying the phase of the output of the inverting inverter, and And a full-swing inverter for generating the first and second gate clock bar pulses of the gate-on voltage and the gate-off voltage level in response to the output of the drive inverter.

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