JP2021012365A - Display device, gate driver circuit, and driving method - Google Patents

Abstract

To provide a display device, gate driver circuit, and driving method, which improve image quality by improving charging rate through overlap driving of the subpixels.SOLUTION: Embodiments of the present disclosure relate to a display device 100, a gate driver circuit 120, and a driving method, and more specifically, to a display device, a gate driver circuit, and a driving method, which allow for totally solving the problems of insufficient charging time or image abnormalities by controlling supply timing of two gate signals, namely a scan signal and sense signal.SELECTED DRAWING: Figure 1

Description

Embodiments of the present invention relate to display devices, gate drive circuits, and drive methods.

As the information society develops, the demand for display devices for displaying images is increasing in various forms, and in recent years, various display devices such as liquid crystal display devices, plasma display devices, and organic light emission display devices have been utilized. Has been done.

Such a display device can charge a capacitor arranged in each of a large number of subpixels arranged on the display panel and utilize the capacitor to drive the display. However, in the case of a conventional display device, there may be a problem that the image quality is deteriorated due to a phenomenon that the charging at each subpixel is insufficient. In addition to these problems, in the case of a conventional display device, the image is not classified and a blurring phenomenon occurs, or a luminance deviation occurs due to a difference in the light emission period for each line position, resulting in deterioration of image quality. Points can also be brought about.

An embodiment of the present invention can provide a display device, a gate drive circuit, and a drive method for improving image quality by improving the charge rate through overlapping drive of subpixels.

Further, in the embodiment of the present invention, the image is divided through the fake data insertion drive for inserting a fake image (eg, black image, low gradation image, etc.) different from the actual image in the middle of displaying the actual image. It is possible to provide a display device, a gate drive circuit, and a drive method for improving image quality by preventing a blurring phenomenon and a phenomenon in which a difference in brightness appears for each sub-pixel line.

Further, in the embodiment of the present invention, even if the fake data insertion drive is advanced during the overlap drive, the overlap drive and the fake data are prevented through the advanced overlap drive so that the overlap drive characteristics do not change due to the fake data insertion drive. Display devices, gate drive circuits, and drive methods can be provided that allow all the advantages of each of the insert drives to be obtained.

Further, in the embodiment of the present invention, even if the fake data insertion drive is advanced during the overlap drive, a display device for preventing an image abnormality phenomenon (eg, a specific line bright phenomenon) immediately before the fake data insertion drive occurs. , A gate drive circuit, and a drive method can be provided.

Further, an embodiment of the present invention provides a display device, a gate drive circuit, and a drive method that can complement the decrease in charging time by increasing the ratio of the channel width to the channel length of the sense transistor together with the advanced overlap drive. Can be provided.

In the embodiment of the present invention, a scan clock signal generator that receives inputs of a first reference scan clock signal and a second reference scan clock signal to generate and output a scan clock signal; a first reference sense clock signal and a second reference. Sense clock signal generator that receives the input of the sense clock signal and generates and outputs the sense clock signal; outputs a scan signal having a turn-on-level voltage section based on the scan clock signal, and turns based on the sense clock signal. It is possible to provide a gate drive circuit including a gate signal output unit that outputs a sense signal having an on-level voltage section.

After the first reference scan clock signal is rising and falling, the second reference scan clock signal can be rising and falling. After the first reference sense clock signal is rising and falling, the second reference sense clock signal can be rising and falling.

The high level gate voltage section of the sense clock signal can be delayed by a preset sense shift time as compared with the high level gate voltage section of the scan clock signal. As a result, the turn-on level voltage section of the sense signal can be delayed by the sense shift time as compared with the turn-on level voltage section of the scan signal.

The scan clock signal generation unit can generate and output a scan clock signal that is raised at the rising timing of the first reference scan clock signal and falls at the falling timing of the second reference scan clock signal.

The sense clock signal generation unit is not raised at the rising timing of the first reference sense clock signal, but is raised at the rising timing of the second reference sense clock signal, and is preset after the falling timing of the second reference sense clock signal. It is possible to generate and output a sense clock signal that falls after the delay time.

The time interval between the rising timing of the first reference sense clock signal and the rising timing of the second reference sense clock signal can correspond to the sense shift time.

The rising timing of the first reference sense clock signal can be the same as the rising timing of the first reference scan clock signal.

The rising timing of the second reference sense clock signal can precede the rising timing of the second reference scan clock signal.

The length of the superposition time between the scan clock signal and the sense clock signal can correspond to the time length of the turn-on level voltage section of the sense signal minus the delay time.

The scan clock signal generation unit receives the input of the first reference scan clock signal and the second reference scan clock signal, rises to the rising timing of the first reference scan clock signal, and sets the falling timing of the second reference scan clock signal. It can include a scan logic unit that produces a falling scan clock signal; and a scan level shifter that outputs a scan clock signal that is raised to a high level gate voltage and dropped to a low level gate voltage.

The sense clock signal generation unit receives the input of the first reference sense clock signal and the second reference sense clock signal, and is not raised at the rising timing of the first reference sense clock signal, but at the rising timing of the second reference sense clock signal. A sense logic unit that generates a sense clock signal that is rising and falls after a preset delay time after the falling timing of the second reference sense clock signal; the sense clock signal is the first reference sense clock signal. A delayer that delays the rising timing of the sense clock signal so that it is not rising at the rising timing but at the rising timing of the second reference sense clock signal; and falling to the high level gate voltage and falling to the low level gate voltage. A sense level shifter that outputs a sense clock signal having a high level gate voltage section delayed by a sense shift time as compared with the high level gate voltage section of the scan clock signal can be included.

The delay device can include one or more resistance elements.

In one aspect, embodiments of the invention include a plurality of data lines, a plurality of scan signal lines, a plurality of sense signal lines, a plurality of reference lines, and a plurality of subpixels, each of the plurality of subpixels being a light emitting element. The drive transistor for driving the light emitting element, the scan transistor for controlling the connection between the data line and the first node of the drive transistor by the scan signal, and the reference line and the second node of the drive transistor by the sense signal. A display panel including a sense transistor for controlling the connection between the transistors, a capacitor connected between the first node and the second node of the drive transistor, a data drive circuit for driving a plurality of data lines, and a plurality of data drive circuits. A first gate drive circuit that supplies a first scan signal having a turn-on level voltage section to a first scan signal line electrically connected to a gate node of a scan transistor in the first subpixel contained in a subpixel. , Turn of the first scan signal on the first sense signal line electrically connected to the gate node of the sense transistor in the first subpixel-a turn delayed by a preset sense shift time compared to the on-level voltage section. A display device can be provided that includes a second gate drive circuit that supplies a first sense signal with an on-level voltage section.

The turn-on level voltage section of the first sense signal can include a period of superimposition with the turn-on level voltage section of the first scan signal and a period of non-superimposition with the turn-on level voltage section of the first scan signal. ..

The period in which the turn-on level voltage section of the first sense signal and the turn-on level voltage section of the first scan signal are superimposed can correspond to the programming period in which the video data is programmed in the first subpixel.

The start time of the turn-on level voltage section of the first sense signal can be delayed by the sense shift time from the start time of the turn-on level voltage section of the first scan signal.

The sense shift time can be a time corresponding to 1/2 of the turn-on level voltage section of the first scan signal.

The plurality of subpixels further include a second subpixel and a third subpixel, and the drain node or source node of the sense transistor contained in each of the first subpixel, the second subpixel, and the third subpixel is the same. Can be electrically connected to the reference line.

A second scan signal having a turn-on level voltage is supplied to the gate node of the scan transistor in the second subpixel, and a second sense signal having a turn-on level voltage is supplied to the gate node of the sense transistor in the second subpixel. During this time, there can be a timing at which the sense transistor in the first subpixel and the sense transistor in the third subpixel are turned off at the same time.

Of the plurality of scan signal lines, the period during which the scan signal having the turn-on level voltage is supplied to the i (i is a natural number of 1 or more) th scan signal line, and among the plurality of scan signal lines, (i + 1). ) Actually for subpixels arranged in k (k is a natural number of 1 or more) subpixel lines during the period during which a scan signal with a turn-on level voltage is supplied to the thirst scan signal line. It is possible to supply a fake data voltage that is distinguished from the video data voltage of.

In yet another embodiment, the embodiment of the invention is a first scan having a turn-on level voltage section in a first scan signal line connected to a gate node of a scan transistor within the first subpixel of a plurality of subpixels. The step of supplying a signal and transmitting the video data voltage supplied to the data line to the first node of the drive transistor in the first subpixel through the scan transistor, and electrically to the gate node of the sense transistor in the first subpixel. A first sense signal having a turn-on level voltage section delayed by a preset sense shift time as compared with the turn-on level voltage section of the first scan signal is supplied to the connected first sense signal line. , The step of transmitting the reference voltage supplied to the reference line to the second node of the drive transistor through the sense transistor, and supplying the first scan signal having the turn-off level voltage section to the first scan signal line, the first sense. A method of driving a display device can be provided that includes a step of supplying a first sense signal having a turn-off level voltage section to the signal line.

The turn-on level voltage section of the first sense signal can include a period of superimposition with the turn-on level voltage section of the first scan signal and a period of non-superimposition with the turn-on level voltage section of the first scan signal. ..

The start time of the turn-on level voltage section of the first sense signal is delayed by the sense shift time from the start time of the turn-on level voltage section of the first scan signal, and the sense shift time is the turn-on of the first scan signal. It can be a time corresponding to 1/2 of the level voltage section.

The plurality of subpixels further include a second subpixel and a third subpixel, and the drain node or source node of the sense transistor contained in each of the first subpixel, the second subpixel, and the third subpixel is the same. Can be electrically connected to the reference line.

A second scan signal having a turn-on level voltage is supplied to the gate node of the scan transistor in the second subpixel, and a second sense signal having a turn-on level voltage is supplied to the gate node of the sense transistor in the second subpixel. During this time, there can be a timing at which the sense transistor in the first subpixel and the sense transistor in the third subpixel are turned off at the same time.

Of the plurality of scan signal lines, the period during which the scan signal having the turn-on level voltage is supplied to the i (i is a natural number of 1 or more) th scan signal line, and among the plurality of scan signal lines, (i + 1). ) Actually for subpixels arranged in k (k is a natural number of 1 or more) subpixel lines during the period during which a scan signal with a turn-on level voltage is supplied to the thirst scan signal line. It is possible to supply a fake data voltage that is distinguished from the video data voltage of.

According to the embodiment of the present invention, the image quality can be improved by improving the charge rate through the overlapping drive of the subpixels.

Further, according to the embodiment of the present invention, the image is displayed through the fake data insertion drive for inserting a fake image (eg, black image, low gradation image, etc.) different from the actual image in the middle of displaying the actual image. It is possible to improve the image quality by preventing the phenomenon of blurring without classification and the phenomenon of difference in brightness for each sub-pixel line.

Further, according to the embodiment of the present invention, even if the fake data insertion drive is advanced during the overlap drive, the turn-on level voltage section of the sense signal among the two gate signals (scan signal and sense signal) is set. Through the advanced overlap drive that controls the scan signal to be delayed from the turn-on level voltage section, it is possible to control the overlap drive characteristics so that they do not change immediately before the fake data insertion drive.

As a result, when the fake data insertion drive proceeds during the overlap drive, it is possible to prevent an image abnormality phenomenon (eg, a specific line obvious phenomenon) that occurs in the subpixel row immediately before the fake data insertion drive.

Further, the embodiment of the present invention can supplement the charging time that can be reduced by the advanced overlap driving by increasing the ratio of the channel width to the channel length of the sense transistor together with the advanced overlap driving.

It is a system block diagram of the display device according to embodiment of this invention.

It is a figure which shows the equivalent circuit of the sub-pixel arranged in the display panel of the display device according to the embodiment of this invention.

It is a system embodiment example figure of the display device according to the Embodiment of this invention.

It is a diagram which shows the fake data insertion drive of the display device according to the embodiment of this invention.

When the display device according to the embodiment of the present invention performs the fake data insertion drive and the overlap drive, it is a drive timing diagram.

When the display device according to the embodiment of the present invention performs the fake data insertion drive and the overlap drive, it is a drive timing diagram.

It is a figure which shows the specific line luminance defect which occurs when the display device which follows the embodiment of this invention performs a fake data insertion drive and overlap drive.

It is a figure for demonstrating the cause of the specific line luminance defect which occurs when the display device which follows the embodiment of this invention performs fake data insertion drive and overlap drive.

It is a figure which shows typically the subpixel and the signal wiring arranged in the display panel of the display device according to the Embodiment of this invention.

It is a drive timing diagram for advanced overlap driving of a display device according to an embodiment of the present invention.

A drive timing diagram when a display device according to an embodiment of the present invention performs a black data insertion drive and an advanced overlap drive.

It is a figure which shows the state of the 3rd subpixel and the adjacent subpixel at the programming timing of the 3rd subpixel.

It is a figure which shows the state of the 4th subpixel and the adjacent subpixel at the programming timing of the 4th subpixel before the black data insertion drive starts.

It is a figure which shows the state of the 5th subpixel and the adjacent subpixel at the programming timing of the 5th subpixel after the black data insertion drive is finished.

It is a figure which shows the black data insertion drive of the display device according to the embodiment of this invention.

It is a figure which shows the precharge drive of the display device according to the embodiment of this invention.

It is a figure which shows the setting range of the precharge data voltage used in the precharge drive of the display device according to the embodiment of this invention.

It is a figure which shows the scan transistor of the display device which follows the embodiment of this invention.

It is a figure which shows the sense transistor of the display device which follows the embodiment of this invention.

It is a flowchart for the driving method of the display device according to embodiment of this invention.

It is a figure for demonstrating the effect which the specific line luminance defect is prevented when the display device which follows the embodiment of this invention performs a fake data insertion drive and advanced overlap drive.

It is a figure which shows the gate drive circuit which follows the embodiment of this invention.

It is a gate drive timing diagram according to the embodiment of this invention.

It is a figure which shows the gate signal output unit according to embodiment of this invention.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to the components of each drawing, the same components may have the same reference numerals as much as possible even if they are displayed on other drawings. Further, in explaining the present invention, if it is determined that a specific description of the related known configuration or function may obscure the gist of the present invention, the detailed description thereof may be omitted. .. When'includes',' possesses','does', etc. mentioned in the present specification are used, other parts can be added as long as'only'is not used. When a component is expressed in the singular, the case where a plurality of components are included may be included unless otherwise specified.

In addition, terms such as first, second, A, B, (a), and (b) can be used in explaining the components of the present invention. Such terms are used to distinguish one component from other components, and the term does not limit the essence, order, order, number, or the like of the component.

When it is stated that two or more components are "connected", "joined" or "connected" in the description of the positional relationship of the components, the two or more components are directly "connected" or "connected". It should be understood that it can be "joined" or "connected", but it can also be "connected", "joined" or "connected" by further "intervening" two or more components and other components. .. Here, the other components may also be included in one or more of the two or more components that are "connected," "joined," or "connected" to each other.

In the explanation of the temporal flow relationship related to the components, the operation method, the manufacturing method, etc., for example, the time such as "after", "following", "next", "before", etc. When a pro-post-relationship or a flow-preceding relationship is explained, it can include non-continuous cases as long as "immediate" or "direct" is not used.

On the other hand, when a numerical value or its corresponding information (example: level, etc.) for a component is mentioned, the numerical value or its corresponding information is various factors (example: process factor, internal) even if there is no separate explicit description. Or it can be interpreted as including an error range that can be generated by (external impact, noise, etc.).

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a system configuration diagram of a display device 100 according to an embodiment of the present invention.

Referring to FIG. 1, the display device 100 according to an embodiment of the present invention can include a display panel 110, a data drive circuit 120, a first gate drive circuit 130, a second gate drive circuit 140, and the like, and includes a controller 150. Further can be included.

The display panel 110 can include a large number of data lines DL, a large number of scan signal lines SCL, a large number of sense signal lines SENL, a large number of reference lines RL, a large number of subpixel SPs, and the like. The display panel 110 can include a display area and a non-display area. A large number of subpixel SPs for displaying an image can be arranged in the display area. Drive circuits 120, 130, 140 can be electrically connected or mounted in the non-display area, and a pad portion can be arranged.

The data drive circuit 120 is a circuit for driving a large number of data line DLs, and can supply a data voltage to a large number of data line DLs.

The first gate drive circuit 130 is a circuit for sequentially supplying scan signals (SCAN) to a large number of scan signal lines SCL, which is a kind of gate line.

The second gate drive circuit 140 is a circuit for sequentially supplying sense signals to a large number of sense signal lines, which is a kind of gate line.

The controller 150 can control the data drive circuit 120, the first gate drive circuit 130, and the second gate drive circuit 140.

The controller 150 and the data drive circuit 120 for data drive by supplying various drive control signals (DCS, GCS) to the data drive circuit 120, the first gate drive circuit 130, and the second gate drive circuit 140. , A first gate drive circuit 130 for gate drive, and a second gate drive circuit 140 are controlled.

The controller 150 starts scanning according to the timing embodied in each frame, converts the input video data input from the outside so as to match the data signal format used in the data drive circuit 120, and converts the converted video data (DATA). Is output, and the data drive is controlled at an appropriate time according to the scan.

Along with the input video data, the controller 150 externally (eg,) various timing signals including a vertical synchronization signal (VSYNC), a horizontal synchronization signal (HSYNC), an input data enable signal (DE: Data Enable), a clock signal (CLK), and the like. : Received from the host system).

The controller 150 converts the input video data input from the outside so as to match the data signal format used in the data drive circuit 120, and outputs the converted video data. In addition, the data drive circuit 120, the first In order to control the gate drive circuit 130 and the second gate drive circuit 140, timing signals such as a vertical sync signal (VSYNC), a horizontal sync signal (HSYNC), an input data enable signal (DE), and a clock signal (CLK) Upon receiving the input, various control signals (DCS, GCS) are generated and output to the data drive circuit 120, the first gate drive circuit 130, and the second gate drive circuit 140.

For example, the controller 150 controls a gate start pulse (GSP: Gate Start Pulse), a gate shift clock (GSC: Gate Shift Clock), and a gate output enable signal (GSC: Gate Shift Clock) in order to control the first and second gate drive circuits 130 and 140. It outputs various gate control signals (GCS: Gate Control Signal) including GOE: Gate Output Enable).

Here, the gate start pulse (GSP) controls the operation start timing of one or more gate driver integrated circuits constituting each of the first and second gate drive circuits 130 and 140. The gate shift clock (GSC) is a clock signal commonly input to one or more gate driver integrated circuits, and controls the shift timing of the scan signal (gate pulse). The gate output enable signal (GOE) specifies timing information for one or more gate driver integrated circuits.

Further, in order to control the data drive circuit 120, the controller 150 includes a source start pulse (SSP: Source Start Pulse), a source sampling clock (SSC: Source Sampling Clock), a source output enable signal (SOE: Source Output Enable), and the like. It outputs various data control signals (DCS: Data Control Signal) including.

Here, the source start pulse (SSP) controls the data sampling start timing of one or more source driver integrated circuits constituting the data drive circuit 120. The source sampling clock (SSC) is a clock signal that controls the data sampling timing in each of the source driver integrated circuits. The source output enable signal (SOE) controls the output timing of the data drive circuit 120.

The controller 150 can be embodied as a component separate from the data drive circuit 120, or can be integrated with the data drive circuit 120 and embodied in an integrated circuit.

The data drive circuit 120 drives a large number of data line DLs by receiving input of video data (DATA) from the controller 150 and supplying a data voltage to a large number of data line DLs. Here, the data drive circuit 120 is also referred to as a source drive circuit.

Such a data drive circuit 120 can be embodied including at least one source driver integrated circuit (SDIC).

Each source driver integrated circuit SDIC can include a shift register (Shift Register), a latch circuit (Latch Circuit), a digital-to-analog converter (DAC), an output buffer (Output Buffer), and the like.

Each source driver integrated circuit SDIC may further include an analog-to-digital converter (ADC), as the case may be.

Each source driver integrated circuit SDIC is connected to the Bonding Pad of the display panel 110 by the Tape Automated Bonding (TAB) method or the Chip On Glass (COG) method, or is connected to the Bonding Pad. It may be arranged directly on the display panel 110, or may be integrated and arranged on the display panel 110 in some cases. Further, each source driver integrated circuit SDIC can be embodied by a chip-on-film (COF) method, and in this case, each source driver integrated circuit SDIC is mounted on a film connected to the display panel 110. It can be electrically connected to the display panel 110 through wiring on the film.

The first gate drive circuit 130 sequentially drives a large number of scan signal lines SCL by sequentially supplying scan signals to a large number of scan signal line SCLs. The first gate drive circuit 130 can output a scan signal having a turn-on level voltage or a scan signal having a turn-off level voltage under the control of the controller 150.

The second gate drive circuit 140 sequentially drives a large number of sense signal lines SENL by sequentially supplying sense signals to a large number of sense signal lines SENL. The second gate drive circuit 140 can output a sense signal having a turn-on level voltage or a sense signal having a turn-off level voltage under the control of the controller 150.

A large number of scan signal lines SCL and a large number of sense signal lines SENL correspond to gate lines. The scan signal and the sense signal correspond to the gate signal applied to the gate node of the transistor.

Each of the first and second gate drive circuits 130 and 140 can be embodied including at least one gate drive circuit integrated circuit (GDIC).

Each gate drive circuit integrated circuit GDIC can include a shift register (Shift Register), a level shifter (Level Shifter), and the like.

Each gate driver integrated circuit GDIC is connected to a bonding pad (Bonding Pad) of the display panel 110 by a tape automated bonding (TAB) method or a chip-on-glass (COG) method, or is a GIP (Gate In Panel) type. It can be embodied and placed directly on the display panel 110, or, in some cases, integrated and placed on the display panel 110. Further, each gate driver integrated circuit GDIC can also be realized by a chip-on-film (COF) method mounted on a film connected to the display panel 110.

When the specific scan signal line SCL is opened by the first gate drive circuit 130, the data drive circuit 120 converts the video data (DATA) received from the controller 150 into an analog data voltage and supplies it to a large number of data lines DL. ..

The data drive circuit 120 may be located only on one side of the display panel 110 (eg, upper or lower side), and in some cases, depending on the drive method, panel design method, etc., both sides of the display panel 110 (eg, upper side). It can also be all located on the lower side).

The first and second gate drive circuits 130 and 140 may be located only on one side (eg, left or right side) of the display panel 110, and in some cases, depending on the drive method, panel design method, etc., the display panel 110 may be located. It can also be located on both sides (eg left and right).

The controller 150 may be a timing controller (Timing Controller) used in ordinary display technology, or may be a control device including a timing controller (Timing Controller) that further performs other control functions, and is a control device different from the timing controller. It can be a circuit in the controller. The controller 150 can be embodied in various circuits and electronic components such as an IC (Integrate Circuit), an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a processor (Processor).

The controller 150 is mounted on a printed circuit board, a flexible printing circuit, or the like, and through the printed circuit board, the flexible printing circuit, or the like, the data drive circuit 120, the first gate drive circuit 130, and the second gate drive circuit 140 Can be electrically connected.

The controller 150 can send and receive signals to and from the data drive circuit 120 through one or more predetermined interfaces. Here, for example, the interface can include an LVDS (Low Voltage D differential Signaling) interface, an EPI interface, an SPI (Serial Peripheral Interface), and the like.

The controller 150 can transmit and receive signals to and from the data drive circuit 120, the first gate drive circuit 130, and the second gate drive circuit 140 by one or more predetermined interfaces. Here, for example, the interface can include an LVDS (Low Voltage D differential Signaling) interface, an EPI interface, an SPI (Serial Peripheral Interface), and the like. The controller 150 can include a storage location such as one or more registers.

The display device 100 according to the embodiment of the present invention can be some form of display including a light emitting element in the subpixel SP. For example, the display device 100 according to the embodiment of the present invention is an OLED display including an organic light emitting diode (OLED) as a light emitting element in the subpixel SP, or a light emitting diode (LED) as a light emitting element in the subpixel SP. : Light Emitting Diode) can be an LED display or the like.

FIG. 2 is a diagram showing an equivalent circuit of a subpixel SP arranged on the display panel 110 of the display device 100 according to the embodiment of the present invention.

With reference to FIG. 2, each of the many subpixel SPs can include a light emitting element (EL), three transistors (DT, SCT, SENT) and one capacitor Cst. Such a subpixel structure is called a 3T (Transistor) 1C (Capacitor) structure.

The three transistors (DT, SCT, SENT) can include a drive transistor DT, a scan transistor SCT, and a sense transistor SENT.

The light emitting element EL can include a first electrode, a second electrode, and the like. In the light emitting element EL, the first electrode may be an anode electrode or a cathode electrode, and the second electrode may be a cathode electrode or an anode electrode. In the light emitting element EL of FIG. 2, the first electrode is an anode electrode corresponding to a pixel electrode existing for each subpixel SP, and the second electrode is a cathode electrode to which a base voltage (EVSS) corresponding to a common voltage is applied. is there.

For example, the light emitting element EL may be an organic light emitting diode (OLED) including a first electrode, a light emitting layer, and a second electrode, or a light emitting diode (LED: Light Emitting Diode) or the like can be embodied.

The drive transistor DT is a transistor for driving the light emitting element EL, and may include a first node N1, a second node N2, a third node N3, and the like.

The first node N1 of the drive transistor DT can be a gate node and can be electrically connected to the source node or drain node of the scan transistor SCT.

The second node N2 of the drive transistor DT can be a source node or a drain node, is electrically connected to the source node or the drain node of the sense transistor SENT, and can be electrically connected to the first electrode of the light emitting element EL.

The third node N3 of the drive transistor DT can be electrically connected to the drive voltage line DVL that supplies the drive voltage (E VDD).

The scan transistor SCT is turned on or turned off according to the scan signal (SCAN) supplied from the scan signal line SCL to control the connection between the data line DL and the first node N1 of the drive transistor DT. Can be done.

The scan transistor SCT can be turned-on by a scan signal (SCAN) having a turn-on level voltage and transmit the data voltage (Vdata) supplied to the data line DL to the first node N1 of the drive transistor DT. it can.

The sense transistor SENT is turned on or turned off according to the sense signal (SENSE) supplied from the sense signal line SENL to control the connection between the reference line RL and the second node N2 of the drive transistor DT. Can be done.

The sense transistor SENT is turned-on by a sense signal (SENSE) having a turn-on level voltage, and can transmit the reference voltage (Vref) supplied from the reference line RL to the second node N2 of the drive transistor DT. it can.

Further, the sense transistor SENT can be turned on by a sense signal (SENSE) having a turn-on level voltage, and can transmit the voltage of the second node N2 of the drive transistor DT to the reference line RL.

The function of the sense transistor SENT to transmit the voltage of the second node N2 of the drive transistor DT to the reference line RL can be used at the time of driving for sensing the characteristic value (for example, threshold voltage or mobility) of the drive transistor DT. In this case, the voltage transmitted to the reference line RL can be a voltage for calculating the characteristic value of the drive transistor DT.

The function of the sense transistor SENT to transmit the voltage of the second node N2 of the drive transistor DT to the reference line RL can also be used during driving to sense the characteristic value (for example, threshold voltage) of the light emitting element EL. .. In this case, the voltage transmitted to the reference line RL can be a voltage for calculating the characteristic value of the light emitting element EL.

Each of the drive transistor DT, the scan transistor SCT, and the sense transistor SENT can be an n-type transistor or a p-type transistor. In the following, for convenience of explanation, each of the drive transistor DT, the scan transistor SCT, and the sense transistor SENT will be given as an example of n type.

The capacitor Cst can be connected between the first node N1 and the second node N2 of the drive transistor DT. The capacitor Cst is charged with an amount of electric charge corresponding to the voltage difference between both ends, and serves to maintain the voltage difference between both ends for a fixed frame time. As a result, the corresponding subpixel SP can emit light for a fixed frame time.

The capacitor Cst is not a parasitic capacitor (eg, Cgs, Cgd) that is an internal capacitor (internal Capacitor) existing between the gate node and the source node (or drain node) of the drive transistor DT, but outside the drive transistor DT. It can be an intentionally designed External Capacitor.

FIG. 3 is a system embodiment example diagram of the display device 100 according to the embodiment of the present invention.

Referring to FIG. 3, each gate driver integrated circuit GDIC can be mounted on a film (GF) connected to a display panel 110 when embodied by a chip-on-film (COF) scheme.

Each source driver integrated circuit SDIC can be mounted on a film SF connected to the display panel 110 when embodied by the chip-on-film (COF) method.

The display device 100 includes at least one source printed circuit board (SPCB), control components, and various types for circuit connection between a large number of source driver integrated circuits SDIC and other devices. A Control Printed Circuit Board (CPCB) for mounting an electric device can be included.

A film SF on which a source driver integrated circuit SDIC is mounted can be connected to at least one source printing circuit board SPCB. That is, one side of the film SF on which the source driver integrated circuit SDIC is mounted can be electrically connected to the display panel 110, and the other side can be electrically connected to the source printing circuit board SPCB.

The control printing circuit board CPCB supplies various voltages or currents to the controller 150 that controls the operation of the data drive circuit 120 and the gate drive circuit 130, the display panel 110, the data drive circuit 120, the gate drive circuit 130, and the like. A power management integrated circuit (PMIC) 410 or the like that controls various voltages or currents to be supplied or supplied can be implemented.

The at least one source printed circuit board SPCB and the control printed circuit board CPCB can be circuit-connected through at least one connecting member. Here, the connecting member may be, for example, a flexible printed circuit (FPC), a flexible flat cable (FFC), or the like.

At least one source printed circuit board SPCB and a control printed circuit board CPCB can be integrated and embodied in one printed circuit board.

The display device 100 can further include a set board 330 that is electrically connected to the control printing circuit board CPCB. Such a set board 330 can also be called a power board.

In such a set board 330, a main power management circuit 320 (310: Main Power Management Circuit) that manages the overall power of the display device 100 can exist.

The power management integrated circuit 310 is a circuit that manages the power for the display module including the display panel 110 and its drive circuits 120, 130, 140, etc., and the main power management circuit 320 manages the overall power including the display module. It is a circuit and can be linked with the power management integrated circuit 310.

FIG. 4 is a diagram showing a Fake Data Insertion (FDI) drive of the display device 100 according to the embodiment of the present invention. 5 and 6 are drive timing diagrams when the display device 100 according to the embodiment of the present invention performs the fake data insertion drive and the overlap drive.

A large number of subpixel SPs arranged on the display panel 110 can be arranged in a matrix form. That is, the display panel 110 has a large number of subpixel rows (..., R (n + 1), R (n + 2), R (n + 3), R (n + 4), R (n + 5), ...). The display panel 110 has a large number of subpixel sequences.

A large number of subpixel rows (..., R (n + 1), R (n + 2), R (n + 3), R (n + 4), R (n + 5), ...) can be scanned in sequence.

When each subpixel SP has a 3T1C structure, a large number of subpixel rows (..., R (n + 1), R (n + 2), R (n + 3), R (n + 4), R (n + 5), ...) A scan signal line SCL for transmitting a scan signal (SCAN) and a sense signal line SENL for transmitting a sense signal (SENSE) can be arranged in each of the above.

A large number of sub-pixel columns can be present in the display panel 110, and one data line DL can be arranged correspondingly to each of the large number of sub-pixel columns. In some cases, one data line DL may be arranged for every two or three or more subpixel columns.

Like the subpixel drive operation described above, a large number of subpixel rows (..., R (n + 1), R (n + 2), R (n + 3), R (n + 4), R (n + 5), ...) Of these, when the (n + 1) th subpixel row (R (n + 1)) is driven, the scan signal (SCAN) and the scan signal (SCAN) and the subpixel SP arranged in the (n + 1) th subpixel row (R (n + 1)) A sense signal (SENSE) is applied, and a video data voltage (Vdata) is supplied to the subpixel SPs arranged in the (n + 1) th subpixel row (R (n + 1)) through a large number of data lines DL.

Next, the (n + 2) th subpixel row (R (n + 2)) located below the (n + 1) th subpixel row (R (n + 1)) is driven. A scan signal (SCAN) and a sense signal (SENSE) are applied to the subpixel SPs arranged in the (n + 2) th subpixel row (R (n + 2)), and the (n + 2) th subpixel is applied through a large number of data line DLs. The video data voltage (Vdata) is supplied to the sub-pixel SPs arranged in the row (R (n + 2)).

By such a method, a large number of subpixel rows (..., R (n + 1), R (n + 2), R (n + 3), R (n + 4), R (n + 5), ...) are sequentially recorded as video data. Is done. Here, the video data recording is a procedure performed at the video data recording stage of the sub-pixel drive operation described above.

A large number of subpixel rows (..., R (n + 1), R (n + 2), R (n + 3), R (n + 4), R (n + 5), ...) are the subs described above for one frame time. By the pixel drive operation, the video data recording step, the boosting step, and the light emitting step can proceed in sequence.

On the other hand, as illustrated in FIG. 4, a large number of subpixel rows (..., R (n + 1), R (n + 2), R (n + 3), R (n + 4), R (n + 5), ...) Each does not last to the end of the emission period (EP) following the emission step of the subpixel drive operation within one frame time. Here, the light emission period (EP) can also be referred to as a real video period.

Each of the many subpixel rows (..., R (n + 1), R (n + 2), R (n + 3), R (n + 4), R (n + 5), ...) is one in one frame time. Real Display Driving can proceed during the part time, and Fake Display Driving can proceed during the remaining time.

During one frame time, one subpixel SP has a light emission period (EP) corresponding to a part of one frame time through a real display drive (video data recording step, boosting step, and light emission step). It emits light for a while, and then does not emit light for the remaining period excluding the emission period (EP) in one frame time through the fake display drive. The period during which the subpixel SP does not emit light in one frame time is called the non-emission period (NEP).

Fake Display Driving is a false drive that is different from the real display drive for displaying an actual image (Real Image). Such a fake display drive can be performed by a method of inserting a fake image between the actual images. Therefore, the fake display drive is also referred to as a fake data insertion (FDI) drive. In the following, the fake display drive will be referred to as a fake data insertion drive.

When the real display is driven, the video data voltage (Vdata) corresponding to the actual video is supplied to the subpixel SP in order to display the actual video. Unlike this, when the fake data insertion drive is performed, the fake data voltage (Vfake) corresponding to the fake image having nothing to do with the actual image is supplied to one or more subpixel SPs.

That is, the video data voltage (Vdata) supplied to the subpixel SP when driving a general real display can be changed by a frame or by video, but is supplied to one or more subpixel SPs when driving fake data insertion. The fake data voltage (Vfake) is not variable by the frame or by the image and can be constant.

As one method of the fake data insertion drive described above, one subpixel row can proceed with the fake data insertion drive, and the next one subpixel row can proceed with the fake data insertion drive.

Alternatively, as another method of the fake data insertion drive described above, the fake data insertion drive can proceed simultaneously for a plurality of subpixel rows, and the fake data insertion drive can proceed for the next plurality of subpixel rows. That is, the fake data insertion drive can be performed simultaneously in units of a plurality of subpixel rows. For example, the number of subpixel rows (k) that are driven to insert fake data at the same time can be 2, 4, or 8 or the like.

With reference to FIGS. 4 to 6, the actual video data recording (subpixel row R (n + 1), subpixel row R (n + 2), subpixel row R (n + 3), and subpixel row R (n + 4) in sequence (subpixel row R (n + 4)) Fake Data Write (Fake Data Write) is performed on k subpixel rows that are placed before the subpixel row R (n + 1) and have already passed the light emission period (EP) for a certain period of time after the Real Image Data Write) is advanced. ) Can proceed at the same time.

Next, the subpixel row R (n + 5), the subpixel row R (n + 6), the subpixel row R (n + 7), and the subpixel row R (n + 8) are sequentially subjected to the actual video data recording, and then the sub. Fake data writing proceeds simultaneously in k subpixel rows that are arranged before the pixel row R (n + 1) or the subpixel row R (n + 5) and have already passed the light emission period (EP) for a certain period of time. it can.

The number of subpixel rows (k) that are driven to insert fake data at the same time may be the same or different. As an example, the fake data insertion drive can proceed simultaneously in the first two subpixel rows, and then the fake data insertion drive can proceed simultaneously in units of four subpixel rows. In another example, the fake data insertion drive can be carried out simultaneously in the first four subpixel rows, and then the fake data insertion drive can be carried out simultaneously in units of eight subpixel rows.

By displaying the actual video data (Real Image Data) and fake data (Fake Data) in the same frame through the fake data insertion drive described above, the video is not divided and the motion blur phenomenon that blurs is prevented. The image quality can be improved.

At the time of driving the fake data insertion described above, real image data recording (Real Image Data Write) and fake data recording (Fake Data Write) can be performed through the data line DL.

Further, as described above, by simultaneously proceeding the fake data recording to a plurality of subpixel rows, it is possible to compensate for the luminance deviation due to the difference in the light emission period (EP) according to the position of the subpixel rows, and the video data recording time. Can be secured.

On the other hand, the length of the light emission period (EP) can be adaptively adjusted according to the image by adjusting the timing of the fake data insertion drive.

The video data recording timing and the fake data recording timing can be changed through gate drive control.

For example, the fake data voltage (Vfake) can be a black data voltage (Vblk) or a low gradation data voltage.

When the fake data voltage (Vfake) is the black data voltage (Vblk), the fake data insertion drive can also be referred to as a black data insertion (BDI) drive. When the fake data insertion is driven, the fake data recording can be called black data recording.

The period during which k sub-pixel rows do not emit light due to the fake data insertion drive is called the non-emission period (NEP), and can also be called the black image period.

On the other hand, the gate drive for each of a large number of subpixel rows (..., R (n + 1), R (n + 2), R (n + 3), R (n + 4), R (n + 5), ...) is performed sequentially. , And can proceed so as to overlap for a certain period of time.

With reference to FIG. 6, when the overlap drive is performed, a large number of subpixel rows (..., R (n + 1), R (n + 2), R (n + 3), R (n + 4), R (n + 5), ...) The scan transistor SCT and the sense transistor SENT included in each of the above can be turned on and turned off at the same time. That is, when the overlap is driven, it is included in each of a large number of subpixel rows (..., R (n + 1), R (n + 2), R (n + 3), R (n + 4), R (n + 5), ...). The scan signal (SCAN) and sense signal (SENSE) applied to each of the scan transistor SCT and the sense transistor SENT can be the same gate signal having a turn-on level voltage section at the same timing.

According to the illustrations of FIGS. 5 and 6, a large number of subpixel rows (..., R (n + 1), R (n + 2), R (n + 3), R (n + 4), R (n + 5), ...) The length of the turn-on level voltage section of the gate signal (SCAN, SENSE) supplied to each of the above can be, for example, 2H.

According to the illustrations of FIGS. 5 and 6, a large number of subpixel rows (..., R (n + 1), R (n + 2), R (n + 3), R (n + 4), R (n + 5), ...) The turn-on level voltage sections of the two gate signals (SCAN, SENSE) supplied to each of the two can overlap each other.

Gate signals (SCAN, SCAN,) supplied to each of a large number of subpixel rows (..., R (n + 1), R (n + 2), R (n + 3), R (n + 4), R (n + 5), ...) The length of the turn-on level voltage section of SENSE) can all be 2H.

The turn-on level voltage section (2H) of the scan signal (SCAN) and sense signal (SENSE) applied to the scan transistor SCT and sense transistor SENT of the subpixel SP arranged in the subpixel row R (n + 1) is Turn-on level voltage section (2H) and 1H of the scan signal (SCAN) and sense signal (SENSE) applied to the scan transistor SCT and sense transistor SENT of the subpixel SP arranged in the subpixel row R (n + 2), respectively. Can only overlap.

The turn-on level voltage section (2H) of the scan signal (SCAN) and sense signal (SENSE) applied to the scan transistor SCT and sense transistor SENT of the subpixel SP arranged in the subpixel row R (n + 2) is Turn-on level voltage section (2H) and 1H of the scan signal (SCAN) and sense signal (SENSE) applied to the scan transistor SCT and sense transistor SENT of the subpixel SP arranged in the subpixel row R (n + 3), respectively. Can only overlap.

The turn-on level voltage section (2H) of the scan signal (SCAN) and sense signal (SENSE) applied to the scan transistor SCT and sense transistor SENT of the subpixel SP arranged in the subpixel row R (n + 3) is Turn-on level voltage section (2H) and 1H of the scan signal (SCAN) and sense signal (SENSE) applied to the scan transistor SCT and sense transistor SENT of the subpixel SP arranged in the subpixel row R (n + 4), respectively. Can only overlap.

According to the illustrations of FIGS. 5 and 6, the length of the turn-on level voltage section of the two gate signals (SCAN, SENSE) in each subpixel row is 2H, and in two adjacent subpixel rows. The turn-on level voltage sections of the two gate signals (SCAN, SENSE) can overlap each other by 1H.

Such a gate drive system is called overlap drive, and as shown in FIGS. 5 and 6, the length of the turn-on level voltage section of the two gate signals (SCAN, SENSE) in each subpixel row is 2H. In this case, it is called 2H overlap drive.

The overlap drive can be variously modified other than the 2H overlap drive.

In another example of overlapping drive, the length of the turn-on level voltage section of the two gate signals (SCAN, SENSE) in each subpixel row is 3H, and the two in two adjacent subpixel rows. The turn-on level voltage sections of the gate signals (SCAN, SENSE) can overlap by 2H.

In yet another example of overlapping drive, the length of the turn-on level voltage section of the two gate signals (SCAN, SENSE) in each subpixel row is 3H and 2 in two adjacent subpixel rows. The turn-on level voltage sections of one gate signal (SCAN, SENSE) can overlap by 1H.

In yet another example of overlapping drive, the length of the turn-on level voltage section of the two gate signals (SCAN, SENSE) in each subpixel row is 4H and 2 in two adjacent subpixel rows. The turn-on level voltage sections of one gate signal (SCAN, SENSE) can overlap by 3H.

As described above, various overlap drives are possible, but in the following, for convenience of explanation, 2H overlap drive will be described as an example.

At the time of 2H overlap drive described above, there are two sub-pixel rows (..., R (n + 1), R (n + 2), R (n + 3), R (n + 4), R (n + 5), ...). The front part (1H length) of the turn-on level voltage section (2H length) of the gate signal (SCAN, SENSE) is the data voltage to the corresponding subpixel (which acts as the precharge data voltage). Is a gate signal part for driving a pre-charge (PC: Pre-Charge) to which is applied. The rear part (1H length) of the turn-on level voltage section of the two gate signals (SCAN, SENSE) in each subpixel row is the image in which the actual image data voltage (Vdata) is applied to the corresponding subpixel. It is a gate signal part for data recording.

Through the overlap drive described above, the charge rate at each subpixel can be improved, and the image quality can be improved through this.

When both the fake data insertion drive and the overlap drive described above are performed, the turn-on level voltage section of the two gate signals (SCAN, SENSE) at the subpixel row R (n + 3) is the subpixel row R (n + 4). Overlaps the turn-on level voltage section of the two gate signals (SCAN, SENSE) at.

In this case, of the turn-on level voltage sections of the two gate signals (SCAN, SENSE) at the subpixel row R (n + 3), the rear 1H period is 2 at the next subpixel row R (n + 4). It is a period that overlaps with the turn-on level voltage section of one gate signal (SCAN, SENSE), and is a period in which video data is recorded in the subpixel row R (n + 3). Of the turn-on level voltage sections of the two gate signals (SCAN, SENSE) at the subpixel row R (n + 4), the first 1H period is the precharge drive period. The subpixel row R (n + 3) and the subpixel row R (n + 4) are subpixel rows in which video data is recorded before the fake data insertion drive is advanced.

Also, the turn-on-level voltage section of the two gate signals (SCAN, SENSE) at the subpixel row R (n + 5) is the turn of the two gate signals (SCAN, SENSE) at the subpixel row R (n + 6). Overlaps with the on-level voltage section.

Here, of the turn-on level voltage sections of the two gate signals (SCAN, SENSE) at the subpixel row R (n + 5), the rear 1H period is 2 at the next subpixel row R (n + 6). It is a period that overlaps with the turn-on level voltage section of one gate signal (SCAN, SENSE), and is a period in which video data is recorded in the subpixel row R (n + 5). Of the turn-on level voltage sections of the two gate signals (SCAN, SENSE) in the subpixel row R (n + 6), the first 1H period is the precharge drive period. The subpixel row R (n + 5) and the subpixel row R (n + 6) are subpixel rows in which video data is recorded before the fake data insertion drive proceeds.

However, just before the execution of the fake data insertion drive, the turn-on level voltage section of the two gate signals (SCAN, SENSE) at the subpixel row R (n + 4) is at the subpixel row R (n + 5) that follows. It does not overlap the turn-on level voltage section of the two gate signals (SCAN, SENSE).

Of the turn-on level voltage sections of the two gate signals (SCAN, SENSE) at the subpixel row R (n + 4), the latter 1H period is the period during which video data is recorded at the subpixel row R (n + 4). is there.

Of the turn-on level voltage sections of the two gate signals (SCAN, SENSE) at the subpixel row R (n + 4), the precharge drive is performed at the next subpixel row R (n + 5) during the latter 1H period. Not done.

Based on the fake data insertion period, the subpixel row R (n + 4) is the subpixel row in which the video data is recorded immediately before the fake data insertion drive, and the subpixel row R (n + 5) is immediately after the fake data insertion drive. This is a sub-pixel line where video data is recorded.

Turn-on of two gate signals (SCAN, SENSE) at subpixel row R (n + 4) Turn-on of two gate signals (SCAN, SENSE) at the next subpixel row R (n + 5) The level voltage sections are separated from each other by the period during which the fake data insertion drive is advanced.

In FIGS. 5 and 6, the Vg graph shows both the voltage of the first node N1 of the subpixel drive transistor DT included in the subpixel row, and before entering the boosting step in the subpixel drive operation procedure. Shows the change in the voltage state of.

With reference to FIGS. 5 and 6, the Vs graph also shows the voltage of the second node N2 of the subpixel drive transistor DT contained in the subpixel row, and is a boosting step in the subpixel drive operation procedure. Shows the change in voltage state before approaching.

With reference to the Vg graphs of FIGS. 5 and 6, the Vg voltage of the first node N1 of the subpixel drive transistor DT included in each subpixel row is the Vg voltage of the subpixel drive transistor DT contained in each subpixel row for the remaining period excluding the period in which the fake data insertion proceeds. Is the video data voltage (Vdata) that follows the progress of video data recording.

However, during the period in which the fake data insertion proceeds, the Vg voltage of the first node N1 of the subpixel drive transistor DT included in the subpixel row in which the fake data insertion drive proceeds is the fake data voltage (Vfake). Will have.

On the other hand, as described above, the period of the rear part of the turn-on level voltage section of the two gate signals (SCAN, SENSE) at each of the subpixel rows R (n + 1), R (n + 2), and R (n + 3). Overlaps the period of the preceding part of the turn-on level voltage section of the two gate signals (SCAN, SENSE) in the next subpixel row. However, the latter part of the turn-on-level voltage interval of the two gate signals (SCAN, SENSE) at the subpixel row R (n + 4) is the two gate signals (SCAN, SENSE) at the next subpixel row R (n + 5). It does not overlap with the period of the preceding part of the turn-on level voltage section of SENSE).

Thus, the subpixel row R (n + 1) during the turn-on-level voltage interval of the two gate signals (SCAN, SENSE) at each of the subpixel rows R (n + 1), R (n + 2), and R (n + 3). , R (n + 2), and R (n + 3), the voltage Vs of the second node N2 of the subpixel drive transistor DT contained in each of the video data recording step is a voltage (Vref + Δ) similar to the reference voltage (Vref). Will have V). At this time, the potential difference Vgs between the first node N1 and the second node N2 of each drive transistor DT is Vdata − (Vref + ΔV).

The 1H period immediately before the fake data insertion period, that is, the period after the turn-on level voltage section of the two gate signals (SCAN, SENSE) at the subpixel row R (n + 4) (next subpixel row R (next subpixel row R). The subpixel drive transistor (n + 4) contained in the subpixel row R (n + 4) during the period of the preceding part of the turn-on level voltage section of the two gate signals (SCAN, SENSE) at n + 5). The Vs voltage of the second node N2 of Dt) can be a voltage (Vref + Δ (V / 2)) lower than Vref + ΔV.

As a result, the potential difference Vgs (Vgs (4)) between the first node N1 and the second node N2 of each drive transistor DT is Vdata- (Vref + Δ (V / 2)), and the potential difference (Vdata-) in the previous period. (Vref + ΔV)) will increase more.

FIG. 7 is a diagram showing a specific line luminance defect that occurs when the display device 100 according to the embodiment of the present invention performs the fake data insertion drive and the overlap drive.

As described above, when both the overlap drive and the fake data insertion drive are performed, the drive is performed on a subpixel row (eg, R (n + 4), R (n + 8), etc.) that cannot be overlapped immediately before the fake data insertion drive. The potential difference (Vgs) between the first node N1 and the second node N2 of the transistor DT suddenly increases.

Therefore, as illustrated in FIG. 7, the sub-pixel row (eg, R (n + 4), R (n + 8), etc.) in which the video data recording proceeds immediately before the fake data insertion drive is in the form of an abnormal bright line 700. You will be able to see it.

According to the above-described embodiment of the present invention, the motion blur phenomenon can be prevented through the fake data insertion drive, and the charge rate at each subpixel can be improved through the overlap drive. If the overlap drive is performed together with the above, a phenomenon in which a specific line brightness defect occurs as an unexpected side effect (Side Effect) can be observed.

As a result of analyzing the root cause of such a specific line luminance defect, it has been confirmed that there are the following causes. The root cause of the specific line luminance defect will be described with reference to FIG.

FIG. 8 is a diagram for explaining a cause of a specific line luminance defect that occurs when the display device 100 according to the embodiment of the present invention performs both the fake data insertion drive and the overlap drive.

FIG. 8 shows a first subpixel Spa arranged in the subpixel row R (n + 3) of FIGS. 5 and 6, a second subpixel SPb arranged in the subpixel row R (n + 4), and a subpixel row R ( It is a figure which shows the driving operation with respect to the 3rd subpixel SPc arranged in n + 4).

Referring to FIG. 8, the first subpixel SPa arranged in the subpixel row R (n + 3), the second subpixel SPb arranged in the subpixel row R (n + 4), and the subpixel row R (n + 5). The resulting third subpixel SPc is arranged in the same column and is electrically connected to the same data line DL and the same reference line RL.

That is, the drain node or source node of the scan transistor SCT arranged in each of the first subpixel SPa, the second subpixel SPb, and the third subpixel SPc can be electrically connected to the data line DL in common. The drain node or source node of the sense transistor SENT arranged in each of the first subpixel SPa, the second subpixel SPb, and the third subpixel SPc can be electrically connected to the reference line RL in common.

With reference to FIGS. 5, 6 and 8, when video data is recorded for the first subpixel Spa arranged in the subpixel row R (n + 3), the scan transistor SCT included in the first subpixel SPA is turned-. Turned on by the on-level voltage scan signal (SCAN). As a result, the video data voltage (Vdata) supplied to the data line DL is transmitted to the first node N1 corresponding to the gate node of the drive transistor DT via the turn-on scan transistor SCT.

At this time, the sense transistor SENT included in the first subpixel SPA is turned-on together with the scan transistor SCT by the sense signal (SENSE) of the turn-on level voltage, and the reference voltage (Vref) supplied to the reference line RL. ) Is transmitted to the second node N2 corresponding to the source node of the drive transistor DT via the turn-on sense transistor SENT.

When the video data recording for the first subpixel SPA arranged in the subpixel row R (n + 3) is advanced by the 2H overlap drive, the second subpixel SPb arranged in the next subpixel row R (n + 4) is advanced. Can proceed with precharge drive.

That is, when recording video data for the first subpixel SPa arranged in the subpixel row R (n + 3), a turn-on level scan is performed on the second subpixel SPb arranged in the next subpixel row R (n + 4). The first, which is the gate node of the drive transistor DT of the second subpixel SPb, passes through the scan transistor SCT in which the signal (SCAN) is applied and the video data voltage (Vdata) supplied to the data line DL is turned on. A video data voltage (Vdata) is applied to the node N1 as a precharge voltage.

At this time, the sense transistor SENT included in the second subpixel SPb arranged in the subpixel row R (n + 4) is turned-on together with the scan transistor SCT by the sense signal (SENSE) of the turn-on level voltage. , The reference voltage (Vref) supplied to the reference line RL is transmitted to the second node N2 corresponding to the source node of the drive transistor DT via the turn-on sense transistor SENT.

When recording video data for the first subpixel Spa arranged in the subpixel row R (n + 3), the current (id) supplied from the first subpixel SPA and the current (id) supplied from the second subpixel SPb are The combined current (2 id) flows through the reference line RL.

As a result, the line capacitor existing in the reference line RL is charged by the current (2 id) flowing through the reference line RL, and the voltage of the reference line RL can be increased. The increased voltage of the reference line RL is transferred to the second node N2 of the drive transistor DT in the first subpixel Spa through the turn-on sense transistor SENT in the first subpixel Spa located in the subpixel row R (n + 3). At the same time, it can be transmitted to the second node N2 of the drive transistor DT in the second subpixel SPb through the sense transistor SENT turned on in the second subpixel SPb arranged in the subpixel row R (n + 4).

Therefore, the voltage (Vs voltage) of the second node N2 of the drive transistor DT in the first subpixel SPA arranged in the subpixel row R (n + 3) where the video data recording is advanced increases.

On the other hand, after the video data recording for the first subpixel SPa arranged in the subpixel row R (n + 3) has progressed, the video data recording for the second subpixel SPb arranged in the subpixel row R (n + 4) has progressed. it can.

When video data recording for the second subpixel SPb arranged in the subpixel row R (n + 4) proceeds, the scan transistor SCT included in the second subpixel SPb arranged in the subpixel row R (n + 4) Turn-on Turned on by the scan signal (SCAN) of the level voltage. As a result, the video data voltage (Vdata) supplied to the data line DL is transmitted to the first node N1 corresponding to the gate node of the drive transistor DT via the turn-on scan transistor SCT.

At this time, the sense transistor SENT included in the second subpixel SPb arranged in the subpixel row R (n + 4) is turned-on together with the scan transistor SCT by the sense signal (SENSE) of the turn-on level voltage. , The reference voltage (Vref) supplied to the reference line RL is transmitted to the second node N2 corresponding to the source node of the drive transistor DT via the turn-on sense transistor SENT.

Since the period during which the video data recording for the second subpixel SPb arranged in the subpixel row R (n + 4) proceeds is immediately before the fake data insertion drive proceeds, it is arranged in the subpixel row R (n + 4). During the period in which the video data recording for the second subpixel SPb is advanced, the precharge drive for the third subpixel SPc arranged in the next subpixel row R (n + 5) is not advanced.

Therefore, when video data is recorded for the second subpixel SPb arranged in the subpixel row R (n + 4), only the current (id) supplied from the second subpixel SPb flows in the reference line RL.

As a result, the second node N2 of the drive transistor DT in the second subpixel SPb arranged in the subpixel row R (n + 4) where the video data recording proceeds without the overlap drive immediately before the fake data insertion drive proceeds. The voltage (Vs voltage) of is increased. However, the degree of voltage rise of the second node N2 of the second subpixel SPb drive transistor DT of the subpixel row R (n + 4) having no overlap drive immediately before the fake data insertion drive is due to the decrease in the current flowing through the reference line RL. Compared to the voltage rise of the second node N2 of the drive transistor DT in the first subpixel SPA arranged in the subpixel row R (n + 3) where the overlap drive normally proceeds due to the decrease of the voltage rise of the reference line RL. small.

Therefore, the second subpixel arranged in the subpixel row R (n + 4) immediately before the fake data voltage (Vfake) is applied to the data line DL by the fake data insertion drive (that is, immediately before the fake data insertion drive). The potential difference (Vgs) between the first node N1 and the second node N2 of the drive transistor DT in the SPb increases.

Such an increase in potential difference (Vgs) is caused by a line 700 with bright subpixel rows (eg, R (n + 4), R (n + 12), R (n + 20), etc.) in which video data recording proceeds immediately before the fake data insertion drive. Can be displayed with. An advanced Overlap Driving method for preventing such a phenomenon will be described in detail below.

In the following, an example in which the subpixel SP and the signal wiring (SCL, SENL, DL, RL) of the display panel 110 for explaining the advanced overlap driving method are arranged will be described first.

FIG. 9 shows subpixels (SPrc, r = 1 to 6, c = 1 to 4) and signal wirings (SCLR, SENLr, DLc, RL) arranged on the display panel 110 of the display device 100 according to the embodiment of the present invention. It is a figure which shows r = 1-6, c = 1-4) exemplarily.

Referring to FIG. 9, 24 subpixels (SPrc, r = 1 to 6, c = 1 to 4) can be arranged in 6 rows and 4 columns on the display panel 110. That is, the display panel 110 has 24 subpixels (SPrc, r = 1 to 6, c = 1 to 4) and 6 subpixel rows (R (n + 1), R (n + 2), ..., R. (N + 6)).

Referring to FIG. 9, there are 6 scan signal lines (SCLR, r = 1-6) in 6 subpixel rows (R (n + 1), R (n + 2), ..., R (n + 6)). Each can be arranged correspondingly. Six sense signal lines (SENLr, r = 1 to 6) can be arranged correspondingly to each of the six subpixel rows (R (n + 1), R (n + 2), ..., R (n + 6)). ..

Six scan signal lines (SCLr, r = 1-6) translate scan signals (SCANr, r = 1-6) into six subpixel lines (R (n + 1), R (n + 2), ..., R. (N + 6)). The six sense signal lines (SENLr, r = 1-6) have the sense signal (SENSEr, r = 1-6) in six subpixel lines (R (n + 1), R (n + 2), ..., R. (N + 6)).

According to the overlap drive described above with reference to FIGS. 5 and 6, the two gate signals (SCAN, SENSE) supplied to the same subpixel row have turn-on level voltage sections at the same timing.

For example, in the first subpixel row (R (n + 1)), the first scan signal (SCAN1) supplied to the first scan signal line SCL1 and the first sense signal (SENSE1) supplied to the first sense signal line SENL1. Have turn-on level voltage sections at the same timing. Further, in the second subpixel row (R (n + 2)), the second scan signal (SCAN2) supplied to the second scan signal line SCL2 and the second sense signal (SENSE2) supplied to the second sense signal line SENL2. Has a turn-on level voltage interval at the same timing. Further, in the third subpixel row (R (n + 3)), the third scan signal (SCAN3) supplied to the third scan signal line SCL3 and the third sense signal (SENSE3) supplied to the third sense signal line SENL3. Have turn-on level voltage sections at the same timing.

According to the advanced overlap drive described below, two gate signals (SCAN, SENSE) supplied to the same subpixel row can have turn-on level voltage sections at different timings.

With reference to FIG. 9, four data lines (DLc, c = 1-4) can be arranged in each of the four subpixel sequences.

Referring to FIG. 9, one reference line RL can supply a reference voltage (Vref) to the subpixels arranged in the four subpixel sequences. That is, the four subpixel sequences can share one reference line RL.

In the following description and drawings, the subpixels (SPrc, r = 1-6, c = 1-4) and signal wiring (SCLR, SENLr, DLc, RL, r = 1-6, c = 1-4) of FIG. 9 ) Arrangement is referred to.

FIG. 10 is a drive timing diagram for the advanced overlap driving of the display device 100 according to the embodiment of the present invention.

Referring to FIG. 10, a large number of subpixel SPs were coupled to a first scan signal line SCL1 transmitting a first scan signal (SCAN1) and a first sense signal line SENL1 transmitting a first sense signal (SENSE1). The first subpixel SP1, the second scan signal line SCL2 that transmits the second scan signal (SCAN2), and the second subpixel SP2 that is connected to the second sense signal line SENL2 that transmits the second sense signal (SENSE2). And the third subpixel SP3 connected to the third scan signal line SCL3 that transmits the third scan signal (SCAN3) and the third sense signal line SENL3 that transmits the third sense signal (SENSE3) can be included. ..

In FIG. 10, the first subpixel SP1 represents the subpixels (SPrc, r = 1, c = 1-4) arranged in the first subpixel row (R (n + 1)) in FIG. In FIG. 10, the second subpixel SP2 represents the subpixels (SPrc, r = 2, c = 1 to 4) arranged in the second subpixel row (R (n + 2)) in FIG. In FIG. 10, the third subpixel SP3 represents the subpixels (SPrc, r = 3, c = 1-4) arranged in the third subpixel row (R (n + 3)) in FIG.

According to this, the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 are subpixels that are sequentially arranged in the column direction.

Referring to FIG. 10, a large number of scan signal lines SCL correspond to the first scan signal corresponding to each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 sequentially arranged on the display panel 110. The line SCL1, the second scan signal line SCL2, and the third scan signal line SCL3 can be included.

Referring to FIG. 10, a large number of sense signal lines SENLs have a first sense signal corresponding to each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 sequentially arranged on the display panel 110. The line SENL1, the second sense signal line SENL2, and the third sense signal line SENL3 can be included.

The drain node (or source node) of the sense transistor SENT included in each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 can be electrically connected to the same reference line RL.

Referring to FIG. 10, the display device 100 according to an embodiment of the present invention controls the timing of the drive period of each of two adjacent subpixel rows by performing advanced overlap drive, and the adjacent 2 You can control when or the pattern in which the drive periods of each of the subpixel rows overlap each other.

Referring to FIG. 10, the display device 100 according to an embodiment of the present invention performs two gate signals, a scan signal (SCAN) and a sense, which are supplied to one subpixel row by performing an advanced overlap drive. The timing of each turn-on level voltage interval of the signal (SENSE) can be controlled.

Referring to FIG. 10, according to the advanced overlap drive, two gate signals (SCAN, SENSE) fed in the same subpixel row can have turn-on level voltage sections at different timings.

For example, during advanced overlap drive, the first scan signal (SCAN1) and the first sense signal line SENL1 supplied to the first scan signal line SCL1 in connection with the first subpixel row (R (n + 1)). The first sense signal (SENSE1) supplied does not have a turn-on level voltage interval at the same timing.

Further, during the advanced overlap drive, the second scan signal (SCAN2) and the second sense signal line SENL2 supplied to the second scan signal line SCL2 in relation to the second subpixel line (R (n + 2)) The second sense signal (SENSE2) supplied does not have a turn-on level voltage interval at the same timing.

Further, during the advanced overlap drive, the third scan signal (SCAN3) and the third sense signal line SENL3 supplied to the third scan signal line SCL3 in relation to the third subpixel line (R (n + 3)). The third sense signal (SENSE3) supplied does not have a turn-on level voltage interval at the same timing.

Hereinafter, the features of the advanced scan signals (SCAN1, SCAN2, SCAN3) and sense signals (SENSE1, SENSE2, SENSE3) for the advanced overlap drive will be specifically described.

Referring to FIG. 10, in a display device 100 according to an embodiment of the present invention, the first gate drive circuit 130 has a turn-on level voltage on a number of scan signal lines (SCL1, SCL2, SCL3) arranged on the display panel 110. Scan signals (SCAN1, SCAN2, SCAN3) having a section are sequentially supplied.

When the scan transistor SCT is an n-type transistor (transistor having an n-type channel), the turn-on level voltage section of the scan signals (SCAN1, SCAN2, SCAN3) is high, as shown in FIG. It is the (High) level voltage section, and the turn-off level voltage section of the scan signals (SCAN1, SCAN2, SCAN3) can be the low level voltage section.

When the scan transistor SCT is a p-type transistor (transistor having a p-type channel), the turn-on level voltage section of the scan signal (SCAN1, SCAN2, SCAN3) is the low level voltage section, and the scan signal (SCAN1). , SCAN2, SCAN3) turn-off level voltage section can be a high level voltage section.

Referring to FIG. 10, in the display device 100 according to the embodiment of the present invention, the second gate drive circuit 140 has a turn-on level voltage on a large number of sense signal lines (SENL1, SENL2, SENL3) arranged on the display panel 110. Sense signals (SENSE1, SENSE2, SENSE3) having a section are sequentially supplied.

When the sense transistor SENT is an n-type transistor (transistor having an n-type channel), as shown in FIG. 10, the turn-on level voltage section of the sense signals (SENSE1, SENSE2, SENSE3) is a high level voltage. It is a section, and the turn-off level voltage section of the sense signals (SENSE1, SENSE2, SENSE3) can be a low level voltage section.

When the sense transistor SENT is a p-type transistor (transistor having a p-type channel), the turn-on level voltage section of the sense signal (SENSE1, SENSE2, SENSE3) is the low level voltage section, and the sense signal (SENSE1). , SENSE2, SENSE3) turn-off level voltage section can be a high level voltage section.

Referring to FIG. 10, the first gate drive circuit 130 of the display device 100 according to the embodiment of the present invention is electrically connected to the gate node of the scan transistor SCT in the first subpixel SP1 included in a large number of subpixels SP. A first scan signal (SCAN1) having a turn-on level voltage section can be supplied to the first scan signal line SCL1.

Referring to FIG. 10, the second gate drive circuit 140 of the display device 100 according to the embodiment of the present invention is connected to the first sense signal line SENL1 electrically connected to the gate node of the sense transistor SENT in the first subpixel SP1. A first sense signal (SENSE1) having a turn-on-level voltage section delayed by a preset sense shift time (tSHIFT / SEN) as compared with the turn-on-level voltage section of one scan signal (SCAN1) is supplied. be able to.

The timing of the turn-on level voltage section of the first sense signal (SENSE1) was delayed by a preset sense shift time (tSHIFT / SEN) as compared with the turn-on level voltage section of the first scan signal (SCAN1). It can be timing.

The first scan signal (SCAN1) comes to have a turn-on level voltage in advance, and after the scan transistor SCT is sufficiently turned-on, programming for the video data voltage (Vdata) proceeds. Further, the sense transistor SENT can increase the charging speed by controlling the drive timing and expanding the channel of the sense transistor SENT, despite the delay in the turn-on level voltage section of the first sense signal (SENSE1). From such a point, the charging performance can be improved.

Referring to FIG. 10, the turn-on-level voltage section of the first sense signal (SENSE1) has a period (OP) that overlaps with the turn-on-level voltage section of the first scan signal (SCAN1) and the first scan signal (SENCE1). It can include a non-overlapping period (NOP) with the turn-on level voltage section of SCAN1).

With reference to FIG. 10, the first subpixel SP1 is programmed during the period in which the turn-on level voltage section of the first sense signal (SENSE1) and the turn-on level voltage section of the first scan signal (SCAN1) overlap. Can cope with time. The programming of the first subpixel SP1 means that the corresponding video data is programmed in the first subpixel SP1, and the capacitor Cst in the first subpixel SP1 is charged as desired by the video data voltage (Vdata). It can mean that

The period in which the turn-on-level voltage section of the first sense signal (SENSE1) and the turn-on-level voltage section of the first scan signal (SCAN1) overlap is the programming period in which video data is programmed in the first subpixel SP1 (programming period). It can correspond to tPROG).

Referring to FIG. 10, the start time of the turn-on level voltage section of the first sense signal (SENSE1) is the sense shift time (tSHIFT / SEN) from the start time of the turn-on level voltage section of the first scan signal (SCAN1). ) Can be delayed.

For example, the preset sense shift time (tSHIFT / SEN) can be a time corresponding to 1/2 of the turn-on level voltage section of the first scan signal (SCAN1).

Referring to FIG. 10, for example, the turn-on level voltage section of the first sense signal (SENSE1) and the turn-on level voltage section of the first scan signal (SCAN1) have the same temporal length.

As a result, the preset sense shift time (tSHIFT / SEN) can be a time corresponding to 1/2 of the turn-on level voltage section of the first sense signal (SENSE1).

In this case, the period in which the turn-on level voltage section of the first sense signal (SENSE1) and the turn-on level voltage section of the first scan signal (SCAN1) are superimposed can be the same as the sense shift time (tSHIFT / SEN).

The programming period (tPROG) of the first subpixel SP1 can be the same as the sense shift time (tSHIFT / SEN).

With reference to FIG. 10, the relationship and characteristics between the second scan signal (SCAN2) and the second sense signal (SENSE2) are the same as those of the first scan signal (SCAN1) and the first sense signal (SENSE1) described above. It is the same as the relationship and characteristics between. The relationship and characteristics between the third scan signal (SCAN3) and the third sense signal (SENSE3) are the relationship and characteristics between the first scan signal (SCAN1) and the first sense signal (SENSE1) described above. It is the same.

Referring to FIG. 10, a second scan signal (SCAN2) having a turn-on level voltage is supplied to the gate node of the scan transistor SCT in the second subpixel SP2, and is supplied to the gate node of the sense transistor SENT in the second subpixel SP2. Timing at which the sense transistor SENT in the first subpixel SP1 and the sense transistor SENT in the third subpixel SP3 are simultaneously turned off while the second sense signal (SENSE2) having the turn-on level voltage is supplied (PROG2). Can exist.

In other words, during the period when the turn-on level voltage section of the second scan signal (SCAN2) and the turn-on level voltage section of the second sense signal (SENSE2) overlap, the sense transistor SENT in the first subpixel SP1 and the first There can be a timing (PROG2) in which the sense transistors SENT in the 3-subpixel SP3 are turned off at the same time.

With reference to FIG. 10, the turn-on level voltage section of the first sense signal (SENSE1) can be delayed by the sense shift time (tSHIFT / SEN) from the turn-on level voltage section of the first scan signal (SCAN1). The turn-on level voltage section of the first sense signal (SENSE1) can be superimposed on the turn-on level voltage section of the first scan signal (SCAN1) by a preset programming period (tPROG).

With reference to FIG. 10, the turn-on level voltage section of the second sense signal (SENSE2) can be delayed by the sense shift time (tSHIFT / SEN) from the turn-on level voltage section of the second scan signal (SCAN2). The turn-on level voltage section of the second sense signal (SENSE2) can be superimposed only on the turn-on level voltage section of the second scan signal (SCAN2) by the programming period (tPROG).

With reference to FIG. 10, the turn-on level voltage section of the second scan signal (SCAN2) can be superimposed on the turn-on level voltage section of the first scan signal (SCAN1). The turn-on-level voltage section of the second scan signal (SCAN2) can be delayed by a preset scan shift time (tSHIFT / SCAN) from the turn-on-level voltage section of the first sense signal (SENSE1).

Referring to FIG. 10, the turn-on level voltage section of the second sense signal (SENSE2) does not overlap with the turn-on level voltage section of the first scan signal (SCAN1).

Referring to FIG. 10, during the period in which the turn-on level voltage section of the second scan signal (SCAN2) and the turn-on level voltage section of the second sense signal (SENSE2) overlap, the third sense signal (SENSE3) is It can have a turn-off level voltage.

During the programming period (tPROG) of the second subpixel SP2, the third sense signal (SENSE3) can have a turn-off level voltage.

Before the period in which the turn-on level voltage section of the second scan signal (SCAN2) and the turn-on level voltage section of the second sense signal (SENSE2) are superimposed ends, the first sense signal (SENSE1) is turned-on level. You can change from voltage to turn-off level voltage.

According to the above, the period during which the turn-on level voltage section of the second scan signal (SCAN2) and the turn-on level voltage section of the second sense signal (SENSE2) overlap (that is, programming of the second subpixel SP2). At a certain point (PROG2) of the period (tPROG)), the first sense signal (SENSE1) and the third sense signal (SENSE3) can all have a turn-off level voltage.

That is, the period during which the turn-on level voltage section of the second scan signal (SCAN2) and the turn-on level voltage section of the second sense signal (SENSE2) overlap (that is, the programming period (tPROG) of the second subpixel SP2). At a certain point (PROG2), the sense transistor SENT in the first subpixel SP1 and the sense transistor SENT in the third subpixel SP3 can all be in the turn-off state.

Therefore, when the second subpixel SP2 is the programming progress target, the second subpixel SP2 to which the programming is progressed among the first to third subpixels SP1, SP2, and SP3 is the turn-on sense transistor SENT. The second node N2 of the drive transistor DT and the reference line RL are electrically connected to each other.

At this time, among the first to third subpixels SP1, SP2, and SP3, in the case of the first subpixel SP1 located around the second subpixel SP2 where programming is progressing, the sense transistor SENT is in the turn-off state. Therefore, the second node N2 of the drive transistor DT and the reference line RL are not electrically connected. Similarly, among the first to third subpixels SP1, SP2, and SP3, in the case of the third subpixel SP3 located around the second subpixel SP2 where programming is progressing, the sense transistor SENT is in the turn-off state. Therefore, the second node N2 of the drive transistor DT and the reference line RL are not electrically connected.

The rear part of the turn-on level voltage section of the first scan signal (SCAN1) and the front part of the turn-on level voltage section of the second scan signal (SCAN2) overlap.

The rear part of the turn-on level voltage section of the first sense signal (SENSE1) and the front part of the turn-on level voltage section of the second sense signal (SENSE2) overlap.

The turn-on-level voltage section of the first sense signal (SENSE1) and the turn-on-level voltage section of the second scan signal (SCAN2) overlap with each other.

According to the example of FIG. 10, 1H is one horizontal time. The turn-on level voltage section of the first to third scan signals (SCAN3) is 1.6H. The turn-on level voltage section of the first to third sense signals (SENSE3) is 1.6H.

The preset sense shift time (tSHIFT / SEN) is 0.8H. The turn-on level voltage section of the first sense signal (SENSE1) begins with a delay of 0.8H corresponding to the sense shift time (tSHIFT / SEN) from the turn-on level voltage section of the first scan signal (SCAN1).

The period during which the turn-on level voltage section of the first scan signal (SCAN1) and the turn-on level voltage section of the first sense signal (SENSE1) overlap is 0.8H. The programming period (tPROG) of the first subpixel SP1 is 0.8H.

The turn-on-level voltage section of the second sense signal (SENSE2) begins with a delay of 0.8H corresponding to the sense shift time (tSHIFT / SEN) from the turn-on-level voltage section of the second scan signal (SCAN2).

The period during which the turn-on level voltage section of the second scan signal (SCAN2) and the turn-on level voltage section of the second sense signal (SENSE2) overlap is 0.8H. The programming period (tPROG) of the second subpixel SP2 is 0.8H.

The turn-on-level voltage section of the third sense signal (SENSE3) begins with a delay of 0.8H, which corresponds to the sense shift time (tSHIFT / SEN), from the turn-on-level voltage section of the third scan signal (SCAN3).

The period during which the turn-on level voltage section of the third scan signal (SCAN3) and the turn-on level voltage section of the third sense signal (SENSE3) overlap is 0.8H. The programming period (tPROG) of the third subpixel SP3 is 0.8H.

The preset scan shift time (tSHIFT / SCAN) is 0.2H. The turn-on level voltage section of the second scan signal (SCAN2) is delayed by 0.2 H corresponding to the preset scan shift time (tSHIFT / SCAN) from the turn-on level voltage section of the first sense signal (SENSE1). Will be done.

The turn-on level voltage section of the first scan signal (SCAN1) and the turn-on level voltage section of the second scan signal (SCAN2) are superimposed by 0.6H. The turn-on level voltage section of the first sense signal (SENSE1) and the turn-on level voltage section of the second sense signal (SENSE2) are superimposed by 0.6H.

When the turn-on level voltage section of the first sense signal (SENSE1) is 1.6H and the turn-on level voltage section of the second scan signal (SCAN2) is 1.6H, the first sense signal (SENSE1) The period during which the turn-on level voltage section and the turn-on level voltage section of the second scan signal (SCAN2) overlap is 1.4H. As a result, the length of the period (1.4H) in which the turn-on level voltage section of the first sense signal (SENSE1) and the turn-on level voltage section of the second scan signal (SCAN2) are superimposed is the total section length of each. It occupies 87.5% (= 1.4 / 1.6) as compared with (1.6H).

FIG. 11 is a drive timing diagram when the display device 100 according to an embodiment of the present invention performs a black data insertion drive and an advanced overlap drive. FIG. 12 is a diagram showing a state of the third subpixel SP3 and its adjacent subpixels SP2 and SP4 at the programming timing of the third subpixel SP3. FIG. 13 is a diagram showing the states of the fourth subpixel SP4 and its adjacent subpixels SP3 and SP5 at the programming timing of the fourth subpixel SP4 before the black data insertion drive starts. FIG. 14 is a diagram showing the states of the fifth subpixel SP5 and its adjacent subpixels SP4 and SP6 at the programming timing of the fifth subpixel SP5 after the black data insertion drive is completed.

Referring to FIG. 11, a large number of subpixel SPs were coupled to a fourth scan signal line SCL4 transmitting a fourth scan signal (SCAN4) and a fourth sense signal line SENL4 transmitting a fourth sense signal (SENSE4). The 4th subpixel SP4 and the 5th subpixel SP5 connected to the 5th scan signal line SCL5 for transmitting the 5th scan signal (SCAN5) and the 5th sense signal line SENL5 for transmitting the 5th sense signal (SENSE5). , The sixth scan signal line SCL6 that transmits the sixth scan signal (SCAN6), the sixth subpixel SP6 that is connected to the sixth sense signal line SENL6 that transmits the sixth sense signal (SENSE6), and the like can be included.

In FIG. 11, the fourth subpixel SP4 represents the subpixels (SPrc, r = 4, c = 1-4) arranged in the fourth subpixel row (R (n + 4)) in FIG. In FIG. 11, the fifth subpixel SP5 represents the subpixels (SPrc, r = 5, c = 1-4) arranged in the fifth subpixel row (R (n + 5)) in FIG. In FIG. 11, the sixth subpixel SP6 represents the subpixels (SPrc, r = 6, c = 1 to 4) arranged in the sixth subpixel row (R (n + 6)) in FIG.

Referring to FIG. 11, the period during which the turn-on level voltage section of the third scan signal (SCAN3) and the turn-on level voltage section of the third sense signal (SENSE3) overlap (that is, the programming period of the third subpixel SP3). (TPROG)), the fourth sense signal (SENSE4) has a turn-off level voltage.

The period in which the turn-on-level voltage section of the third scan signal (SCAN3) and the turn-on-level voltage section of the third sense signal (SENSE3) overlap (that is, the programming period (tPROG) of the third subpixel SP3) ends. Previously, at a certain timing (PROG3), the second sense signal (SENSE2) is changed from the turn-on level voltage to the turn-off level voltage.

Referring to FIG. 12, the programming period (tPROG) of the third subpixel SP3 in which the turn-on level voltage section of the third scan signal (SCAN3) and the turn-on level voltage section of the third sense signal (SENSE3) are superimposed. Meanwhile, the scan transistor SCT and the sense transistor SENT in the third subpixel SP3 are all in the turn-on state.

During the programming period (tPROG) of the third subpixel SP3, the second node N2 of the drive transistor DT in the third subpixel SP3 is electrically connected to the reference line RL by the turn-on sense transistor SENT.

During the programming period (tPROG) of the third subpixel SP3, the sense transistor SENT in the fourth subpixel SP4 can be in the turn-off state by the fourth sense signal (SENSE4) of the turn-off level voltage. Therefore, the reference line RL in which the second node N2 of the drive transistor DT in the third subpixel SP3 is electrically connected through the sense transistor SENT turned on is not affected by the fourth subpixel SP4.

At a certain timing (PROG3) in the programming period (tPROG) of the third subpixel SP3, the sense transistor SENT in the second subpixel SP2 is in a turn-off state by the second sense signal (SENSE2) of the turn-off level voltage. Can be. Therefore, the reference line RL in which the second node N2 of the drive transistor DT in the third subpixel SP3 is electrically connected through the sense transistor SENT turned on is not affected by the second subpixel SP2.

According to the above-mentioned advanced overlap drive, during the programming period (tPROG) of the third subpixel SP3, the timing at which all the sense transistors SENT in the adjacent subpixels (SP2, SP4) of the third subpixel SP3 are turned off ( Since PROG3) is present, the third subpixel SP3 is not affected by the adjacent subpixels (SP2, SP4), and can proceed with normal programming operation to exhibit a light emitting state with a desired brightness.

Referring to FIG. 11, the period during which the turn-on-level voltage section of the fourth scan signal (SCAN4) and the turn-on-level voltage section of the fourth sense signal (SENSE4) overlap (that is, the programming period of the fourth subpixel SP4). (TPROG)), the fifth sense signal (SENSE5) has a turn-off level voltage.

The period in which the turn-on-level voltage section of the fourth scan signal (SCAN4) and the turn-on-level voltage section of the fourth sense signal (SENSE4) overlap (that is, the programming period (tPROG) of the fourth subpixel SP4) ends. Previously, at a certain timing (PROG4), the third sense signal (SENSE3) is changed from the turn-on level voltage to the turn-off level voltage.

Referring to FIG. 13, the programming period of the fourth subpixel SP4, which is the period in which the turn-on level voltage section of the fourth scan signal (SCAN4) and the turn-on level voltage section of the fourth sense signal (SENSE4) overlap. During tPROG), the scan transistor SCT and sense transistor SENT in the fourth subpixel SP4 are all in the turn-on state.

During the programming period (tPROG) of the fourth subpixel SP4, the second node N2 of the drive transistor DT in the fourth subpixel SP4 is electrically connected to the reference line RL by the turn-on sense transistor SENT.

During the programming period (tPROG) of the fourth subpixel SP4, the sense transistor SENT in the fifth subpixel SP5 can be in the turn-off state by the fifth sense signal (SENSE5) of the turn-off level voltage. Therefore, the reference line RL in which the second node N2 of the drive transistor DT in the fourth subpixel SP4 is electrically connected through the sense transistor SENT turned on is not affected by the fifth subpixel SP5.

At a certain timing (PROG4) in the programming period (tPROG) of the 4th subpixel SP4, the sense transistor SENT in the 3rd subpixel SP3 is in the turn-off state by the 3rd sense signal (SENSE3) of the turn-off level voltage. Can be. Therefore, the reference line RL in which the second node N2 of the drive transistor DT in the fourth subpixel SP4 is electrically connected through the sense transistor SENT turned on is not affected by the third subpixel SP3.

According to the above-mentioned advanced overlap drive, during the programming period (tPROG) of the 4th subpixel SP4, the timing at which all the sense transistors SENT in the adjacent subpixels (SP3, SP5) of the 4th subpixel SP4 are turned off ( Since PROG4) is present, the fourth subpixel SP4 is not affected by the adjacent subpixels (SP3, SP5), and can proceed with normal programming operation to exhibit a light emitting state with a desired brightness.

Referring to FIG. 11, the period during which the turn-on-level voltage section of the fifth scan signal (SCAN5) and the turn-on-level voltage section of the fifth sense signal (SENSE5) overlap (that is, the programming period of the fifth subpixel SP5). (TPROG)), the sixth sense signal (SENSE6) has a turn-off level voltage.

The period in which the turn-on-level voltage section of the fifth scan signal (SCAN5) and the turn-on-level voltage section of the fifth sense signal (SENSE5) overlap (that is, the programming period (tPROG) of the fifth subpixel SP5) ends. Previously, at a certain timing (PROG5), the fourth sense signal (SENSE4) is changed from the turn-on level voltage to the turn-off level voltage.

Referring to FIG. 14, the programming period of the fifth subpixel SP5, which is the period in which the turn-on level voltage section of the fifth scan signal (SCAN5) and the turn-on level voltage section of the fifth sense signal (SENSE5) overlap. During tPROG), the scan transistor SCT and the sense transistor SENT in the fifth subpixel SP5 are all in the turn-on state.

During the programming period (tPROG) of the fifth subpixel SP5, the second node N2 of the drive transistor DT in the fifth subpixel SP5 is electrically connected to the reference line RL by the turn-on sense transistor SENT.

During the programming period (tPROG) of the fifth subpixel SP5, the sense transistor SENT in the sixth subpixel SP6 can be in the turn-off state by the sixth sense signal (SENSE6) of the turn-off level voltage. Therefore, the reference line RL in which the second node N2 of the drive transistor DT in the fifth subpixel SP5 is electrically connected through the sense transistor SENT turned on is not affected by the sixth subpixel SP6.

At a certain timing (PROG5) in the programming period (tPROG) of the 5th subpixel SP5, the sense transistor SENT in the 4th subpixel SP4 is in a turn-off state by the 4th sense signal (SENSE4) of the turn-off level voltage. Can be. Therefore, the reference line RL in which the second node N2 of the drive transistor DT in the fifth subpixel SP5 is electrically connected through the sense transistor SENT turned on is not affected by the fourth subpixel SP4.

According to the above-mentioned advanced overlap drive, during the programming period (tPROG) of the 5th subpixel SP5, the timing at which all the sense transistors SENT in the adjacent subpixels (SP4, SP6) of the 5th subpixel SP5 are turned off ( Since PROG5) is present, the fifth subpixel SP5 is not affected by the adjacent subpixels (SP4, SP6), and can proceed with normal programming operation to exhibit a light emitting state with a desired brightness.

Referring to FIG. 11, the period during which the fourth scan signal (SCAN4) having the turn-on level voltage is supplied to the fourth scan signal line SCL4 and the fifth scan having the turn-on level voltage on the fifth scan signal line SCL5. Subpixels arranged in k (k is a natural number of 1 or more) subpixel lines (subpixel rows) during the fake data insertion (FDI) drive period between the period during which the signal (SCAN5) is supplied. A fake data voltage (Vfake) that is distinguished from the actual video data voltage (Vdata) can be supplied to the SP.

Here, fake data insertion (FDI) is also referred to as black data insertion (BDI) in which black data is inserted, for example.

Generally speaking, of the large number of scan signal lines, the period during which the i-th scan signal (SCAN) having the turn-on level voltage is supplied to the i-th scan signal line (i is a natural number of 1 or more) and Fake data insertion (FDI) drive between the period during which the (i + 1) th scan signal (i + 1) th scan signal (SCAN) having the turn-on level voltage is supplied to the (i + 1) th scan signal line among a large number of scan signal lines. During the period, the subpixel SPs arranged in k (k is a natural number of 1 or more) subpixel lines (subpixel rows) have a fake data voltage (Vfake) that is distinguished from the actual video data voltage (Vdata). ) Can be supplied.

Referring to FIG. 11, data during the fake data insertion drive period (tFDI) between the turn-on-level voltage section of the fourth scan signal (SCAN4) and the turn-on-level voltage section of the fifth scan signal (SCAN5). The drive circuit 120 can output a fake data voltage (Vfake) that is distinguished from the actual video data voltage (Vdata) to all or part of a large number of data lines DL.

The fake data voltage (Vfake) can be supplied to the subpixel SPs arranged in k (k is a natural number of 1 or more) subpixel lines (subpixel rows).

For example, the fake data voltage (Vfake) can be a black data voltage (Vblack), a low gradation data voltage, or the like. When the fake data voltage (Vfake) is the black data voltage (Vblack), the fake data insertion (FDI) drive is called the black data insertion (BDI) drive.

With reference to FIG. 11, the precharge drive period (tPC) can proceed after the fake data insertion drive period (tFDI).

Referring to FIG. 11, the data drive circuit 120 outputs the fake data voltage (Vfake) during the fake data insertion drive period (tFDI), and then outputs the precharge data voltage (Vpre) during the precharge drive period (tPC). It can be output to all or part of a large number of data line DLs.

Referring to FIG. 11, after the data drive circuit 120 starts outputting the precharge data voltage (Vpre), the first gate drive circuit 130 has a turn-on level voltage on the fifth scan signal line SCL5. (SCAN5) can be output.

The period in which the turn-on-level voltage section of the fifth scan signal (SCAN5) and the turn-on-level voltage section of the fifth sense signal (SENSE5) overlap (that is, the programming period of the fifth subpixel SP5) is the data drive circuit. It can proceed after the period in which 120 outputs the precharge data voltage (Vpre) (that is, the precharge drive period (tPC)).

FIG. 15 is a diagram showing a fake data insertion drive (for example, black data insertion drive) of the display device 100 according to the embodiment of the present invention.

Referring to FIG. 15, during the fake data insertion drive period (tFDI), the fake data voltage (Vfake) for fake data insertion is applied to the first node N1 of the k subpixel SP intra-drive transistors DT.

Therefore, when the data drive circuit 120 outputs the fake data voltage (Vfake), all the scan transistors SCT in the k subpixel SPs are in the turn-on state, and in the subpixel SP excluding the k subpixel SPs. All scan transistor SCTs are in the turn-off state.

When the data drive circuit 120 outputs the fake data voltage (Vfake), all the sense transistors SENTs of all the subpixel SPs including the k subpixel SPs and the remaining subpixel SPs are in the turn-off state.

In other words, during the fake data insertion drive period (tFDI), when the data drive circuit 120 outputs the fake data voltage (Vfake), the first gate drive circuit 130 has k subs of a large number of scan signal line SCLs. A scan signal having a turn-on level voltage can be output to the k scan signal lines corresponding to the pixel lines, and a scan signal having a turn-off level voltage can be output to the remaining scan signal lines. The second gate drive circuit 140 can output a sense signal having a turn-off level voltage to all of a large number of sense signal lines SENL.

FIG. 16 is a diagram showing a precharge drive of the display device 100 according to the embodiment of the present invention.

Referring to FIG. 16, during the precharge drive period (tPC), when the data drive circuit 120 outputs the precharge data voltage (Vpre), the first gate drive circuit 130 turns to all of the numerous scan signal line SCLs. A scan signal (SCAN) having an off-level voltage can be output, and the second gate drive circuit 140 can output a sense signal (SENSE) having a turn-off level voltage to all of a large number of sense signal lines SENL.

During the precharge drive period (tPC), the precharge data voltage (Vpre) is only applied to a large number of data line DLs, not inside a large number of subpixel SPs.

In other words, during the precharge drive period (tPC), the precharge data voltage (Vpre) is only applied to a large number of data line DLs and is the first node of each drive transistor DT of a large number of subpixel SPs. It is not applied to N1.

FIG. 17 is a diagram showing a setting range of the precharge data voltage (Vpre) used in the precharge drive of the display device 100 according to the embodiment of the present invention.

Also referring to FIG. 17, the precharge data voltage (Vpre) applied to one or more data lines DL during the precharge drive period (tPC) is before the precharge data voltage (Vpre) is output. The output first video data voltage (Vdata1), the second video data voltage (Vdata2) output after the precharge data voltage (Vpre) is output, the fake data voltage (Vfake), and the first video data. It can be one of the higher voltage of the voltage (Vdata1) and the second video data voltage (Vdata2) and the voltage between the fake data voltage (Vfake).

With reference to FIG. 17, within the setting range in which the fake data voltage (Vfake) is the lower limit value and the higher voltage of the first video data voltage (Vdata1) and the second video data voltage (Vdata2) is the upper limit value. , Precharge data voltage (Vpre) can be set.

FIG. 18 is a diagram showing a scan transistor SCT of the display device 100 according to the embodiment of the present invention, and FIG. 19 is a diagram showing a sense transistor SENT of the display device 100 according to the embodiment of the present invention. The circuit of the subpixel SP of FIG. 2 is also referred to.

Referring to FIG. 18, the scan transistor SCT acts as a drain node (or source node) of the scan transistor SCT, and has a first scan pattern 1810 electrically connected to the data line DL and a source of the scan transistor SCT. The second scan pattern 1820, which acts as a node (or drain node) and is electrically connected to the first node N1 of the drive transistor DT, is electrically connected between the first scan pattern 1810 and the second scan pattern 1820. One side is connected to the first scan pattern 1810 through the contact hole CNT, and the other side is connected to the second scan pattern 1820, or includes a gate electrode 1800 integrated with the second scan pattern 1820, etc. be able to.

The scan signal line SCL can be arranged so as to overlap the gate electrode 1800 of the scan transistor SCT. The portion of the gate electrode 1800 of the scan transistor SCT that overlaps with the scan signal line SCL corresponds to the channel CHc of the scan transistor SCT. The channel CHc of the scan transistor SCT has a channel width (Wc) and a channel length (Lc).

The ratio (Wc / Lc) of the channel width (Wc) to the channel length (Lc) in the scan transistor SCT can determine the characteristics of the channel CHc of the scan transistor SCT. In the scan transistor SCT, the ratio (Wc / Lc) of the channel width (Wc) to the channel length (Lc) can determine the on-off characteristics and switching performance of the scan transistor SCT.

Referring to FIG. 19, the sense transistor SENT acts as a drain node (or source node) of the sense transistor SENT, and has a first pattern 1910 electrically connected to the reference line RL and a source node of the sense transistor SENT. The second pattern 1920, which acts as a (or drain node) and is electrically connected to the second node N2 of the drive transistor DT, and the first pattern 1910 and the second pattern 1920 are electrically connected. It can include a gate electrode 1900 or the like in which one side is connected to the first pattern 1910 through a contact hole CNT and the other side is connected to a second pattern 1920 through another contact hole CNT.

The sense signal line SENL can be arranged so as to overlap with the gate electrode 1900 of the sense transistor SENT. The portion of the gate electrode 1900 of the sense transistor SENT that overlaps with the sense signal line SENL corresponds to the channel CHs of the sense transistor SENT. The channel CHs of the sense transistor SENT have a channel width (Ws) and a channel length (Ls).

The ratio (Ws / Ls) of the channel width (Ws) to the channel length (Ls) of the sense transistor SENT can determine the characteristics of the channel CHs of the sense transistor SENT. The ratio (Ws / Ls) of the channel width (Ws) to the channel length (Ls) of the sense transistor SENT can determine the on-off characteristics and switching performance of the sense transistor SENT.

With reference to FIGS. 18 and 19, the ratio (Ws / Ls) of the channel width (Ws) to the channel length (Ls) of the sense transistor SENT is the channel width (Wc) with respect to the channel length (Lc) of the scan transistor SCT. It may be larger than the ratio (Wc / Lc).

According to the advanced overlap drive, in one subpixel SP, the turn-on level voltage section of the sense signal (SENSE) is the sense shift time (tSHIFT / SEN) from the turn-on level voltage section of the scan signal (SCAN). For normal charging and normal programming operation, the sense transistor SENT needs to have a faster turn-on speed than the turn-on speed of the scan transistor SCT, as it is only delayed.

Therefore, as described above, the ratio (Ws / Ls) of the channel width (Ws) to the channel length (Ls) of the sense transistor SENT is the ratio of the channel width (Wc) to the channel length (Lc) of the scan transistor SCT ( By designing to be larger than Wc / Lc), it is possible to ensure that the charging time of the storage capacitor Cst is not insufficient while carrying out the above-mentioned advanced overlap drive. As a result, the programming operation of the corresponding sub-pixel SP can be performed quickly and normally.

On the other hand, when a large number of subpixels SP include subpixels that emit different light (eg, subpixels that emit red light, subpixels that emit green light, subpixels that emit blue light, and subpixels that emit white light). The ratio (Ws / Ls) of the channel width (Ws) to the channel length (Ls) of the sense transistor SENT for each of the subpixels that emit different light can all be the same.

Unlike this, the ratio (Ws / Ls) of the channel width (Ws) to the channel length (Ls) of at least one subpixel sense transistor SENT out of the four subpixels that emit different light is the remaining subpixels. It may be different from the ratio (Ws / Ls) of the channel width (Ws) to the channel length (Ls) of the intra-pixel sense transistor SENT.

FIG. 20 is a flowchart for a driving method of the display device 100 according to the embodiment of the present invention.

Referring to FIG. 20, the driving method of the display device 100 including a large number of subpixel SPs is a first scan signal line connected to the gate node of the scan transistor SCT in the first subpixel SP1 among the large number of subpixels SPs. The step (S2010) of supplying the first scan signal (SCAN1) having a turn-on level voltage section to the SCL1 and the first sense signal line electrically connected to the gate node of the sense transistor SENT in the first subpixel SP1. The first sense signal (SENSE1) having a turn-on level voltage section delayed by a preset sense shift time (tSHIFT / SEN) with respect to the turn-on level voltage section of the first scan signal (SCAN1) in SENL1. (S2020) and the first scan signal (SCAN1) having a turn-off level voltage section on the first scan signal line SCL1 and having a turn-off level voltage section on the first sense signal line SENL1. The step (S2030) for supplying the first sense signal (SENSE1) and the like can be included.

In step S2010, the display device 100 may transmit the video data voltage (Vdata) supplied to the data line DL to the first node N1 of the drive transistor DT in the first subpixel SP1 through the turn-on scan transistor SCT. it can.

In step S2020, the display device 100 can transmit the reference voltage (Vref) supplied to the reference line RL to the second node N2 of the drive transistor DT through the turn-on sense transistor SENT.

In step S2030, the voltages of the first node N2 and the second node N2 of the drive transistor DT increase. Here, the second node N2 of the drive transistor DT can be electrically connected to the first electrode of the light emitting element EL.

In step S2030, when the voltage of the second node N2 of the drive transistor DT rises by a certain level or more, a current flows through the light emitting element EL, and the light emitting element EL starts emitting light.

The turn-on level voltage section of the first sense signal (SENSE1) is the period (OP) that overlaps with the turn-on level voltage section of the first scan signal (SCAN1) and the turn-on of the first scan signal (SCAN1). It can include a period (NOP) that does not overlap with the level voltage interval.

The start time of the turn-on level voltage section of the first sense signal (SENSE1) is delayed by the sense shift time (tSHIFT / SEN) from the start time of the turn-on level voltage section of the first scan signal (SCAN1), and the sense is sensed. The shift time (tSHIFT / SEN) can be a time corresponding to 1/2 of the turn-on level voltage section of the first scan signal (SCAN1).

The large number of subpixels SP further includes a second subpixel SP2 and a third subpixel SP3, and a drain node of the sense transistor SENT included in each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3. Alternatively, the source node can be electrically connected to the same reference line.

A second scan signal (SCAN2) having a turn-on level voltage is supplied to the gate node of the scan transistor SCT in the second subpixel SP2, and a turn-on level voltage is applied to the gate node of the sense transistor SENT in the second subpixel SP2. While the second sense signal (SENSE2) to have is supplied, there can be a timing (PROG2) in which the sense transistor SENT in the first subpixel SP1 and the sense transistor SENT in the third subpixel SP3 are simultaneously turned off.

Of the large number of scan signal lines, the period during which the i-th scan signal line (i is a natural number of 1 or more) is supplied with the i-th scan signal (SCAN) having a turn-on level voltage, and a large number of scan signals. Of the lines, of the fake data insertion (FDI) drive period between the period during which the (i + 1) th scan signal (SCAN) having the turn-on level voltage is supplied to the (i + 1) th scan signal line. A fake data voltage (Vfake) that is distinguished from the actual video data voltage (Vdata) can be supplied to the subpixel SPs arranged in k (k is a natural number of 1 or more) subpixel lines (subpixel rows). ..

FIG. 21 is a diagram for explaining the effect of preventing a specific line luminance defect when the display device 100 according to the embodiment of the present invention performs the fake data insertion drive and the advanced overlap drive.

As described above, in the case of the overlap drive described with reference to FIGS. 5 and 6, when the fake data insertion drive proceeds during the overlap drive, the subpixel row immediately before the fake data insertion drive is a bright line. A specific line bright phenomenon, which is seen as 700, can occur.

However, in the case of advanced overlap drive, the turn-on level voltage section of the sense signal is scanned out of the two gate signals (scan signal and sense signal) even if the fake data insertion drive is advanced during the overlap drive. Overlap drive characteristics do not change immediately prior to fake data insertion drive through advanced overlap drive that controls the signal to be delayed from the turn-on level voltage section. That is, according to the advanced overlap drive, each of all the subpixels in which programming proceeds is unaffected by adjacent subpixels.

Therefore, according to the advanced overlap drive, it is possible to prevent a specific line obvious phenomenon in which the subpixel line immediately before the fake data insertion drive (eg, the fourth, eighth subpixel line, etc.) is seen as a bright line 700.

FIG. 22 is a diagram showing a gate drive circuit 2200 according to an embodiment of the present invention, FIG. 23 is a gate drive timing diagram according to an embodiment of the present invention, and FIG. 24 is a gate signal output unit 2400 according to an embodiment of the present invention. It is a figure which shows.

With reference to FIG. 22, the gate drive circuit 2200 according to the embodiment of the present invention can include a level shifter circuit 2210 and a gate signal output unit 2220.

With reference to FIG. 22, the level shifter circuit 2210 can include a scan clock signal generation unit 2211, a sense clock signal generation unit 2212, and the like.

The scan clock signal generation unit 2211 receives the input of the first reference scan clock signal (GCLK_SC) and the second reference scan clock signal (MCLK_SC), and generates and outputs a plurality of scan clock signals (example: SC_CLK1 to SC_CLK8). be able to. Here, the plurality of scan clock signals (SC_CLK1 to SC_CLK8) can have signal waveforms shifted by a certain period of time.

The sense clock signal generation unit 2212 may generate and output a plurality of sense clock signals (SE_CLK1 to SE_CLK8) by receiving the input of the first reference sense clock signal (GCLK_SE) and the second reference sense clock signal (MCLK_SE). it can. Here, the plurality of sense clock signals (SE_CLK1 to SE_CLK8) can have signal waveforms shifted by a certain period of time.

When the gate drive circuit 2200 performs n-phase gate drive, n scan clock signals can be generated and n sense clock signals can be generated. For example, as shown in FIG. 22, when the gate drive circuit 2200 performs 8-phase gate drive, eight scan clock signals (SC_CLK1 to SC_CLK8) are generated, and eight sense clock signals (SE_CLK1 to SE_CLK8) are generated. Can be generated.

With reference to FIG. 22, the level shifter circuit 2210 may further include a carry clock signal generator 2213.

Referring to FIG. 22, the gate signal output unit 2220 outputs a scan signal (SCAN) having a turn-on level voltage section based on a plurality of sense clock signals (SE_CLK1 to SE_CLK8), and outputs a plurality of sense clock signals (SE_CLK1 to SE_CLK8). A sense signal (SENSE) having a turn-on level voltage section can be output based on SE_CLK8).

With reference to FIG. 22, the scan clock signal generation unit 2211 can include a scan logic unit (LOGIC_SC) and a scan level shifter (LS_SC).

The scan logic unit (LOGIC_SC) receives the input of the first reference scan clock signal (GCLK_SC) and the second reference scan clock signal (MCLK_SC), rises to the rising timing of the first reference scan clock signal (GCLK_SC), and second. It is possible to generate scan clock signals (SC_CLK1 to SC_CLK8) that fall at the falling timing of the reference scan clock signal (MCLK_SC).

The scan level shifter (LS_SC) can output by changing the voltage level of the scan clock signals (SC_CLK1 to SC_CLK8) generated by the scan logic unit (LOGIC_SC).

The scan level shifter (LS_SC) can output scan clock signals (SC_CLK1 to SC_CLK8).

The sense clock signal generation unit 2212 can include a sense logic unit (LOGIC_SE), a delay device (DD), and a sense level shifter (LS_SE).

The sense logic unit (LOGIC_SE) receives the input of the first reference sense clock signal (GCLK_SE) and the second reference sense clock signal (MCLK_SE), and can generate the sense clock signals (SE_CLK1 to SE_CLK8) by the signal control logic. ..

The sense clock signals (SE_CLK1 to SE_CLK8) generated by the signal control logic are not raised at the rising timing of the first reference sense clock signal (GCLK_SE), but are raised at the rising timing of the second reference sense clock signal (MCLK_SE). After the falling timing of the two reference sense clock signals (MCLK_SE), a preset delay time (tDELAY) can be subsequently dropped.

The delay device (DD) does not rise the sense clock signal (SE_CLK1 to SE_CLK8) at the rising timing of the first reference sense clock signal (GCLK_SE), but rises at the rising timing of the second reference sense clock signal (MCLK_SE). The rising timing of the sense clock signals (SE_CLK1 to SE_CLK8) can be delayed.

The sense level shifter (LS_SE) can output by changing the voltage level of the sense clock signals (SE_CLK1 to SE_CLK8) generated by the sense logic unit (LOGIC_SE).

The sense level shifter (LS_SE) is raised to the high level gate voltage, fallen to the low level gate voltage, and delayed by the sense shift time (tSHIFT / SEN) compared to the high level gate voltage section of the scan clock signals (SC_CLK1 to SC_CLK8). It is possible to output a sense clock signal (SE_CLK1 to SE_CLK8) having a high level gate voltage section.

With reference to FIG. 22, for example, the delay device (DD) can include one or more resistance elements.

The carry clock signal generation unit 2213 may generate and output a plurality of carry clock signals (CR_CLK1 to CR_CLK8) by receiving the inputs of the first reference carry clock signal (GCLK_CR) and the second reference scan clock signal (MCLK_SC). it can.

With reference to FIG. 22, the carry clock signal generation unit 2213 can include a carry logic unit (LOGIC_CR) and a carry level shifter (LS_CR).

The carry logic unit (LOGIC_CR) receives the input of the first reference carry clock signal (GCLK_CR) and the second reference carry clock signal (MCLK_CR), and is rised to the rising timing of the first reference carry clock signal (GCLK_CR). 2. It is possible to generate a plurality of carry clock signals (CR_CLK1 to CR_CLK8) that are fallen at the falling timing of the reference carry clock signal (MCLK_CR). Here, the plurality of carry clock signals (CR_CLK1 to CR_CLK8) can have the same waveform as the plurality of scan clock signals (SC_CLK1 to SC_CLK8).

The carry level shifter (LS_CR) can change and output the voltage levels of a plurality of carry clock signals (CR_CLK1 to CR_CLK8) generated by the carry logic unit (LOGIC_CR).

The carry level shifter (LS_CR) can output a plurality of carry clock signals (CR_CLK1 to CR_CLK8) that are raised to a high level gate voltage and fallen to a low level gate voltage.

On the other hand, the level shifter circuit 2210 included in the gate drive circuit 2200 can be realized by one integrated circuit chip.

The gate signal output unit 2220 included in the gate drive circuit 2200 can also be embodied by one or more integrated circuit chips.

Alternatively, the gate signal output unit 2220 included in the gate drive circuit 2200 can be realized by a GIP (Gate In Panel) type. In this case, the gate signal output unit 2220 is a non-display panel 110 on which the scan signal line (SCL) to which the scan signal (SCAN) is applied and the sense signal line (SENL) to which the sense signal (SENSE) is applied are arranged. Can be placed in the display area.

The gate drive circuit 2200 of FIG. 22 may be a circuit embodied including the first gate drive circuit 130 and the second gate drive circuit 140 of FIG.

Hereinafter, the features of the scan clock signals (SC_CLK1 to SC_CLK8) generated by the scan clock signal generation unit 2211 and the sense clock signals (SE_CLK1 to SE_CLK8) generated by the sense clock signal generation unit 2212 will be described in more detail with reference to FIG. Explain to. However, for convenience of explanation, one of the plurality of sense clock signals (SE_CLK1 to SE_CLK8) is taken as an example of one scan clock signal (SC_CLK) among the plurality of scan clock signals (SC_CLK1 to SC_CLK8). Taking one sense clock signal (SE_CLK) as an example, one carry clock signal (CR_CLK) among a plurality of carry clock signals (CR_CLK1 to CR_CLK8) will be given as an example.

With reference to FIG. 23, after the first reference scan clock signal (GCLK_SC) is rising and falling, the second reference scan clock signal (MCLK_SC) can be raised and fallen.

After the first reference sense clock signal (GCLK_SE) is rising and falling, the second reference sense clock signal (MCLK_SE) can be raised and fallen.

Referring to FIG. 23, the high level gate voltage section of the sense clock signal (SE_CLK) can be delayed by a preset sense shift time (tSHIFT / SEN) as compared with the high level gate voltage section of the scan clock signal (SC_CLK).

Therefore, the turn-on level voltage section of the sense signal (SENSE) generated from the sense clock signal (SE_CLK) is compared to the turn-on level voltage section of the scan signal (SCAN) generated from the scan clock signal (SC_CLK). It can be delayed by the sense shift time (tSHIFT / SEN).

Referring to FIG. 23, the scan clock signal generation unit 2211 rises to the rising timing of the first reference scan clock signal (GCLK_SC) and falls to the falling timing of the second reference scan clock signal (MCLK_SC). A signal (SC_CLK) can be generated and output.

The sense clock signal generation unit 2212 is not raised at the rising timing of the first reference sense clock signal (GCLK_SE), but is raised at the rising timing of the second reference sense clock signal (MCLK_SE), and the second reference sense clock signal (MCLK_SE). After the falling timing of, a preset delay time (tDELAY) can be generated and output as a sense clock signal (SE_CLK) to be fallen thereafter.

The time interval between the rising timing of the first reference sense clock signal (GCLK_SE) and the rising timing of the second reference sense clock signal (MCLK_SE) can correspond to the sense shift time (tSHIFT / SEN).

With reference to FIG. 23, the rising timing of the first reference sense clock signal (GCLK_SE) can be the same as the rising timing of the first reference scan clock signal (GCLK_SC).

In order to indicate the rising timing of the sense clock signal (SE_CLK), the rising timing of the second reference sense clock signal (MCLK_SE) can precede the rising timing of the second reference scan clock signal (MCLK_SC).

Referring to FIG. 23, the length of the superposition time (eg 0.8H) between the scan clock signal (SC_CLK) and the sense clock signal (SE_CLK) is the turn-on level voltage section of the sense signal (SENSE). It can correspond to the value obtained by subtracting the delay time (Tdeli, eg 0.8H) from the temporal length (eg 1.6H).

As described above, the gate signal output unit 2220 can output a scan signal (SCAN) to a plurality of scan signal lines (SCL) and output a sense signal (SENSE) to a plurality of sense signal lines (SENL). Such a gate signal output unit 2220 can include a plurality of gate signal output units 2400 corresponding to a plurality of stages.

Referring to FIG. 24, each of the plurality of gate signal output units 2400 outputs a scan signal (SCAN) to one scan signal line (SCL) and outputs a sense signal (SENSE) to one sense signal line (SENL). can do.

Each of the plurality of gate signal output units 2400 can include an output buffer circuit 2410 and a control logic circuit 2420.

The output buffer circuit 2410 includes a first pull-up transistor (Tu1) and a first pull-down transistor (Td1) for outputting the nth scan signal (SCAN (n)), and includes an nth sense signal (Td1). A third carry signal (CR (n)) including a second pull-up transistor (Tu2) for outputting SENSE (n)) and a second pull-down transistor (Td2) for outputting the nth carry signal (CR (n)). A pull-up transistor (Tu3) and a third pull-down transistor (Td3) can be included.

The first pull-up transistor (Tu1) and the first pull-down transistor (Td1) are the first clock signal node (NH1) to which the nth upper scan clock signal (SC_CLK (n)) is applied and the gate base voltage (NH1). It can be connected in series with the gate base node (NL) to which GVSS) is applied.

The first connection point (Nout1) to which the first pull-up transistor (Tu1) and the first pull-down transistor (Td1) are connected is a point where a scan signal (SCAN) is output, and is a scan signal line (SCL). ) Can be electrically connected.

The second pull-up transistor (Tu2) and the second pull-down transistor (Td2) have a second clock signal node (NH2) to which the nth upper sense clock signal (SE_CLK (n)) is applied and a gate ground voltage (NH2). It can be connected in series with the gate base node (NL) to which GVSS) is applied.

The second connection point (Nout2) to which the second pull-up transistor (Tu2) and the second pull-down transistor (Td2) are connected is a point where the sense signal (SENSE) is output, and the sense signal line (SENL). ) Can be electrically connected.

The third pull-up transistor (Tu3) and the third pull-down transistor (Td3) are applied with the n-th upper scan clock signal (CR_CLK (n)) to the third clock signal node (NH3) and the gate ground voltage (N). It can be connected in series with the gate base node (NL) to which GVSS) is applied.

The third connection point (Nout3) to which the third pull-up transistor (Tu3) and the third pull-down transistor (Td3) are connected is the point where the nth carry signal (CR (n)) is output.

The nth carry signal (CR (n)) can be input to the gate signal output unit 2400 of the subsequent stage (for example, the (n + 2) th stage) of the gate signal output unit 2400 of FIG. 24.

The gate node of the first pull-up transistor (Tu1) can be electrically connected to the Q1 node. The first pull-up transistor (Tu1) can be turned on and off by the voltage of the Q1 node.

The gate node of the second pull-up transistor (Tu2) can be electrically connected to the Q2 node. The second pull-up transistor (Tu2) can be turned on and off by the voltage of the Q2 node.

The gate node of the third pull-up transistor (Tu3) can be electrically connected to the Q3 node. The third pull-up transistor (Tu3) can be turned on and off by the voltage of the Q3 node.

The gate node of the first pull-down transistor (Td1) can be electrically connected to the QB1 node. The first pull-down transistor (Td1) can be turned on and off by the voltage of the QB1 node.

The gate node of the second pull-down transistor (Td2) can be electrically connected to the QB2 node. The second pull-down transistor (Td2) can be turned on and off by the voltage of the QB2 node.

The gate node of the third pull-down transistor (Td3) can be electrically connected to the QB3 node. The third pull-down transistor (Td3) can be turned on and off by the voltage of the QB3 node.

The control logic circuit 2420 controls the voltages of the Q1 node, the Q2 node, and the Q3 node by receiving the input of the carry signal (CR (n-2)), the start signal (VST), and the reset signal (RST) of the previous stage. Then, the voltages of the QB1 node, the QB2 node, and the QB3 node can be controlled. The control logic circuit 2420 can include a plurality of transistors and one or more capacitors.

The Q1 node, Q2 node, and Q3 node can be electrically separated nodes. Alternatively, the Q1 node, the Q2 node, and the Q3 node can all be electrically connected nodes. Alternatively, the Q1 node and the Q3 node may be electrically connected, and the Q2 node may be a node that is electrically separated from the Q1 node and the Q3 node.

The QB1 node, QB2 node, and QB3 node can be electrically separated nodes. Alternatively, the QB1 node, the QB2 node, and the QB3 node can all be electrically connected nodes. Alternatively, the QB1 node and the QB3 node may be electrically connected, and the QB2 node may be a node that is electrically separated from the QB1 node and the QB3 node.

If the first pull-up transistor (Tu1) is turned on, the first pull-down transistor (Td1) can be turned off. At this time, a scan signal (SCAN) having a turn-on level voltage section (eg, high level gate voltage section) can be output through the first pull-up transistor (Tu1) based on the scan clock signal (SC_CLK (n)). ..

If the first pull-up transistor (Tu1) is turned off, the first pull-down transistor (Td1) can be turned on. At this time, a scan signal (SCAN) having a turn-off level voltage section (eg, low level gate voltage section) can be output through the first pull-down transistor (Td1) based on the gate base voltage (GVSS).

If the second pull-up transistor (Tu2) is turned on, the second pull-down transistor (Td2) can be turned off. At this time, a sense signal (SENSE) having a turn-on level voltage section (eg, high level gate voltage section) can be output through the second pull-up transistor (Tu2) based on the sense clock signal (SE_CLK (n)). .. Here, the sense signal (SENSE) can have a turn-on level voltage section shifted by a sense shift time (tSHIFT / SEN) from the turn-on level voltage section of the scan signal (SCAN).

If the second pull-up transistor (Tu2) is turned off, the second pull-down transistor (Td2) can be turned on. At this time, a sense signal (SENSE) having a turn-off level voltage section (eg, low level gate voltage section) can be output through the second pull-down transistor (Td2) based on the gate base voltage (GVSS).

If the third pull-up transistor (Tu3) is turned on, the third pull-down transistor (Td3) can be turned off. At this time, a carry signal (CR (n)) having a turn-on level voltage section (eg, high level gate voltage section) based on the carry clock signal (CR_CLK (n)) through the third pull-up transistor (Tu3). Can be output.

If the third pull-up transistor (Tu3) is turned off, the third pull-down transistor (Td3) can be turned on. At this time, a carry signal (CR (n)) having a turn-off level voltage section (eg, low level gate voltage section) can be output through the third pull-down transistor (Td3) based on the gate base voltage (GVSS). ..

As illustrated in FIG. 23, the carry signal (CR (n)) may have the same signal change timing as the scan signal (SCAN).

On the other hand, the level shifter circuit 2210 included in the gate drive circuit 2200 can be realized by one integrated circuit chip.

The gate signal output unit 2220 included in the gate drive circuit 2200 can also be embodied by one or more integrated circuit chips.

Alternatively, the gate signal output unit 2220 included in the gate drive circuit 2200 can be realized by a GIP (Gate In Panel) type. In this case, the gate signal output unit 2220 hides the display panel 110 on which the scan signal line (SCL) to which the scan signal (SCAN) is applied and the sense signal line (SENL) to which the sense signal (SENSE) is applied are arranged. Can be placed in the area.

The gate drive circuit 2200 of FIG. 22 may be a circuit embodied including the first gate drive circuit 130 and the second gate drive circuit 140 of FIG.

According to the embodiment of the present invention described above, the image quality can be improved by improving the charging rate through the overlapping drive of the subpixel SP.

Further, according to the embodiment of the present invention, the image is displayed through the fake data insertion drive for inserting a fake image (eg, black image, low gradation image, etc.) different from the actual image in the middle of displaying the actual image. It is possible to improve the image quality by preventing the phenomenon of blurring and the phenomenon of brightness difference for each sub-pixel line without being classified.

Further, according to the embodiment of the present invention, even if the fake data insertion drive is advanced during the overlap drive, the sense signal (SENSE) out of the two gate signals (scan signal (SCAN) and sense signal (SENSE)) ) Turn-on level voltage section is controlled to be delayed from the turn-on level voltage section of the scan signal (SCAN). Through the advanced overlap drive, the overlap drive characteristics do not change immediately before the fake data insertion drive. Can be controlled as

As a result, when the fake data insertion drive proceeds during the overlap drive, an image abnormality phenomenon (eg, the 4th, 8th subpixel row, etc.) that occurs immediately before the fake data insertion drive (eg, 4th, 8th subpixel row, etc.) occurs. : Specific line bright phenomenon) can be prevented.

Further, in the embodiment of the present invention, the advanced overlap drive is performed by increasing the ratio (Ws / Ls) of the channel width (Ws) to the channel length (Ls) of the sense transistor SENT. It can compensate for the reduced charging time.

The above description is merely an exemplary explanation of the technical idea of the present invention, and any person who has ordinary knowledge in the technical field to which the present invention belongs can view the essential characteristics of the present invention. Various modifications and modifications are possible within the range that does not come off. Further, since the embodiments disclosed in the present invention are not for limiting the technical idea of the present invention but for explaining the technical idea, the scope of the technical idea of the present invention is limited by such an embodiment. It is not. The scope of protection of the present invention must be construed according to the claims, and all technical ideas within the equivalent scope should be construed as being included in the scope of rights of the present invention.

100 Display device 110 Display panel 120 Data drive circuit 130 1st gate drive circuit 140 2nd gate drive circuit 150 Controller

Claims (20)

In the gate drive circuit
A scan clock signal generator that receives inputs from the first reference scan clock signal and the second reference scan clock signal, generates a scan clock signal, and outputs the scan clock signal.
A sense clock signal generator that receives the inputs of the first reference sense clock signal and the second reference sense clock signal, generates a sense clock signal, and outputs the sense clock signal.
A gate signal output unit that outputs a scan signal having a turn-on level voltage section based on the scan clock signal and outputs a sense signal having a turn-on level voltage section based on the sense clock signal is included.
After the first reference scan clock signal is rising and falling, the second reference scan clock signal is rising and falling.
After the first reference sense clock signal is rising and falling, the second reference sense clock signal is rising and falling.
The high level gate voltage section of the sense clock signal is delayed by a preset sense shift time as compared with the high level gate voltage section of the scan clock signal.
The turn-on level voltage section of the sense signal is a gate drive circuit delayed by the sense shift time as compared with the turn-on level voltage section of the scan signal. The scan clock signal generation unit
The scan clock signal that is raised at the rising timing of the first reference scan clock signal and falls at the falling timing of the second reference scan clock signal is generated and output.
The sense clock signal generation unit
It is not raised at the rising timing of the first reference sense clock signal, but is raised at the rising timing of the second reference sense clock signal, and a preset delay time is set after the falling timing of the second reference sense clock signal. The sense clock signal that is subsequently dropped is generated and output, and then
The gate drive circuit according to claim 1, wherein the time interval between the rising timing of the first reference sense clock signal and the rising timing of the second reference sense clock signal corresponds to the sense shift time. The rising timing of the first reference sense clock signal is the same as the rising timing of the first reference scan clock signal.
The gate drive circuit according to claim 2, wherein the rising timing of the second reference sense clock signal precedes the rising timing of the second reference scan clock signal. The length of the superimposition time between the scan clock signal and the sense clock signal is
The gate drive circuit according to claim 2, which corresponds to a value obtained by subtracting the delay time from the temporal length of the turn-on level voltage section of the sense signal. The scan clock signal generation unit
Upon receiving the input of the first reference scan clock signal and the second reference scan clock signal, it is raised to the rising timing of the first reference scan clock signal and fallen to the falling timing of the second reference scan clock signal. The scan logic unit that generates the scan clock signal and
Includes a scan level shifter that outputs the scan clock signal that is rising to a high level gate voltage and falling to a low level gate voltage.
The sense clock signal generation unit
Upon receiving the input of the first reference sense clock signal and the second reference sense clock signal, the rise timing is not the rising timing of the first reference sense clock signal, but the rising timing of the second reference sense clock signal. A sense logic unit that generates the sense clock signal that falls after a preset delay time after the falling timing of the second reference sense clock signal.
A delayer that delays the rising timing of the sense clock signal so that the sense clock signal is not raised at the rising timing of the first reference sense clock signal but is raised at the rising timing of the second reference sense clock signal.
The sense clock having a high level gate voltage section that is raised to the high level gate voltage, falls to the low level gate voltage, and is delayed by the sense shift time with respect to the high level gate voltage section of the scan clock signal. A gate drive circuit that includes a sense level shifter that outputs a signal. The gate drive circuit according to claim 5, wherein the delayer includes one or more resistance elements. The gate drive circuit according to claim 1, further comprising a carry clock signal generation unit that receives inputs of a first reference carry clock signal and a second reference scan clock signal to generate and output a carry clock signal. It comprises a plurality of data lines, a plurality of scan signal lines, a plurality of sense signal lines, a plurality of reference lines, and a plurality of subpixels, each of the plurality of subpixels for driving a light emitting element and the light emitting element. Drive transistor, scan transistor that controls the connection between the data line and the first node of the drive transistor by a scan signal, and connection between the reference line and the second node of the drive transistor by a sense signal. A display panel including a sense transistor for controlling the drive transistor and a capacitor connected between the first node and the second node of the drive transistor.
A data drive circuit for driving the plurality of data lines and
A first scan signal having a turn-on level voltage section is supplied to a first scan signal line electrically connected to a gate node of the scan transistor in the first subpixel included in the plurality of subpixels. 1st gate drive circuit and
Only a preset sense shift time compared to the turn-on level voltage section of the first scan signal on the first sense signal line electrically connected to the gate node of the sense transistor in the first subpixel. A display device comprising a second gate drive circuit that supplies a first sense signal with a delayed turn-on-level voltage section. The turn-on level voltage section of the first sense signal is
The display device according to claim 8, further comprising a period of superimposition with the turn-on level voltage section of the first scan signal and a period of non-superimposition with the turn-on level voltage section of the first scan signal. The period during which the turn-on level voltage section of the first sense signal and the turn-on level voltage section of the first scan signal are superimposed is
The display device according to claim 8, which corresponds to a programming period in which video data is programmed in the first subpixel. The start time of the turn-on level voltage section of the first sense signal is delayed by the sense shift time from the start time of the turn-on level voltage section of the first scan signal.
The display device according to claim 8, wherein the sense shift time is a time corresponding to 1/2 of the turn-on level voltage section of the first scan signal. The plurality of subpixels further include a second subpixel and a third subpixel.
The drain node or source node of the sense transistor contained in each of the first subpixel, the second subpixel, and the third subpixel is electrically connected to the same reference line.
A second scan signal having a turn-on level voltage is supplied to the gate node of the scan transistor in the second subpixel, and a turn-on level voltage is supplied to the gate node of the sense transistor in the second subpixel. While the second sense signal is being supplied
The display device according to claim 8, wherein there is a timing at which the sense transistor in the first subpixel and the sense transistor in the third subpixel are simultaneously turned off. Of the plurality of scan signal lines, the period during which a scan signal having a turn-on level voltage is supplied to the i (i is a natural number of 1 or more) th scan signal line, and
During the period during which the scan signal having the turn-on level voltage is supplied to the (i + 1) th scan signal line among the plurality of scan signal lines.
The display device according to claim 8, wherein a fake data voltage that is distinguished from the actual video data voltage is supplied to the subpixels arranged in k (k is a natural number of 1 or more) subpixel lines. The plurality of subpixels further include a second scan signal line that transmits a second scan signal and a second subpixel that is connected to a second sense signal line that transmits a second sense signal.
The turn-on level voltage section of the first sense signal is delayed by the sense shift time from the turn-on level voltage section of the first scan signal, and the turn-on level voltage section of the first sense signal is the first. Superimposes the scan signal turn-on level voltage interval for a preset programming period.
The turn-on level voltage section of the second sense signal is delayed by the sense shift time from the turn-on level voltage section of the second scan signal, and the turn-on level voltage section of the second sense signal is the second. The turn-on level voltage section of the scan signal is superimposed only during the programming period,
The turn-on-level voltage section of the second scan signal overlaps with the turn-on-level voltage section of the first scan signal, and the turn-on-level voltage section of the second scan signal is the turn-on-level voltage section of the first sense signal. Delayed by a preset scan shift time from the on-level voltage section,
The display device according to claim 8, wherein the turn-on level voltage section of the second sense signal does not overlap with the turn-on level voltage section of the first scan signal. The display device according to claim 13, wherein the fake data voltage is a black data voltage or a low gradation data voltage. The display device according to claim 7, wherein the ratio of the channel width to the channel length of the sense transistor is larger than the ratio of the channel width to the channel length of the scan transistor. Of the plurality of subpixels, the first scan signal line having the turn-on level voltage section is supplied to the first scan signal line connected to the gate node of the scan transistor in the first subpixel, and is supplied to the data line. A step of transmitting the generated video data voltage to the first node of the drive transistor in the first subpixel through the scan transistor, and
The first sense signal line electrically connected to the gate node of the sense transistor in the first subpixel is delayed by a preset sense shift time as compared with the turn-on level voltage section of the first scan signal. A step of supplying a first sense signal having a turned-on-level voltage section and transmitting the reference voltage supplied to the reference line to the second node of the drive transistor through the sense transistor.
A step of supplying the first scan signal having a turn-off level voltage section to the first scan signal line and supplying the first sense signal having a turn-off level voltage section to the first sense signal line. How to drive the display, including. The turn-on level voltage section of the first sense signal is
The period of superimposition with the turn-on level voltage section of the first scan signal and
The method for driving a display device according to claim 17, further comprising a period that does not overlap with the turn-on level voltage section of the first scan signal. The start time of the turn-on level voltage section of the first sense signal is delayed by the sense shift time from the start time of the turn-on level voltage section of the first scan signal.
The method for driving a display device according to claim 17, wherein the sense shift time is a time corresponding to 1/2 of the turn-on level voltage section of the first scan signal. Of the plurality of scan signal lines, the period during which a scan signal having a turn-on level voltage is supplied to the i (i is a natural number of 1 or more) th scan signal line, and
During the period during which a scan signal having a turn-on level voltage is supplied to the (i + 1) th scan signal line among the plurality of scan signal lines.
The drive of the display device according to claim 17, wherein a fake data voltage different from the actual video data voltage is supplied to the subpixels arranged in k (k is a natural number of 1 or more) subpixel lines. Method.

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