KR20230101466A - Gate driving circuit and display device including the same - Google Patents

Abstract

The present invention relates to a display panel capable of preventing a driving margin from being reduced each time shift registers of a gate driving circuit are sequentially driven in a display device including a gate driving circuit (GIP) and a display device including the same. will be.
In order to realize this, the present invention is characterized by arranging two inverter circuits configured by using TFTs having different MOS structures on the input terminal side of each stage in the gate driving circuit of the display panel.
With this structure, the present invention minimizes or hardly generates leakage current by the TFTs of different materials in the signals input to the shift register, thereby preventing the voltage rise of the Q node and thereby preventing the reduction of the driving margin. There are possible effects.

Description

Gate driving circuit and display device including the same

The present invention is a gate driving device capable of preventing a driving margin of each stage from being reduced in a gate shift register of a gate driving circuit that applies a scan signal to a display panel of a display device. It relates to a circuit and a display device including the same.

The display device may include pixels having a light emitting element and a pixel circuit for driving the light emitting element.

For example, the pixel circuit includes a driving transistor that controls a driving current flowing through a light emitting element, and at least one switching transistor that controls (or programs) a gate-source voltage of the driving transistor according to a gate signal (scan signal).

A switching transistor of the pixel circuit may be switched by a gate signal output from a gate driving circuit (eg, GIP) disposed on a substrate of the display panel.

In a display device, a gate driving circuit includes a plurality of stage circuits. Each stage circuit includes a plurality of shift registers for generating gate signals.

In a display device such as a liquid crystal display (LCD) or an organic light emitting display (OLED), a GIP circuit using an output terminal Q node structure structurally controls the voltage of the Q node through a thin film transistor. Based on the thin film transistor, the output side is the Q node, and the input side is the Q1 node.

At this time, the output of the previous stage is used as a clock for the next stage, and the rising gate low voltage (VGL) of the previous stage raises the voltage of the Q1 node of the next stage.

As a result, a leakage current is generated through the thin film transistor, and accordingly, the voltage of the Q node rises, so that the driving margin decreases whenever the shift register operates, resulting in driving failure.

Accordingly, the inventors of the present specification invented a gate driving circuit to prevent driving failure by providing two inverter circuits at the input terminal side of the shift register to prevent leakage current from occurring through the two inverter circuits in order to solve the above-described problem.

In addition, the inventors of the present specification implement the inverter circuit provided on the input side of the gate shift register with a thin film transistor having a different MOS structure, so that leakage current is minimized or hardly generated during low-speed driving, thereby reducing Q Disclosed is a display device including a gate driving circuit that maintains a voltage of a node below a certain level to prevent driving failure.

The above objects of the present invention are not limited to the above-mentioned objects, and other objects and advantages of the present invention not mentioned above can be understood by the following description and will be more clearly understood by the examples of the present invention. will be. It will also be readily apparent that the objects and advantages of the present invention may be realized by means of the instrumentalities and combinations indicated in the claims.

A gate driving circuit according to an embodiment of the present invention may be provided. The gate driving circuit includes a plurality of stages that sequentially output scan signals, and each stage is operated by a clock signal to input an input signal (gate low voltage or gate high voltage), and first invert the input signal. A first inverter unit for inverting the first inverted input signal, a second inverter unit for second inverting the first inverted input signal, a Q node control unit for controlling the voltage of the Q node, a QB node control unit for controlling the voltage of the QB node, and a low level or high level scan It may include an output unit that outputs a signal.

In addition, a display device according to an embodiment of the present invention may be provided. The display device may include a display panel having a plurality of gate lines; It includes a plurality of stages that sequentially output scan signals, and each stage is operated by a clock signal to input an input signal (gate low voltage or gate high voltage), and a first inverter unit that first inverts the input signal. , a second inverter unit that inverts the first inverted input signal a second time, a Q node controller that controls the voltage of the Q node, a QB node controller that controls the voltage of the QB node, and an output that outputs a low level or high level scan signal. a gate driving circuit including a unit; a data driving circuit for applying a data signal to the display panel; and a timing controller controlling the gate driving circuit and the data driving circuit.

According to an embodiment of the present invention, in a display device, a gate driving circuit is disposed on one side of a display panel or a plurality of gate driving circuits are disposed on both sides of a display panel, respectively, and two inverters are provided at an input terminal for the gate driving circuit. It can be configured to include a shift register that

In addition, according to an embodiment of the present invention, the threshold voltage of the thin film transistor (Vth ) does not rise, so there is an effect that leakage current is minimized or hardly generated.

Also, according to an embodiment of the present invention, the effect of the output voltage of the previous stage may be removed by correcting the raised gate low voltage VGL of the previous stage to a gate low voltage VGL having no leakage current.

In addition, according to an embodiment of the present invention, even if the gate low voltage (VGL) rises in the previous stage, it does not affect the GIP circuit, and the gate low voltage (VGL) in which leakage current is minimized or hardly occurs ) is applied to the Q1 node, thereby increasing the driving margin of the GIP.

In addition, according to an embodiment of the present invention, even if the display device operates at a low speed (Low Hz), it is possible to secure a reliability margin by minimizing the effect of the output voltage level of the previous stage in the gate driving circuit.

In addition, according to an embodiment of the present invention, there is an effect of reducing the number of thin film transistors in the shift register of the gate driving circuit, and accordingly, there is an effect of reducing the size (Layout) size (Layout) of the GIP circuit.

Effects of the present specification are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

In addition to the effects described above, specific effects of the present invention will be described together while explaining specific details for carrying out the present invention.

1 is a configuration diagram schematically showing the overall configuration of a display device having a gate shift register according to the present invention.
FIG. 2 is a block diagram of a gate shift register constituting the gate driving circuit shown in FIG. 1 .
3 is a configuration circuit diagram of an arbitrary k-th stage STk in a gate shift register of a gate driving circuit according to an embodiment of the present invention.
4 is a diagram illustrating operation timing signals of a gate driving circuit according to an embodiment of the present invention.
5 is a graph showing a voltage change of a Q node according to a leakage period of a thin film transistor according to an embodiment of the present invention.
6 is a graph showing signal waveforms for each node of a gate driving circuit according to an embodiment of the present invention.
FIG. 7 is a cross-sectional view taken along line AB of FIG. 3 in a second inverter unit of a gate driving circuit according to an embodiment of the present invention.
8 is a cross-sectional view taken along the CD line of FIG. 3 in the second inverter unit of the gate driving circuit according to an embodiment of the present invention.

The above objects, features and advantages will be described later in detail with reference to the accompanying drawings, and accordingly, those skilled in the art to which the present invention belongs will be able to easily implement the technical spirit of the present invention. In describing the present invention, if it is determined that the detailed description of the known technology related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to indicate the same or similar components.

In addition, when a component is described as "connected", "coupled" or "connected" to another component, the components may be directly connected or connected to each other, but other components may be "interposed" between each component. ", or each component may be "connected", "coupled" or "connected" through other components.

Unless otherwise defined, all terms (including technical and scientific terms) used in this specification may be used in a meaning commonly understood by those of ordinary skill in the art to which the present invention belongs. In addition, terms defined in commonly used dictionaries are not interpreted ideally or excessively unless explicitly specifically defined.

Each feature of the various embodiments of the present specification may be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, each embodiment may be implemented independently of each other, and two or more embodiments may be performed together.

In the present specification, the subpixel circuit and the gate driving circuit formed on the substrate of the display panel may be implemented with n-type MOSFET structure transistors, but are not limited thereto and may be implemented with p-type MOSFET structure transistors. A transistor may include a gate, a source, and a drain. In a transistor, carriers can flow from the source to the drain. In the case of an n-type transistor, since electrons are carriers, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. In an n-type transistor, since electrons flow from the source to the drain, the direction of current flows from the drain to the source. In the case of a p-type transistor, since a carrier is a hole, the source voltage has a higher voltage than the drain voltage so that holes can flow from the source to the drain. In a p-type transistor, since holes flow from the source to the drain, the direction of the current flows from the source to the drain. In a transistor with a MOSFET structure, the source and drain are not fixed but can be changed according to the applied voltage. Therefore, in this specification, one of the source and drain is referred to as a first source/drain electrode, and the other one of the source and drain is referred to as a second source/drain electrode.

Hereinafter, a preferred example of a gate driving circuit according to the present specification and a display device including the gate driving circuit will be described in detail with reference to the accompanying drawings. Even if shown on different figures, the same components may have the same reference numerals. In addition, since the scales of the components shown in the accompanying drawings have different scales from actual ones for convenience of explanation, they are not limited to the scales shown in the drawings.

Hereinafter, a gate driving circuit according to an embodiment of the present specification and a display device including the gate driving circuit will be described.

FIG. 1 is a schematic diagram showing the overall configuration of a display device having a gate shift register according to the present invention, and FIG. 2 is a configuration diagram of a gate shift register constituting the gate driving circuit shown in FIG. 1 .

Referring to FIG. 1 , a display device 100 according to an exemplary embodiment of the present invention may include a display panel 120, a gate driving circuit 140, a data driving circuit 160, and a timing controller 180. .

The display panel 120 may include an OLED panel for displaying an image by emitting light through an organic light emitting diode (OLED) device or a liquid crystal panel for displaying an image using a liquid crystal (LCD) device.

In the display panel 120 , a plurality of gate lines GL and a plurality of data lines DL may intersect in a matrix form on a substrate using glass, and a plurality of pixels P may be defined at the crossing points.

Each pixel P displays an image according to an image signal (data voltage) supplied from the data line DL in response to a scan signal supplied from the gate line GL.

A thin film transistor (TFT) and a storage capacitor (Cst) are provided in each pixel (P), all pixels form one display area (A/A), and the area where pixels are not defined is a non-display area (N/A). ) can be distinguished.

The display panel 120 may include a plurality of pixels P defined in each crossing area of the gate lines GL and data lines DL. Each of the plurality of pixels P according to an example may be a red pixel, a green pixel, or a blue pixel. In this case, adjacent red pixels, green pixels, and blue pixels may implement one unit pixel. Each of the plurality of pixels P according to another example may be a red pixel, a green pixel, a blue pixel, or a white pixel. In this case, adjacent red pixels, green pixels, blue pixels, and white pixels may implement one unit pixel for displaying one color image.

Also, the display panel 120 may include a display area A/A, a non-display area N/A, and a bending area.

The display area A/A may include a plurality of gate lines GL, a plurality of data lines DL, a plurality of reference lines (not shown), and a plurality of pixels P.

The display mode of the display panel 120 may be a drive for sequentially displaying an input image having a predetermined time difference and a black image on a plurality of horizontal lines. The display mode according to an example may include an image display period (or emission display period) displaying an input image and a black display period (or impulse non-emission period) displaying a black image.

The sensing mode (or real-time sensing mode) of the display panel 120 may sense the driving characteristics of pixels P disposed on any one horizontal line among a plurality of horizontal lines after an image display period within one frame.

Further, the sensing mode may be a real-time sensing drive for updating a compensation value for each pixel for compensating for a change in driving characteristics of corresponding pixels P based on the sensing value.

The sensing mode according to an example may sense driving characteristics of pixels P disposed on any one horizontal line among a plurality of horizontal lines in an irregular order within a vertical blank section of each frame.

Since the pixels P that emit light according to the display mode do not emit light in the sensing mode, when horizontal lines are sequentially sensed in the sensing mode, a line dim phenomenon may occur in the sensed horizontal lines due to non-emission. can On the other hand, when horizontal lines are sensed in an irregular or random order in the sensing mode, line dimming can be minimized or prevented due to a visual dispersion effect.

The gate driving circuit 140 may be implemented as, for example, a gate in panel (GIP) type gate driver. The gate driving circuit 140 may be disposed in a non-display area of the display panel 120 .

The gate driving circuit 140 is a gate shift register that supplies scan signals (gate signals) to a plurality of gate lines GL according to a plurality of gate control signals GCS provided from the timing controller 180. consists of

The plurality of gate control signals GCS includes a plurality of clock signals CLK1 to 4 having different phases and a gate start signal VST instructing the gate driving circuit 140 to start driving. The gate shift register will be described later in detail with reference to FIG. 2 .

The data driving circuit 160 converts the digital image data RGB input from the timing controller 180 into data voltages using the reference gamma voltage, and supplies the converted data voltages to a plurality of data lines DL. The data driving circuit 160 is controlled according to a plurality of data control signals DCS provided from the timing controller 180 .

That is, the data driving circuit 160 selectively converts modulated image data (RGBv) in digital form corresponding to the data control signal (DCS) input from the timing controller 180 into analog form according to the reference voltage (Vref). It can be converted into data voltage (VDATA) and provided. The data voltage VDATA is latched one by one horizontal line, and can be simultaneously input to the display panel 120 through all the data lines DL during one horizontal period 1H.

The timing controller 180 transmits timing signals such as an image signal (RGB) transmitted from an external system, a clock signal (CLK), a horizontal synchronization signal (Hsync), a vertical synchronization signal (Vsync), and a data enable signal (DE). control signals of the data driving circuit 140 and the gate driving circuit 140 may be generated.

Here, the horizontal synchronization signal Hsync is a signal representing the time required to display one horizontal line on the screen, and the vertical synchronization signal Vsync is a signal representing the time required to display one frame of the screen. Also, the data enable signal DE is a signal indicating a period for supplying data voltages to pixels P defined on the display panel 120 .

Also, the timing controller 180 may generate the gate control signal GCS of the gate driving circuit 140 and the data control signal DCS of the data driving circuit 160 in synchronization with the input timing signal.

In addition, the timing controller 180 may generate a plurality of clock signals (CLK 1 to CLK 4 ) for determining the driving timing of each stage of the gate driving circuit 140 and provide them to the gate driving circuit 140 . Here, the first to fourth clock signals CLK 1 to CLK 4 are signals in which a high period progresses for 2 horizontal periods (2H), and one horizontal period (1H) overlaps with each other.

In addition, the timing controller 180 may align and modulate the received image data (RGB DATA) in a form processable by the data driving circuit 160 and output the same. Here, the sorted image data RGBv may have a form to which a color coordinate correction algorithm for image quality improvement is applied.

Meanwhile, the gate driving circuit 140 may supply a scan signal to each gate line GL.

The gate driving circuit 140 may include a first gate driving unit and a second gate driving unit when disposed at both left and right ends of the display panel 120 , respectively.

In the gate driving circuit 140 , a first gate driving unit and two second gate driving units may be disposed in the non-display area N/A at both ends of the display panel 120 .

For example, the first gate driver may be disposed on one side (left side) of the display panel 120 and the second gate driver may be disposed on the other side (right side) of the display panel 120 .

At this time, in the gate driving circuit 140, the odd output lines of the first gate driver are connected to the even output lines of the second gate driver, and the even output lines of the first gate driver are connected to each other. It may have a structure connected to odd output lines of the second gate driver.

Each gate driving circuit 140 may include at least one stage including a shift register, that is, a plurality of stages. When the substrate of the display panel 120 is manufactured, the gate driving circuit 140 may be embedded in the non-display area in a gate-in-panel (GIP) method in the form of a thin film pattern.

The gate driving circuit 140 alternates every two horizontal periods (2H) through a plurality of gate lines (GL) formed in the display panel 120 in response to the gate control signal (GCS) input from the timing controller 180. A gate high voltage (VGH) can be output. Here, the output gate high voltage VGH may be maintained for two horizontal periods (2H), and the front and rear gate high voltages (VGH) may overlap for one horizontal period (1H). This is for pre-charging the gate line GL, and more stable pixel charging can be performed when the data voltage is applied.

To this end, the first and third clock signals CLK1 and CLK3 each having two horizontal periods (2H) are applied to the first gate driver, and the first and third clock signals CLK1 and CLK3 are applied to the second gate driver. and 1 horizontal period 1H overlap, and the second and fourth clock signals CLK2 and CLK4 having 2 horizontal periods 2H may be applied.

For example, when the first gate driver outputs the gate high voltage VGH to the n-th gate line GLn, the second gate driver outputs the n+1-th gate line GLn+1 after 1 horizontal period 1H. to output a gate high voltage (VGH).

Next, when the first gate driver outputs the gate high voltage (VGH) to the n+2 th gate line (GLn+2) again after 1 horizontal period (1H), the first gate driver simultaneously outputs the n th gate line ( By outputting the gate low voltage (VGL) to GLn to turn off the thin film transistor (TFT), the data voltage charged in the storage capacitor (Cst) can be maintained for one frame.

In particular, the embodiment of the present specification further includes a discharge circuit when the voltage of the gate line GL is converted from the gate high voltage VGH to the low voltage VGL to minimize the discharge delay of the gate line GL. can

The above-described discharge circuit is connected to the end corresponding to each gate line GL, and the R discharge circuit connected to odd-numbered gate lines is provided adjacent to the second gate driver and L discharge connected to even-numbered gate lines. The circuit may be disposed adjacent to the first gate driver.

Here, each discharge circuit may be connected to the second and subsequent lines of one gate line GL to apply the gate low voltage VGL to the corresponding gate line GL.

Since the discharge circuit is formed as a thin film transistor between each stage constituting the gate driving circuit 140, the area occupied by each gate driving circuit in the non-display area N/A of the display panel 120 is reduced with a narrow bezel. (narrow bezel) can be implemented.

Referring to FIG. 2 , a gate driving circuit 140 according to an embodiment of the present invention is composed of a gate shift register, and the gate shift register may include a plurality of stages ST1 , ST2 , STn connected in cascade. there is.

A plurality of stages (ST) are selectively connected to lines supplied with a plurality of clock signals (CLK1-4) to sequentially output scan pulses (G; G1, G2, G3, ...) serving as gate signals. can

Specifically, each of the plurality of stages ST receives at least one selected from a plurality of clock signals CLK1-4, a gate-on voltage VGL, a gate-off voltage VGH, and a blank signal BS. can

The plurality of clock signals CLK1 - 4 may include 4-phase clock signals, that is, first to fourth clock signals CLK1 - 4 shifted and output at regular intervals. The first to fourth clock signals CLK1-4 are selected three by one and supplied for each stage ST. For example, the first, third, and fourth clock signals CLK1, 3, and 4 are supplied to the 4k-3 (k is a natural number)-th stages ST1, ST5, ST9, .... The second, fourth, and first clock signals CLK2, 4, and 1 are supplied to the 4k-2th stages ST2, ST6, ST10, .... The third, first, and second clock signals CLK3, 1, and 2 are supplied to the 4k−1th stages ST3, ST7, ST11, .... The fourth, second, and third clock signals CLK4, 2, and 3 are supplied to the 4k-th stages ST4, ST8, ST12, ....

The blank signal BS is a signal provided in the blank period and may be a source output enable signal SOE provided from the timing controller 180 . Here, the blank period is a period set after the scan period in which the scan pulse G is output once from the plurality of stages ST.

In particular, the gate shift register of the present invention uses the blank signal (BS) provided in the blank period to set the voltage of the QB node connected to the gate electrode of the pull-down transistor provided in each stage (ST) to the gate-off voltage (VGH). charge with Accordingly, the present invention can improve driving reliability by preventing malfunction of the pull-down transistor PD due to leakage current of the QB node and resulting multi-output.

Meanwhile, although not shown in FIG. 2 , the gate shift register according to an embodiment of the present invention includes a previous dummy stage circuit unit at the front of the first stage ST1 and a rear dummy stage circuit unit at the rear stage of the nth stage STn. can include

The gate driving circuit 140 may receive the gate control signal GCS through the gate control signal line. That is, the gate control signal line receives the gate control signal GCS supplied from the timing controller 180 . Gate control signal lines according to an example may include a gate start signal line, a first reset signal line, a second reset signal line, a plurality of gate driving clock lines, a display panel on signal line, and a sensing preparation signal line.

The gate start signal line may receive the gate start signal VST supplied from the timing controller 180 . For example, the gate start signal line may be connected to the previous dummy stage circuitry.

The first reset signal line may receive the first reset signal supplied from the timing controller 180 . The second reset signal line may receive the second reset signal supplied from the timing controller 180 . For example, each of the first and second reset signal lines may be commonly connected to the previous dummy stage circuit unit, the first to m th stage circuits ST1 to STm, and the next dummy stage circuit unit.

The plurality of gate driving clock lines include a plurality of carry clock lines, a plurality of scan clock lines receiving the plurality of carry shift clocks, the plurality of scan shift clocks, and the plurality of sense shift clocks supplied from the timing controller 180, respectively; and A plurality of sense clock lines may be included. Clock lines included in the plurality of gate driving clock lines may be selectively connected to the previous dummy stage circuit unit, the first to m th stage circuits ST1 to STm, and the next dummy stage circuit unit.

The display panel on signal line may receive the display panel on signal supplied from the timing controller 180 . For example, the display panel on signal line may be commonly connected to the previous dummy stage circuit unit and the first to m th stage circuits ST1 to STm.

The sensing preparation signal line may receive the line sensing preparation signal supplied from the timing controller 180 . For example, the sensing preparation signal line may be commonly connected to the first to m th stage circuits ST1 to STm. Optionally, the sensing ready signal line may be further connected to the previous dummy stage circuitry.

The gate driving voltage line includes first to fourth gate high potential voltage lines receiving first to fourth gate high potential voltages having different voltage levels from the power supply circuit and different voltage levels from the power supply circuit. It may include first to third gate low potential voltage lines for receiving the first to third gate low potential voltages, respectively.

According to an example, the first gate high potential voltage may have a higher voltage level than the second gate high potential voltage. The third and fourth gate high potential voltages may swing opposite to each other or invert each other between a high voltage (or TFT on voltage or first voltage) and a low voltage (or TFT off voltage or second voltage) for AC driving. . For example, when the third gate high potential voltage (or gate odd high potential voltage) has a high voltage, the fourth gate high potential voltage (or gate even high potential voltage) may have a low voltage. Also, when the third gate high potential voltage has a low voltage, the fourth gate high potential voltage may have a high voltage.

Each of the first and second gate high-potential voltage lines may be commonly connected to the first to m-th stage circuits ST1 to STm, the previous dummy stage circuit unit, and the next dummy stage circuit unit.

The third gate high-potential voltage line may be commonly connected to odd-numbered stage circuits among the first to m-th stage circuits ST1 to STm, and is common to odd-numbered dummy stage circuits of each of the previous dummy stage circuit unit and the subsequent dummy stage circuit unit. can be connected to

The fourth gate high-potential voltage line may be commonly connected to even-numbered stage circuits among the first to m-th stage circuits ST1 to STm, and is common to even-numbered dummy stage circuits of each of the previous dummy stage circuit unit and the subsequent dummy stage circuit unit. can be connected to

According to an example, the first gate low potential voltage and the second gate low potential voltage may have substantially the same voltage level. The third gate low potential voltage may have a TFT off voltage level. The first gate low potential voltage may have a higher voltage level than the third gate low potential voltage. An example of the present specification is to set the first gate low potential voltage to a higher voltage level than the third gate low potential voltage to reliably cut off the off current of a TFT having a gate electrode connected to a control node of a stage circuit to be described later, thereby reducing the corresponding TFT The stability and reliability of the operation of can be secured.

The first to third gate low potential voltage lines may be commonly connected to the first to m th stage circuits ST1 to STm.

The previous dummy stage circuit unit may sequentially generate a plurality of previous stage carry signals in response to the gate start signal VST supplied from the timing controller 180 and supply them to one of the subsequent stages as the previous stage carry signal or gate start signal. .

The next dummy stage circuit unit may sequentially generate a plurality of rear stage carry signals and supply the next stage carry signal (or stage reset signal) to any one of the previous stages.

The first to m th stage circuits ST1 to STm may be dependently connected to each other. The first to m-th stage circuits ST1 to STm generate the first to m-th scan signals SC1 to SCm and the first to m-th sense signals SE1 to SEm to generate corresponding circuits disposed on the display panel 120. It can be output through the gate line GL. In addition, the first to m th stage circuits ST1 to STm generate the first to m th carry signals CS1 to CSm and supply them to one of the subsequent stages as a previous stage carry signal (or gate start signal), A carry signal (or a stage reset signal) may be supplied to any one of the previous stages.

The first to m th stage circuits ST1 to STm may share a part of the sensing control circuit and a control node between two adjacent stages, thereby simplifying the circuit configuration of the gate driving circuit 140. , the area occupied by the gate driving circuit 140 in the display panel 120 may be reduced.

3 is a configuration circuit diagram of an arbitrary k-th stage STk in a gate shift register of a gate driving circuit according to an embodiment of the present invention.

Referring to FIG. 3 , in the gate shift register according to an embodiment of the present invention, the k-th stage STk includes an input unit 305, a first inverter unit 310, a second inverter unit 320, and a Q node control unit ( 330), a QB node control unit 340 and an output unit 350.

The input unit 305 is operated by one clock signal GCLK1 among a plurality of clock signals CLK1-4 and inputs a gate-on signal VGL or a gate-off signal VGH to the second node Q2. can

The first inverter unit 310 is operated by the start signal GVST and outputs a gate-on signal VGL or gate-off signal VGH opposite to the level of the start signal to the input unit 305 .

The second inverter unit 320 is operated by the gate-on signal VGL or gate-off signal VGH, and generates a gate-off signal or gate-on signal opposite to the gate-on signal VGL or gate-off signal VGH. It can be output to the first node (Q1).

The Q node controller 330 is operated by the gate-on signal VGL, and may apply the gate-on signal VGL of the first node Q1 to the Q node.

The QB node controller 340 is operated by the gate-off signal VGH of the first node Q1 and may apply the gate-off signal VGH to the QB node.

The output unit 350 may output the gate-on signal VGL of the Q node to an output terminal or output the gate-off signal VGH of the QB node to an output terminal.

Here, the first inverter unit 310 and the second inverter unit 320 may connect two transistors T6A and T6B or T6C and T6D each having a different MOS structure.

For example, the first inverter unit 310 may be configured by connecting the 6C transistor T6C and the 6D transistor T6D. In this case, the 6C transistor T6C may have an N-type MOS structure, and the 6D transistor T6D may have a P-type MOS structure.

The 6C transistor T6C may have a gate electrode connected to the start signal line GVST, a first electrode connected to the gate-on signal line VGL, and a second electrode connected to the third node Q3.

The 6D transistor T6D may have a gate electrode connected to the start signal line GVST, a first electrode connected to the third node Q3, and a second electrode connected to the gate off signal line VHL.

Also, the 6C transistor T6C may be an oxide TFT, and the 6D transistor T6D may be a low temperature polysilicon thin film transistor (LTPS TFT).

Also, the second inverter unit 320 may be configured by connecting the 6A transistor T6A and the 6B transistor T6B. In this case, the 6A transistor T6A may have an N-type MOS structure, and the 6B transistor T6B may have a P-type MOS structure.

The 6A transistor T6A may have a gate electrode connected to the second node Q2, a first electrode connected to the gate on signal VGL line, and a second electrode connected to the first node Q1. The 6B transistor T6B has a gate electrode connected to the second node Q2, a first electrode connected to the first node Q1, and a second electrode connected to the gate off signal VHL line.

The 6A transistor T6A may be an oxide TFT, and the 6B transistor T6B may be a low temperature polysilicon thin film transistor (LTPS TFT).

4 is a diagram illustrating operation timing signals of a gate driving circuit according to an embodiment of the present invention.

Referring to FIG. 4 , it can be seen that in the gate driving circuit 140 according to an embodiment of the present invention, the first clock signal GCLK1 in a low level state is generated three times during a period in which the start signal GVST is at a high level. there is.

In addition, it can be seen that the gate driving circuit 140 generates the low level second clock signal GCLK2 twice while the start signal GVST is at the high level.

In addition, the gate driving circuit 140 may know that the nth scan signal SCAN(n) is also at a high level during the same period while the start signal GVST is at a high level.

The n+1th scan signal SCAN(n+1) becomes a high signal when the second clock signal GCLK2 is at a low level, and becomes a low level when the second clock signal GCLK2 is at a low level twice. is converted

The n+2 scan signal SCAN(n+2) becomes a high signal when the first clock signal GCLK1 is at a low level, and becomes a low level when the first clock signal GCLK1 is at a low level twice. is converted

The n+3 scan signal SCAN(n+3) becomes a high signal when the second clock signal GCLK2 is at a low level, and becomes a low level when the second clock signal GCLK2 is at a low level twice. is converted

5 is a graph showing a voltage change of a Q node according to a leakage period of a thin film transistor according to an embodiment of the present invention.

In the gate driving circuit 140 according to an embodiment of the present invention, when the start signal GVST is at a low level, the 6D thin film transistor T6D of the first inverter unit 310 is turned on.

At this time, when the first clock signal GCLK1 is at a low level, the third thin film transistor T3 is also turned on.

Accordingly, the gate high signal VGH is applied from the 6D thin film transistor T6D to the second node Q2 via the third thin film transistor T3.

Subsequently, the 6A thin film transistor T6A of the second inverter unit 320 is turned on, and the gate low signal VGL is applied to the first node Q1.

Accordingly, as the TA thin film transistor TA of the Q node controller 330 is turned on, the gate low signal VGL is applied from the first node Q1 to the Q node.

Referring to FIG. 5 , as the gate low signal VGL is applied to the Q node, the first thin film transistor T1 of the output unit 350 is turned on, and the gate low signal VGL is sent to the output terminal (Output). output

At this time, it can be seen that the voltage of the Q node, that is, the gate-source voltage (Vgs) of the first thin film transistor (T1) rises to T1Vgs for 1 second (s).

6 is a graph showing signal waveforms for each node of a gate driving circuit according to an embodiment of the present invention.

In the gate driving circuit 140 according to an embodiment of the present invention, when the start signal GVST is at a high level, the 6C thin film transistor T6C of the first inverter unit 310 is turned on.

Accordingly, the gate low signal VGL is applied to the third node Q3 through the 6th thin film transistor T6C. Accordingly, the third node Q3 becomes a low level state during a period in which the start signal GVST is at a high level.

At this time, when the first clock signal GCLK1 is applied at a low level to the third thin film transistor T3, the third thin film transistor T3 is turned on, and the low level signal of the third node Q3 is applied to the second node ( Q2), the second node Q2 also becomes a low level state.

When the second node Q2 is at a low level, the 6B thin film transistor T6B is turned on and the gate high signal VGH is applied to the first node Q1, so that the first node Q1 has a high level become a state

At this time, the first node Q1 is in a high level state, and is converted to a low level state at the moment when the start signal GVST becomes a low level state.

That is, the 6D thin film transistor T6D is turned on by the low-level start signal GVST, and accordingly, the gate high signal VGH is applied to the third node Q3 from the 6D thin film transistor T6D.

When the low level first clock signal GCLK1 is applied to the third thin film transistor T3, the third thin film transistor T3 is turned on and the high level gate high signal VGH of the third node Q3 is applied. When applied to the second node Q2, the second node Q2 becomes a high level state.

When the second node Q2 is in a high level state, the 6A thin film transistor T6A is turned on, and accordingly, the low level gate low signal VGL is applied to the first node Q1, so that the first node ( Q1) becomes a low level state.

Here, fine pulse signals of ripple components are generated at regular intervals when the first node Q1' corresponding to the prior art before the present invention is applied is in a low level state. The fine pulse signal of the ripple component generates a leakage current through the TA thin film transistor (TA) and is applied to the Q node so that the voltage of the Q node rises.

However, in the gate driving circuit 140 according to the present invention, the start signal GVST is applied to the 6C thin film transistor T6C of the N-MOS structure of the first inverter unit 310 and the N-MOS structure of the second inverter unit 320. As shown in FIG. 6 via the 6A thin film transistor T6A of the structure, pulse signals of ripple components are not generated in the low level signal of the first node Q1.

Therefore, as the driving operation of the gate shift registers progresses, leakage current through the TA thin film transistor is not generated for each gate shift register, and thus the driving margin can be prevented from decreasing.

7 is a cross-sectional view taken along the line A-B of FIG. 3 in the second inverter unit of the gate driving circuit according to an embodiment of the present invention.

Referring to FIG. 7 , the second inverter unit 320 according to an embodiment of the present invention connects a 6A thin film transistor T6A of an N-MOS structure and a 6B thin film transistor T6B of a P-MOS structure. made in one form.

Here, the 6A transistor T6A may be implemented as an oxide TFT, and the 6B transistor T6B may be implemented as a low temperature poly silicon thin film transistor (LTPS TFT).

The 6th A transistor T6A includes a buffer film BUF over the substrate SUB; a gate insulating layer (GI) over the buffer layer; an interlayer insulating film (ILD) over the gate insulating film; A bottom gate electrode BGAT may be disposed on the interlayer insulating layer.

In addition, the 6th A transistor T6A may include a second interlayer insulating film ILD2 over the bottom gate electrode BGAT; an oxide active layer (OACT) on the second interlayer insulating layer; An oxide organic light emitting layer (OEL) may be disposed on the oxide active layer.

In addition, the 6th A transistor T6A may include an oxide gate electrode OGAT on the oxide organic light emitting film OEL; an oxide interlayer dielectric (OILD) on the oxide gate electrode; A second node Q2 line may be disposed on the oxide interlayer insulating layer.

In this case, the second node Q2 line may be electrically connected to the oxide gate electrode OGAT through the first contact hole.

In addition, in the 6A transistor T6A, the gate-on signal VGL line is disposed on the oxide interlayer insulating film OILD, and the gate-on signal VGL line electrically connects to the oxide active film OACT through the second contact hole. can be connected to

Meanwhile, the 6B transistor T6B according to the present invention includes a buffer film BUF on the substrate SUB; an active layer (ACT) on the buffer layer; a gate insulating layer (GI) over the active layer; A gate electrode GAT may be disposed on the gate insulating layer.

In addition, the 6th B transistor T6B may include an interlayer insulating film ILD over the gate electrode GAT; a second interlayer insulating film ILD2 over the interlayer insulating film; An oxide organic light emitting layer (OEL) may be disposed on the second interlayer insulating layer.

In addition, the 6th B transistor T6B may include an oxide interlayer insulating film OILD over the oxide organic light emitting film OEL; A second node Q2 line may be disposed on the oxide interlayer insulating layer.

Here, the second node Q2 line is electrically connected to the gate electrode GAT through the fourth contact hole, and the gate off signal VGH line is electrically connected to the active layer ACT through the fifth contact hole. can

At this time, the 6A transistor T6A and the 6B transistor T6B have an N2 node electrically connected to the oxide active film OACT of the 6A thin film transistor T6A through a sixth contact hole, and the 6B transistor It may be electrically connected to the active layer ACT of (T6B).

8 is a cross-sectional view taken along the line C-D of FIG. 3 in the second inverter unit of the gate driving circuit according to an embodiment of the present invention.

Referring to FIG. 8 , the second inverter unit 320 according to an embodiment of the present invention includes a 6A thin film transistor T6A having an N-MOS structure.

Here, the 6th A transistor T6A includes a buffer film BUF over the substrate SUB; a gate insulating layer (GI) over the buffer layer; an interlayer insulating film (ILD) over the gate insulating film; A bottom gate electrode BGAT may be disposed on the interlayer insulating layer.

In addition, the 6th A transistor T6A may include a second interlayer insulating film ILD2 over the bottom gate electrode BGAT; an active layer (ACT) on the second interlayer insulating layer; An oxide organic light emitting layer (OEL) may be disposed on the active layer.

In addition, the 6th A transistor T6A may include an oxide gate electrode OGAT on the oxide organic light emitting film OEL; an oxide interlayer dielectric (OILD) on the oxide gate electrode; A second node Q2 line may be disposed on the oxide interlayer insulating layer.

Here, the second node Q2 line may be electrically connected to the oxide gate electrode OGAT through the first contact hole and electrically connected to the bottom gate electrode BGAT through the third contact hole.

Accordingly, when the 6A transistor T6A is turned on by the high level signal applied from the second node Q2 line, the low level signal from the gate low signal VGL line is passed through the N2 node to the first node. (Q1). At this time, as shown in FIG. 6, the low-level signal does not have a pulse signal of a ripple component, so leakage current does not occur through the TA thin film transistor TA. Accordingly, it is possible to prevent a driving margin from being reduced whenever driving operations of the gate shift registers are performed.

As described above, the display device 100 according to the present invention implements the first inverter unit and the second inverter unit through thin film transistors having a POS structure of different materials at the input of each gate shift register, thereby reducing ripple during low-speed driving. The minute pulse signals of the component are not generated.

Therefore, according to an embodiment of the present invention, it is possible to prevent a driving margin from being reduced whenever driving operations of the gate shift registers of the gate driving circuit 140 are performed.

As described above, according to the present invention, the voltage of the Q node due to the leakage current increases as noise pulse signals are not generated in the low level state of the input signal through the first inverter unit and the second inverter unit for each gate shift register. It is possible to provide a gate driving circuit and a display device including the gate driving circuit that can prevent a driving defect due to a decrease in driving margin.

As described above, the present invention has been described with reference to the drawings illustrated, but the present invention is not limited by the embodiments and drawings disclosed in this specification, and various modifications are made by those skilled in the art within the scope of the technical idea of the present invention. It is obvious that variations can be made. In addition, although the operational effects according to the configuration of the present invention have not been explicitly described and described while describing the embodiments of the present invention, it is natural that the effects predictable by the corresponding configuration should also be recognized.

100: display device 120: display panel
140: gate driving circuit 160: data driving circuit
180: timing controller ST1 to STk: stage
310: first inverter unit 320: second inverter unit
330: Q node control unit 340: QB node control unit
350: output unit SUB: board
BUF: buffer film ILD, ILD2: interlayer insulating film
BGAT: bottom gate electrode ACT: active film
OEL: Oxide organic light emitting film OGAT: Oxide gate electrode
OILD: oxide interlayer insulating film OACT: oxide active film
T1~T3, T5, TA, T6B, T6D : P-MOS TFT
T4, T6A, T6C: N-MOS TFT

Claims (15)

a plurality of stages selectively connected to lines supplied with a plurality of clock signals and sequentially outputting scan signals;
Each of the plurality of stages
an input unit that is operated by one of the plurality of clock signals and inputs a gate-on signal or a gate-off signal to a second node;
a first inverter unit that is operated by a start signal and outputs the gate-on signal or the gate-off signal opposite to the level of the start signal to the input unit;
a second inverter unit operated by the gate-on signal or the gate-off signal and outputting the gate-off signal or the gate-on signal opposite to the gate-on signal or the gate-off signal to a first node;
a Q node control unit that is operated by the gate-on signal and applies the gate-on signal of the first node to a Q node;
a QB node control unit operated by the gate-off signal of the first node and applying the gate-off signal to a QB node; and
an output unit outputting the gate-on signal of the Q node to an output terminal or outputting the gate-off signal of the QB node to an output terminal;
Including, the gate driving circuit.
According to claim 1,
wherein the first inverter unit and the second inverter unit connect two transistors each having a different MOS structure.
According to claim 1,
The first inverter unit,
a 6C transistor having a gate electrode connected to the start signal line, a first electrode connected to the gate-on signal line, and a second electrode connected to a third node; and
a 6D transistor having a gate electrode connected to the start signal line, a first electrode connected to the third node, and a second electrode connected to a gate off signal line;
Including, the gate driving circuit.
According to claim 3,
The gate driving circuit of claim 1 , wherein the 6C transistor has an N-type MOS structure and the 6D transistor has a P-type MOS structure.
According to claim 1,
The second inverter unit,
a 6A transistor having a gate electrode connected to the second node, a first electrode connected to a gate-on signal line, and a second electrode connected to the first node; and
a 6B transistor having a gate electrode connected to the second node, a first electrode connected to the first node, and a second electrode connected to a gate-off signal line;
Including, the gate driving circuit.
According to claim 5,
The 6A transistor has an N-type MOS structure, and the 6B transistor has a P-type MOS structure.
According to claim 5,
The 6A transistor is an oxide TFT, and the 6B transistor is a low temperature poly silicon thin film transistor (LTPS TFT), the gate driving circuit.
According to claim 5,
The 6A transistor may include a buffer film on a substrate; a gate insulating layer over the buffer layer; an interlayer insulating film over the gate insulating film; a bottom gate electrode on the interlayer insulating film; a second interlayer insulating layer on the bottom gate electrode; an oxide active layer on the second interlayer insulating layer; an oxide organic light emitting layer on the oxide active layer; an oxide gate electrode on the oxide organic light emitting layer; an oxide interlayer insulating film on the oxide gate electrode; The second node line is disposed on the oxide interlayer insulating film, the second node line is electrically connected to the oxide gate electrode through a first contact hole, and the gate-on signal line is connected to the oxide gate electrode through a second contact hole. electrically connected to the active layer,
The 6B transistor may include a buffer film on a substrate; an active layer over the buffer layer; a gate insulating layer over the active layer; a gate electrode on the gate insulating layer; an interlayer insulating film on the gate electrode; a second interlayer insulating film over the interlayer insulating film; an oxide organic light emitting layer on the second interlayer insulating layer; an oxide interlayer insulating layer on the oxide organic light emitting layer; The second node line is disposed on the oxide interlayer insulating layer, the second node line is electrically connected to the gate electrode through a fourth contact hole, and the gate off signal line is connected to the active layer through a fifth contact hole. is electrically connected to
Wherein the 6th A transistor and the 6th transistor are electrically connected to the active layer as well as an N2 th node electrically connected to the oxide active layer through a sixth contact hole.
According to claim 5,
The 6A transistor,
a buffer film on the substrate; a gate insulating layer over the buffer layer; an interlayer insulating film over the gate insulating film; a bottom gate electrode on the interlayer insulating film; a second interlayer insulating layer on the bottom gate electrode; an active layer over the second interlayer insulating layer; an oxide organic light emitting layer over the active layer; an oxide gate electrode on the oxide organic light emitting layer; an oxide interlayer insulating film on the oxide gate electrode; The second node line is disposed on the oxide interlayer insulating film, and the second node line is electrically connected to the oxide gate electrode through a first contact hole and electrically connected to the bottom gate electrode through a third contact hole. , the gate driving circuit.
According to claim 1,
The input unit,
a third thin film transistor having a gate electrode connected to a first clock line, a first electrode connected to a third node, and a second electrode connected to the second node;
A gate driving circuit comprising a.
According to claim 1,
The Q node control unit,
a TA thin film transistor having a gate electrode connected to a gate-on signal line, a first electrode connected to the first node, and a second electrode connected to the Q node; and
a fourth thin film transistor having a gate electrode connected to the Q node, a first electrode connected to the gate-on signal line, and a second electrode connected to the QB node;
Including, the gate driving circuit.
According to claim 1,
The QB node control unit,
a fifth thin film transistor having a gate electrode connected to the first node, a first electrode connected to the QB node, and a second electrode connected to the gate off signal line and the output unit;
Including, the gate driving circuit.
According to claim 1,
the output unit,
a pull-up transistor outputting the scan pulse to an output terminal according to the voltage level of the Q node; and
a pull-down transistor supplying the gate-off signal to the output terminal according to the voltage level of the QB node;
A gate driving circuit comprising a.
According to claim 13,
The pull-up transistor includes a first thin film transistor having a gate electrode connected to the Q node, a first electrode connected to a gate-on signal line, and a second electrode connected to the output terminal;
The pull-down transistor includes a second thin film transistor having a gate electrode connected to the QB node, a first electrode connected to the output terminal, and a second electrode connected to a gate off signal line.
a display panel having a plurality of gate lines;
and a plurality of stages selectively connected to lines to which a plurality of clock signals are supplied and sequentially outputting scan pulses, each of the plurality of stages being operated by one clock signal among the plurality of clock signals. , an input unit for inputting a gate-on signal or a gate-off signal to the second node; a first inverter unit that is operated by a start signal and outputs the gate-on signal or the gate-off signal opposite to the level of the start signal to the input unit; a second inverter unit operated by the gate-on signal or the gate-off signal and outputting the gate-off signal or the gate-on signal opposite to the gate-on signal or the gate-off signal to a first node; a Q node control unit that is operated by the gate-on signal and applies the gate-on signal of the first node to a Q node; a QB node control unit operated by the gate-off signal of the first node and applying the gate-off signal to a QB node; and an output unit configured to output the gate-on signal of the Q node to an output terminal or to output the gate-off signal of the QB node to an output terminal, wherein the gate-on signal or the gate-off signal is applied to the plurality of gate lines. a gate driving circuit for applying a;
a data driving circuit for applying a data signal to the display panel; and
a timing controller controlling the gate driving circuit and the data driving circuit;
A display device comprising a.

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