TWI716469B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI716469B
TWI716469B TW105132147A TW105132147A TWI716469B TW I716469 B TWI716469 B TW I716469B TW 105132147 A TW105132147 A TW 105132147A TW 105132147 A TW105132147 A TW 105132147A TW I716469 B TWI716469 B TW I716469B
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Taiwan
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metal layer
bump
insulating layer
opening
imaging device
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TW105132147A
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TW201725710A (zh
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脇山悟
清水完
林利彦
中村卓矢
城直樹
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日商索尼半導體解決方案公司
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Abstract

本發明揭示一種成像裝置，其包含一第一半導體元件，該第一半導體元件包含具有一凹形形狀之至少一凸塊墊。該至少一凸塊墊包含一第一金屬層及該第一金屬層上之一第二金屬層。該成像裝置包含一第二半導體元件，其包含至少一電極。該成像裝置包含將該至少一凸塊墊電連接至該至少一電極之一微凸塊。該微凸塊包含該第二金屬層之一擴散部分，且該第一半導體元件或該第二半導體元件包含一像素單元。

Description

半導體裝置及其製造方法
本發明係關於一種半導體裝置及其製造方法，且本發明尤其係關於其中堆疊半導體元件之電極藉由Sn基焊料而彼此電連接之半導體裝置及其製造方法。
在相關技術中，當在由堆疊半導體元件形成之半導體裝置之一製造步驟中使堆疊半導體元件之電極彼此連接時，使用一種形成Sn基焊料(SnAg及其類似者)之一微凸塊之方法。
圖1繪示在使半導體元件堆疊時用於相關技術中之形成由Sn基焊料形成之微凸塊之方法之一簡圖。
如圖1中所繪示，使一第一半導體元件1之一側上之一Al墊2之一位置敞開且使Ni及其類似者在該位置處形成為障壁金屬3。使由Sn基焊料形成之一微凸塊6形成於一第二半導體元件4之一側上且藉由甲酸還原而依一擴散方式連接障壁金屬3及Sn基焊料6。
圖2繪示相對於Sn與可用作為障壁金屬之各種類型之金屬之間的時間之一理論擴散距離(在200℃處)。如自圖式所明白，當執行藉由甲酸還原而依一擴散方式連接且考量至Sn基焊料中之擴散率時，應將障壁金屬3之 一厚度設定為微米級(μm)，具體言之，不薄於3μm。
然而，在半導體裝置之製造中，難以允許微米級障壁金屬3流動。
同時，PTL 1揭示晶粒接合技術，其採用Ti作為Sn基焊料之障壁金屬且使用一濺鍍技術來形成可在晶圓程序中流動之約200奈米(nm)之Ti。
[引用列表]
[專利文獻]
[PTL 1]
JP 2006-108604 A
然而，PTL 1中所揭示之方法僅作為晶粒接合技術來實體地連接半導體元件，使得吾人清楚：由於由本發明之申請人執行之一高溫存放測試，歸因於合金生長及氧化之高電阻發生於Sn基焊料與Ti之間的邊界處。因此，應瞭解，儘管堆疊半導體元件之電極可彼此實體地連接，但其無法藉由PTL 1中所揭示之方法而彼此電連接。
鑑於此一條件而達成本發明，且可期望堆疊半導體元件之電極彼此實體地連接。
根據本發明之一第一態樣，在由堆疊半導體元件形成之一半導體裝置(其中對置半導體元件之電極彼此電連接)中，由Sn基焊料形成之一微凸塊形成於一第二半導體元件(其係該等對置半導體元件之一者)之一電極上，且與該微凸塊對置之一凹形凸塊墊形成於一第一半導體元件(其係該等對置半導體元件之另一者)之一電極上，該第一半導體元件之該電極透 過該微凸塊而連接至該第二半導體元件之該電極。
擴散至該微凸塊中之一第三金屬層及由Co形成之一第二金屬層可自該微凸塊之一側依序形成於該凸塊墊上。
具有不同直徑之複數個凸塊墊可提供於該第一半導體元件上。
根據待連接之該等電極之應用，該等凸塊墊之直徑可彼此不同。
該第二半導體元件之該微凸塊之一直徑可對應於該對應第一半導體元件之該凸塊墊之直徑。
該第三金屬層、該第二金屬層及由TiN形成之一第一金屬層可自該微凸塊之該側依序形成於該凸塊墊上。
可將該第二金屬層之一平均厚度設定為15nm或更厚。
可將該第一金屬層之一平均厚度設定為10nm或更厚。
該第一金屬層可由TiN、Ta或TaN形成。
該第三金屬層可由Cu、Ni、Pd、Au或Pt形成。
該凸塊墊可由自該第一半導體元件之一表面提供至該第一半導體元件中之一貫穿電極的一開口形成。
該凸塊墊可由自該第一半導體元件之該表面提供至該第一半導體元件中之金屬佈線的一開口形成。
該半導體裝置可為一堆疊CMOS影像感測器，其中對應於該第二半導體元件之一邏輯晶片藉由CoW連接而連接至對應於該第一半導體元件之一像素基板。
根據本發明之一第二態樣之一製造方法係一種製造一製造裝置之方法，其製造由堆疊半導體元件形成之一半導體裝置(其中該等對置半導體元件之電極彼此電連接)，該方法包含：一微凸塊形成步驟，其使由Sn基 焊料形成之一微凸塊形成於一第二半導體元件(其係該等對置半導體元件之一者)之一電極上；及一凸塊墊形成步驟，其使與該微凸塊對置之一凹形凸塊墊形成於一第一半導體元件(其係該等對置半導體元件之另一者)之一電極上，該第一半導體元件之該電極藉由該製造裝置透過該微凸塊而連接至該第二半導體元件之該電極。
該凸塊墊形成步驟可：使由Co形成之一第二金屬層形成於該第一半導體元件(其係該等對置半導體元件之另一者)之該電極上，該第一半導體元件之該電極透過該微凸塊而連接至該第二半導體元件之該電極；使擴散至該微凸塊中之一第三金屬層形成於該第二金屬層上；使該微凸塊與該第三金屬層接觸；在一還原氣氛下藉由加熱處理而使該第三金屬層及該微凸塊之表面上之氧化物膜還原且使該第三金屬層擴散至該微凸塊中，藉此使該微凸塊與該第二金屬層接觸；及使該第一半導體元件及該第二半導體元件之該等電極電連接。
該凸塊墊形成步驟可進一步使一鈍化層形成於該第一半導體元件之該第三金屬層上且蝕刻該鈍化層以提供其中暴露該第三金屬層之一開口。
該凸塊墊形成步驟可在形成該第二金屬層之前進一步使由TiN形成之一第一金屬層形成於該第一半導體元件(其係該等對置半導體元件之另一者)之該電極上，該第一半導體元件之該電極透過該微凸塊而連接至該第二半導體元件之該電極。
該凸塊墊形成步驟可藉由提供自該第一半導體元件之一表面至該第一半導體元件中之一貫穿電極之一開口而形成該凸塊墊。
該凸塊墊形成步驟可藉由提供自該第一半導體元件之該表面至該第一半導體元件中之金屬佈線之一開口而形成該凸塊墊。
根據本發明之第一態樣，可獲得其中電連接該第一半導體元件及該第二半導體元件之該等電極的該半導體裝置。
根據本發明之第二態樣，可獲得其中電連接該第一半導體元件及該第二半導體元件之該等電極的該半導體裝置。
1:第一半導體元件
2:Al墊
3:障壁金屬
4:第二半導體元件
6:微凸塊/Sn基焊料
10:第一半導體元件
11:Al墊
12:SiO2層
13:第一金屬層
14:第二金屬層
15:第三金屬層
16:SiN層
21:開口/凸塊墊
21-1:凸塊墊
21-2:凸塊墊
23:第二半導體元件
24:微凸塊
31:電力供應單元
32:信號處理器
33:電力供應單元
34:信號處理器
35:電力供應線
36:信號線
37:信號線
51:像素基板
52:邏輯晶片
71:WB墊
72:I/O
81:貫穿電極
91:金屬佈線/Cu佈線
S1:步驟
S2:步驟
S3:步驟
S4:步驟
S5:步驟
S6:步驟
S7:步驟
圖1係繪示使用用於連接堆疊半導體元件之電極之一微凸塊(其由Sn基焊料形成)之一方法之一簡圖的一視圖。
圖2係繪示相對於Sn與可用作為障壁金屬之各種類型之金屬之間的時間之一理論擴散距離的一視圖。
圖3係繪示本發明應用於其之一半導體裝置之一組態實例的一橫截面圖。
圖4係繪示製造圖3中之半導體裝置之一方法的一流程圖。
圖5係一製造步驟中之半導體裝置之一橫截面圖。
圖6係一製造步驟中之半導體裝置之一橫截面圖。
圖7係繪示150℃高溫存放時間中之一開爾文(Kelvin)電阻量測結果的一視圖。
圖8係繪示第一金屬層至第三金屬層之材料及厚度之一實例的一視圖。
圖9係本發明應用於其之一半導體裝置之一第一變型之一橫截面圖。
圖10係本發明應用於其之一半導體裝置之一第二變型之一橫截面圖。
圖11係繪示一凸塊墊及一微凸塊之直徑與一凸塊電容之間的一關係 的一視圖。
圖12係繪示凸塊墊及微凸塊之直徑與一電阻值之間的一關係的一視圖。
圖13係繪示半導體裝置之第二變型之一應用實例的一方塊圖。
圖14係繪示本發明應用於其之半導體裝置應用於一堆疊CMOS影像感測器時之一堆疊前狀態的一橫截面圖。
圖15係繪示本發明應用於其之半導體裝置應用於堆疊CMOS影像感測器時之一堆疊後狀態的一橫截面圖。
圖16係繪示其中一I/O連接至形成於一邏輯晶片上之一WB墊之一狀態的一橫截面圖。
圖17係繪示關於一凸塊墊之形成之一變型的一橫截面圖。
圖18係繪示關於一凸塊墊之形成之一變型的一橫截面圖。
圖19係繪示關於一凸塊墊之形成之一變型的一橫截面圖。
[相關申請案之交叉參考]
本申請案主張2015年10月21日申請之日本優先專利申請案JP 2015-207233之權利，該案之全部內容以引用的方式併入本文中。
在下文中，將參考圖式來詳細地描述用於實施本發明之一最佳模式(下文中指稱一實施例)。
<半導體裝置之組態實例>
圖3係繪示一半導體裝置之一組態實例(其係本發明之一實施例)的一橫截面圖。應注意，此圖式僅繪示一第一半導體元件之一側，其上未形成自該第一半導體元件及一第二半導體元件突出之一微凸塊，該第一半導體 元件及該第二半導體元件經堆疊以經由Sn基焊料而彼此電連接。
同時，指示焊料之一材料之一Sn基包含一SnAg基、一SnBi基、一SnCu基、一SnIn基、一SnAgCu基及其類似者。
如圖中所繪示，一Al墊11(或接觸件或至少一接觸件)作為一電極提供於一第一半導體元件10上，Al墊11之一部分形成為用於連接至第二半導體元件上之微凸塊之一開口21(圖5)，且一第一金屬層13、一第二金屬層14及一第三金屬層15依序形成於開口21上。一SiO2層(或絕緣層)12形成於除開口21之外之一部分上且一SiN層16形成於SiO2層12上。為便於解釋，層13、14及15在此處分別指稱第一金屬層至第三金屬層。然而，實例性實施例不受限於此。例如，取決於實施例，第一金屬層13可指稱以一第二金屬層或一第三金屬層，第二金屬層14可指稱一第一金屬層或一第三金屬層，且第三金屬層15可指稱一第一金屬層或一第二金屬層。相同原理應用於在本發明中被描述為「第一」、「第二」、「第三」等等之其他元件。
例如，採用TiN作為用作障壁金屬之第一金屬層13。將第一金屬層13之一平均厚度設定為約10nm或更厚。據此，可在一晶圓生產線中形成第一金屬層13，其中可尤其降低一顆粒風險。亦可採用Ta或TaN作為第一金屬層。
可藉由提供第一金屬層(障壁金屬)13而防止Al墊11與第二金屬層14之間的反應及一合金層(其可藉由形成第二半導體元件之微凸塊之Sn基焊料與第二金屬層14之間的反應而產生)與Al墊11之間的反應。據此，可預期半導體裝置之可靠性及電特性之改良。同時，亦可省略第一金屬層13。
採用具有有關Sn基焊料之一相圖及低擴散率之一材料(例如Co)作為第二金屬層14。將第二金屬層14之一平均厚度設定為約15nm或更厚。據 此，可在晶圓生產線中形成第二金屬層14，其中可尤其降低顆粒風險。
採用一材料(例如Cu)作為第三金屬層15，該材料可藉由具有至Sn中之高擴散率之免清洗助焊劑、還原氣體及其類似者而使第二金屬層14之一表面上之一表面氧化物膜還原。將第三金屬層15之一平均厚度設定為約80nm或更厚以防止第二金屬層14氧化。除Cu之外，亦可採用Ni、Pd、Au、Pt及其類似者作為第三金屬層15。
由於採用上述組態，所以即使採用極易氧化且較難還原之Co作為第二金屬層14之材料，但Sn基焊料與第二金屬層14之間的接觸(反應)仍變得較容易。此外，可藉由採用Co作為第二金屬層14而改良可靠性及電特性。
<製造半導體裝置之方法>
接著，參考圖4至圖6來描述製造圖3中所繪示之半導體裝置之一方法。
圖4係繪示製造圖3中之半導體裝置之方法的一流程圖。圖5及圖6係繪示一製程的半導體裝置之橫截面圖。
在步驟S1中，如圖5A中所繪示，使SiO2層12形成於其上提供Al墊11作為電極之第一半導體元件10上。接著，根據稍後將描述之開口21之一位置及一直徑，將用於保護除開口21之外之部分之光阻圖案(圖中未繪示)提供於SiO2層12上。此外，如圖5B中所繪示，藉由乾式蝕刻而研磨SiO2層12，直至暴露Al墊11而提供開口21。
在步驟S2中，如圖5C中所繪示，藉由濺鍍而形成第一金屬層(TiN)13、第二金屬層(Co)14及第三金屬層(Cu)15。接著，在步驟S3中，如圖5D中所繪示，藉由相同於第三金屬層15之材料(在情況中為Cu)之材料之 一電鍍程序而增大第三金屬層15之一厚度且使用第三金屬層15來填充開口21之一凹形部分。換言之，藉由一第一沈積程序及一第二沈積程序而形成第三金屬層15。該第一沈積程序使第三金屬層15之一部分形成於凹形形狀中，且該第二沈積程序形成第三金屬層15之一剩餘部分來填充凹形形狀。
在步驟S4中，如圖5E中所繪示，藉由化學機械拋光(CMP)而移除或平坦化除開口21之外之部分上之第三金屬層15及第二金屬層14。在步驟S5中，使作為一鈍化層之SiN層16形成於整個表面上且施加400℃/1h處之退火處理以實現Tr損壞恢復。此外，將光阻圖案(圖中未繪示)提供於SiN層16上且研磨SiN層16，直至藉由乾式蝕刻而暴露開口21上之第三金屬層15，如圖6A中所繪示。據此，開口21具有一凹形結構，使得由Sn基焊料形成之一微凸塊24(其形成於一第二半導體元件23上)之定位變容易。在下文中，與微凸塊24對置之開口21亦指稱一凸塊墊21(或至少一凸塊墊)。
在步驟S6中，如圖6B中所繪示，使形成於第二半導體元件23上之微凸塊24與凸塊墊21之第三金屬層15接觸且藉由甲酸及其類似者之一還原氣氛下之加熱處理而使第三金屬層15及形成微凸塊24之Sn基焊料之表面上之氧化物膜還原。其後，在步驟S7中，如圖6C中所繪示，使第三金屬層15擴散至Sn基焊料中且使Sn基焊料與第二金屬層14接觸(反應)，使得Al墊11(其係第一半導體元件10之電極)與第二半導體元件23之一電極之間建立連接。製造方法之描述結束。
<高溫存放時間中之開爾文電阻量測結果>
接著，圖7繪示分別採用TiN、Co及Cu作為第一金屬層13、第二金屬 層14及第三金屬層15時之第二金屬層14連接至由Sn基焊料形成之微凸塊24時之150℃高溫存放時間中之一開爾文電阻量測結果。
如圖式中所繪示，在504個小時之後，一電阻值不改變。因此，在一段時間之後亦維持第一半導體元件10之電極與第二半導體元件23之電極之間的電連接。
<第一金屬層13、第二金屬層14及第三金屬層15之材料及厚度>
接著，圖8繪示改變第二金屬層14之厚度及第三金屬層15之材料及厚度時之第一實例至第四實例及比較實例(PTL 1中所揭示之組態)之評估。
在第一實例中，分別採用20nm TiN、270nm Co及200nm Cu作為第一金屬層13、第二金屬層14及第三金屬層15。在第二實例中，分別採用20nm TiN、100nm Co及200nm Cu作為第一金屬層13、第二金屬層14及第三金屬層15。在第三實例中，分別採用20nm TiN、30nm Co及200nm Cu作為第一金屬層13、第二金屬層14及第三金屬層15。在第四實例中，分別採用20nm TiN、270nm Co及80nm Cu作為第一金屬層13、第二金屬層14及第三金屬層15。
在第一實例至第四實例之任何者中，可連接性及高溫存放測試之結果不存在問題且第一半導體元件10之電極與第二半導體元件23之電極之間建立實體連接及電連接。同時，在比較實例1中，當進行針對Tr損壞恢復所引入之燒結退火處理以防止至焊料之可連接性時，使第一金屬層Ti擴散至第二金屬層Co中。在比較實例2中，第一金屬層TiN與焊料之間不建立可連接性。在比較實例3中，即使將第二金屬層Co設定為10nm，但無法保證至焊料之可連接性。
<半導體裝置之第一變型>
圖9係繪示一半導體裝置之一第一變型(其係本發明之一實施例)的一橫截面圖。
藉由自圖3中所繪示之一組態實例省略一第一金屬層13而獲得第一變型。據此，可縮短程序循環時間且可減少成本。
<半導體裝置之第二變型>
接著，圖10係繪示一半導體裝置之一第二變型(其係本發明之一實施例)的一橫截面圖。
藉由根據待連接至提供於一第一半導體元件10上之一凸塊墊21之一電極(線)之應用改變凸塊墊21之一直徑而獲得第二變型。提供於第一半導體元件10上之兩個凸塊墊21經形成使得一凸塊墊21-2具有大於一凸塊墊21-1之直徑的一直徑。
同時，可藉由改變在上述製程之步驟S1中提供於一SiO2層12上之光阻圖案及在步驟S5中提供於一SiN層16上之光阻圖案而容易地改變提供於相同基板(在此情況中為第一半導體元件10)上之複數個凸塊墊21之直徑。
另一方面，亦根據對應凸塊墊21之直徑而改變一第二半導體元件之由Sn基焊料形成之一微凸塊24之一直徑。
<取決於凸塊墊21之直徑與微凸塊24之直徑之差異之凸塊電容變化>
圖11繪示取決於凸塊墊21之直徑(開口直徑)與微凸塊之直徑之差異之凸塊電容變化。
如圖式中所繪示，當比較其中凸塊墊21及微凸塊24之直徑較小之一情況與其中凸塊墊21及微凸塊24之直徑較大之一情況時，其中凸塊墊21及微凸塊24之直徑較小之該情況中之凸塊電容係較小的。因此，當藉由使用具有小直徑之凸塊墊21及微凸塊24而連接一信號線時，可預期待傳送 之一電信號之信號特性之改良。此外，在此情況中，待連接之佈線之選路較容易。
<取決於凸塊墊21之直徑與微凸塊24之直徑之差異之電阻值變化>
圖12繪示取決於凸塊墊21之直徑(開口直徑)與微凸塊24之直徑之差異之電阻值變化。
如圖式中所繪示，凸塊墊21及微凸塊24之直徑越大，電阻值越小。因此，當藉由使用具有較大直徑之凸塊墊21及微凸塊24而連接一電力供應線時，可抑制關於電力供應(諸如IR壓降)之一缺陷。
<半導體裝置之第二變型之應用實例>
接著，圖13繪示圖10中所繪示之一第二組態實例之一應用實例。
在此應用實例中，藉由使用具有較大直徑之凸塊墊21-1及微凸塊24而連接一電力供應線35，電力供應線35將第一半導體元件10之一電力供應單元31連接至一第二半導體元件23之一電力供應單元33。此外，藉由使用具有較小直徑之凸塊墊21-2及微凸塊24而連接信號線36及37，信號線36及37將第一半導體元件10之一信號處理器32連接至第二半導體元件23之一信號處理器34。
根據圖13中所繪示之應用實例，可改良在第一半導體元件10與第二半導體元件23之間傳送之電信號之信號特性且可抑制關於電力供應(諸如IR壓降)之缺陷。
<半導體裝置之應用實例>
接著，描述一組態實例，其中將根據本發明之一實施例之半導體裝置應用於一堆疊CMOS影像感測器(下文中指稱一堆疊CIS)。
圖14繪示根據本發明之一實施例之半導體裝置應用於其之堆疊CIS之 一堆疊前狀態且圖15繪示其之一堆疊後狀態。
即，堆疊CIS經形成使得處理自一像素基板51輸出之一像素信號之一邏輯晶片52堆疊於像素基板51上，執行光電轉換之一像素單元藉由晶片堆疊晶圓(CoW)連接而形成於像素基板51上。
像素基板51對應於第一半導體元件10；待連接至邏輯晶片52之微凸塊24之凸塊墊21形成於一光入射側上之像素基板51之一表面上。另一方面，邏輯晶片52對應於第二半導體元件23；微凸塊24形成於待連接至像素基板51之一表面上。
在其中凸塊墊21及微凸塊24經堆疊以彼此接觸之一狀態中，像素基板51及邏輯晶片52經受加熱處理，使得其等彼此電連接。同時，一WB墊71形成於與像素基板51連接至其之表面對置之邏輯晶片52之一表面上且一I/O 72連接至WB墊71，如圖16中所繪示。
如圖中所繪示，可藉由將根據本發明之一實施例之半導體裝置應用於堆疊CMOS影像感測器而抑制損壞，諸如可發生於微凸塊墊亦形成於待連接之像素基板51之一側上時之像素單元之一灰塵缺陷。此外，可使像素基板51及邏輯晶片52堆疊時之一高度降低且可抑制CF之掃描不均勻性。
<關於凸塊墊之形成之變型>
接著，描述關於一凸塊墊之形成之一變型。
圖17繪示變型，其中當一貫穿電極81形成於一像素基板51中且貫穿電極81用作為對應於一邏輯晶片52之一微凸塊24之凸塊墊時，一開口21提供於貫穿電極81之一位置處。當貫穿電極81本身用作為凸塊墊時，可省略第一金屬層13至第三金屬層15之形成。
圖18及圖19繪示一變型，其中自像素基板51(第一半導體元件10)省 略一Al墊11，開口21經形成以到達像素基板51中之金屬佈線(Cu佈線)91，且基板中之金屬佈線91用作為對應於邏輯晶片52之微凸塊24之凸塊墊。
當省略Al墊11且像素基板51中之金屬佈線91用作為凸塊墊時，可改良一客製程序之掃描不均勻性且可實現晶片縮小。此外，可減小邏輯晶片52之一高度。
同時，根據本發明之一實施例之半導體裝置除可應用於上述堆疊CIS之外，亦可應用於其中堆疊半導體元件之電極彼此連接之所有類型之電子裝置。
本發明之實施例不受限於上述實施例，而是可在不背離本發明之範疇之情況下作出各種改變。
同時，本發明亦可組態如下。
(1)一種成像裝置，其包括一第一半導體元件，該第一半導體元件包含具有一凹形形狀之至少一凸塊墊，其中該至少一凸塊墊包含一第一金屬層及該第一金屬層上之一第二金屬層。該成像裝置包含一第二半導體元件，其包含至少一電極。該成像裝置包含將該至少一凸塊墊電連接至該至少一電極之一微凸塊，其中該微凸塊包含該第二金屬層之一擴散部分，且其中該第一半導體元件或該第二半導體元件包含一像素單元。
(2)如上述(1)之成像裝置，其中該微凸塊包含Sn基焊料且該第一金屬層包含Co。
(3)如上述(1)或(2)之成像裝置，其中該至少一凸塊墊包含具有不同直徑之複數個凸塊墊，且其中該至少一電極包含對應於該複數個凸塊墊之複數個電極。
(4)如上述(1)至(3)中任一項之成像裝置，其中根據待連接之該複數個電極之一應用，該等不同直徑彼此不同。
(5)如上述(1)至(4)中任一項之成像裝置，其中該微凸塊之一直徑對應於該至少一凸塊墊層之一直徑。
(6)如上述(1)至(5)中任一項之成像裝置，其中該至少一凸塊墊包含一第三金屬層，且其中該第一金屬層位於該第三金屬層上。
(7)如上述(1)至(6)中任一項之成像裝置，其中該第一金屬層之一平均厚度係15nm或更厚。
(8)如上述(1)至(7)中任一項之成像裝置，其中該第三金屬層之一平均厚度係10nm或更厚。
(9)如上述(1)至(8)中任一項之成像裝置，其中該第三金屬層由TiN、Ta或TaN形成。
(10)如上述(1)至(9)中任一項之成像裝置，其中該第二金屬層由Cu、Co、Ni、Pd、Au或Pt形成。
(11)如上述(1)之成像裝置，其中該至少一凸塊墊係提供於該第一半導體元件之一表面上以將該微凸塊連接至該第一半導體元件中之一貫穿電極的一開口。
(12)如上述(1)之成像裝置，其中該至少一凸塊墊係提供於該第一半導體元件之一表面上以將該微凸塊連接至該第一半導體元件中之一金屬佈線的一開口。
(13)如上述(1)之成像裝置，其中該第一半導體元件係該像素單元且該第二半導體元件係藉由一晶片堆疊晶圓(CoW)連接而連接至該第一半導體元件之一邏輯晶片。
(14)一種製造一成像裝置之方法，其包括：使至少一接觸件形成於一第一基板上；使一絕緣層形成於該至少一接觸件上；蝕刻該絕緣層以提供暴露該至少一接觸件之一部分之至少一開口；使至少一凸塊墊形成於該開口中，使得該至少一凸塊墊具有一凹形形狀；及藉由使該至少一凸塊墊之一部分擴散至連接至一第二基板之一電極之一微凸塊中而將該至少一凸塊墊電連接至該電極。
(15)如上述(14)之方法，其中該形成該至少一凸塊墊包含：使一第一金屬層形成於該至少一接觸件上；及使一第二金屬層形成於該第一金屬層上，其中該至少一凸塊墊之該擴散部分包含該第二金屬層。
(16)如上述(15)之方法，其中該形成該第二金屬層包含：根據一第一沈積程序而使該第二金屬層之一部分形成於該凹形形狀中；及根據一第二沈積程序而形成該第二金屬層之一剩餘部分來填充該凹形形狀。
(17)如上述(15)之方法，其中該形成該至少一凸塊墊包含：在形成該第一金屬層及該第二金屬層之前，使一第三金屬層形成於該絕緣層上。
(18)如上述(17)之方法，其中該形成該至少一凸塊墊包含：平坦化該第一金屬層、該第二金屬層及該第三金屬層，使得該第一金屬層、該第二金屬層及該第三金屬層之上表面與該絕緣層之一上表面共面。
(19)如上述(18)之方法，其中該第二金屬層擴散至該微凸塊中，使得該微凸塊之一尖端部分延伸超出該絕緣層之該上表面，同時該微凸塊之另一部分存在於該絕緣層之該上表面與該電極之間的一空間中。
(20)如上述(18)之方法，其中該形成該至少一凸塊墊包含：使一鈍化層形成於該絕緣層及該第一金屬層、該第二金屬層及該第三金屬層上；及蝕刻該鈍化層以暴露該第二金屬層且產生該凹形形狀。
(21)一種由堆疊半導體元件形成之半導體裝置，其中該等對置半導體元件之電極彼此電連接，其中由Sn基焊料形成之一微凸塊形成於一第二半導體元件之一電極上，該第二半導體元件係該等對置半導體元件之一者，且與該微凸塊對置之一凹形凸塊墊形成於一第一半導體元件之一電極上，該第一半導體元件係該等對置半導體元件之另一者，該第一半導體元件之該電極透過該微凸塊而連接至該第二半導體元件之該電極。
(22)如上述(21)之半導體裝置，其中擴散至該微凸塊中之一第三金屬層及由Co形成之一第二金屬層自該微凸塊之一側依序形成於該凸塊墊上。
(23)如上述(21)或(22)之半導體裝置，其中具有不同直徑之複數個凸塊墊提供於該第一半導體元件上。
(24)如上述(21)至(23)中任一項之半導體裝置，其中根據待連接之電極之應用，該等凸塊墊之直徑彼此不同。
(25)如上述(21)至(24)中任一項之半導體裝置，其中該第二半導體元件之該微凸塊之一直徑對應於該對應第一半導體元件之該凸塊墊之一直徑。
(26)如上述(21)至(25)中任一項之半導體裝置，其中該第三金屬層、該第二金屬層及由TiN形成之一第一金屬層自該微凸塊之該側依序形成於該凸塊墊上。
(27)如上述(21)至(26)中任一項之半導體裝置，其中該第二金屬層之一平均厚度係15nm或更厚。
(28)如上述(21)至(27)中任一項之半導體裝置，其中該第一金屬層之一平均厚度係10nm或更厚。
(29)如上述(21)至(28)中任一項之半導體裝置，其中該第一金屬層由TiN、Ta或TaN形成。
(30)如上述(21)至(29)中任一項之半導體裝置，其中該第三金屬層由Cu、Ni、Pd、Au或Pt形成。
(31)如上述(21)之半導體裝置，其中該凸塊墊由自該第一半導體元件之一表面提供至該第一半導體元件中之一貫穿電極的一開口形成。
(32)如上述(21)之半導體裝置，其中該凸塊墊由自該第一半導體元件之一表面提供至該第一半導體元件中之金屬佈線的一開口形成。
(33)如上述(21)之半導體裝置，其係一堆疊CMOS影像感測器，其中對應於該第二半導體元件之一邏輯晶片藉由CoW連接而連接至對應於該第一半導體元件之一像素基板。
(34)一種製造一製造裝置之方法，其製造由堆疊半導體元件形成之一半導體裝置，其中該等對置半導體元件之電極彼此電連接，該方法包含：一微凸塊形成步驟，其使由Sn基焊料形成之一微凸塊形成於一第二半導體元件之一電極上，該第二半導體元件係該等對置半導體元件之一者；及一凸塊墊形成步驟，其使與該微凸塊對置之一凹形凸塊墊形成於第一半導體元件之一電極上，該第一半導體元件係該等對置半導體元件之另一者，該第一半導體元件之該電極藉由該製造裝置透過該微凸塊而連接至該第二半導體元件之該電極。
(35)如上述(34)之製造方法，其中該凸塊墊形成步驟：使由Co形成之一第二金屬層形成於該第一半導體元件之該電極上，該第一半導體元件係該等對置半導體元件之另一者，該第一半導體元件之該電極透過該微凸塊而連接至該第二半導體元件之該電極；使擴散至該微凸塊中之一第三金 屬層形成於該第二金屬層上；使該微凸塊與該第三金屬層接觸；在一還原氣氛下藉由加熱處理而使該第三金屬層及該微凸塊之表面上之氧化物膜還原且使該第三金屬層擴散至該微凸塊中，藉此使該微凸塊與該第二金屬層接觸；及使該第一半導體元件及該第二半導體元件之該等電極電連接。
(36)如上述(35)之製造方法，其中該凸塊墊形成步驟進一步使一鈍化層形成於該第一半導體元件之該第三金屬層上且蝕刻該鈍化層以提供其中暴露該第三金屬層之一開口。
(37)如上述(35)之製造方法，其中該凸塊墊形成步驟在形成該第二金屬層之前進一步使由TiN形成之一第一金屬層形成於該第一半導體元件之該電極上，該第一半導體元件係該等對置半導體元件之另一者，該第一半導體元件之該電極透過該微凸塊而連接至該第二半導體元件之該電極。
(38)如上述(34)之製造方法，其中該凸塊墊形成步驟藉由提供自該第一半導體元件之一表面至該第一半導體元件中之一貫穿電極之一開口而形成該凸塊墊。
(39)如上述(34)之製造方法，該凸塊墊形成步驟藉由提供自該第一半導體元件之一表面至該第一半導體元件中之金屬佈線之一開口而形成該凸塊墊。
10‧‧‧第一半導體元件
11‧‧‧Al墊
12‧‧‧SiO2層
13‧‧‧第一金屬層
14‧‧‧第二金屬層
15‧‧‧第三金屬層
16‧‧‧SiN層
21‧‧‧開口/凸塊墊
23‧‧‧第二半導體元件
24‧‧‧微凸塊

Claims (20)

  1. 一種成像裝置，其包括：一第一基板；一接觸件，其安置於該第一基板上且包含面對該第一基板之一第一表面及相對於該第一表面之一第二表面；一第一絕緣層，其在該接觸件之側壁上且包含暴露該接觸件之該第二表面之一開口；至少一凸塊墊，其包含：一第一金屬層，其安置於該第一絕緣層之該開口中且電連接至該接觸件；及一第二金屬層，其安置於該第一絕緣層之該開口中且在該第一金屬層上；一第二絕緣層，其在該第一絕緣層上且包含暴露該第二金屬層之一開口；一第二基板，其包含至少一電極；及一微凸塊，其將該至少一凸塊墊電連接至該至少一電極且經定位於該第二絕緣層之該開口中，其中該微凸塊包含該第二金屬層之一擴散部分，且其中該第一基板或該第二基板包含一像素單元。
  2. 如請求項1之成像裝置，其中該微凸塊包含Sn基焊料且該第一金屬層包含Co。
  3. 如請求項2之成像裝置，其中該至少一凸塊墊包含具有不同直徑之複數個凸塊墊，及其中該至少一電極包含對應於該複數個凸塊墊之複數個電極。
  4. 如請求項3之成像裝置，其中根據待連接之該複數個電極之一應用，該等不同直徑彼此不同。
  5. 如請求項1之成像裝置，其中該微凸塊之一直徑對應於該至少一凸塊墊之一直徑。
  6. 如請求項1之成像裝置，其中該至少一凸塊墊包含一第三金屬層，其安置於該第一絕緣層之該開口中，及其中該第一金屬層位於該第三金屬層上。
  7. 如請求項6之成像裝置，其中該第一金屬層之一平均厚度係15nm或更厚。
  8. 如請求項6之成像裝置，其中該第三金屬層之一平均厚度係10nm或更厚。
  9. 如請求項6之成像裝置， 其中該第三金屬層由TiN、Ta或TaN形成。
  10. 如請求項6之成像裝置，其中該第二金屬層由Cu、Co、Ni、Pd、Au或Pt形成。
  11. 如請求項1之成像裝置，其中該第二金屬層之一表面與該第一絕緣層之一表面共面(coplanar)。
  12. 如請求項1之成像裝置，其中該第一絕緣層接觸該接觸件之該第二表面。
  13. 如請求項1之成像裝置，其中該第一基板係該像素單元且該第二基板係藉由一晶片堆疊晶圓(CoW)連接而連接至該第一基板之一邏輯晶片。
  14. 一種製造一成像裝置之方法，其包括：使至少一接觸件形成於一第一基板上，該至少一接觸件具有面對該第一基板之一第一表面及相對於該第一表面之一第二表面；使一第一絕緣層形成於該至少一接觸件上，該第一絕緣層與該至少一接觸件之側壁接觸；蝕刻該第一絕緣層以提供暴露該至少一接觸件之一部分之至少一第一開口； 使至少一凸塊墊形成於該第一絕緣層之該至少一第一開口中；使一第二絕緣層形成於該第一絕緣層及該至少一凸塊墊上；蝕刻該第二絕緣層以提供暴露該至少一凸塊墊之至少一第二開口；及將該至少一凸塊墊電連接至一第二基板之一電極，其藉由定位連接至該第二絕緣層之該至少一第二開口中之該電極之一微凸塊及藉由使該至少一凸塊墊之一部分擴散至該微凸塊中，其中該第一基板或該第二基板包含一像素單元。
  15. 如請求項14之方法，其中該形成該至少一凸塊墊包含：使一第一金屬層形成於該至少一第一開口中之該至少一接觸件上；及使一第二金屬層形成於該第一金屬層上，其中該至少一凸塊墊之該擴散部分包含該第二金屬層。
  16. 如請求項15之方法，其中該形成該第二金屬層包含：根據一第一沈積程序而使該第二金屬層之一部分形成於該第一絕緣層之該至少一第一開口中；及根據一第二沈積程序而形成該第二金屬層之一剩餘部分來填充該第一絕緣層之該至少一第一開口。
  17. 如請求項15之方法，該形成該至少一凸塊墊包含在形成該第一金屬層及該第二金屬層之前，使一第三金屬層形成於該第一絕緣層之該至少一 第一開口中。
  18. 如請求項17之方法，其中該形成該至少一凸塊墊包含平坦化該第一金屬層、該第二金屬層及該第三金屬層，使得該第二金屬層之一表面與該第一絕緣層之一表面共面。
  19. 如請求項18之方法，其中該第二金屬層擴散至該微凸塊中，使得該微凸塊之一尖端部分延伸超出該第一絕緣層之該表面，同時該微凸塊之另一部分存在於該第一絕緣層之該表面與該電極之間的一空間中。
  20. 如請求項18之方法，其中該第一絕緣層接觸該至少一接觸件之該第二表面。
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