CN114335039A - 摄像装置和半导体装置 - Google Patents

摄像装置和半导体装置 Download PDF

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Publication number
CN114335039A
CN114335039A CN202111423047.5A CN202111423047A CN114335039A CN 114335039 A CN114335039 A CN 114335039A CN 202111423047 A CN202111423047 A CN 202111423047A CN 114335039 A CN114335039 A CN 114335039A
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Prior art keywords
metal layer
bump
semiconductor device
micro
insulating layer
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CN202111423047.5A
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Inventor
胁山悟
清水完
林利彦
中村卓矢
城直树
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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Publication of CN114335039A publication Critical patent/CN114335039A/zh
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Abstract

本发明涉及摄像装置和半导体装置。摄像装置包括：第一基板，包括一个或多个像素；触点，被布置在第一基板上，并且包括面对第一基板的第一表面和与第一表面相对的第二表面；第一绝缘层，在第一基板上，并且包括在触点的第二表面上方的开口；至少一个凸块焊盘，包括：第一金属层，被布置在第一绝缘层的开口中，并且电连接至触点；和第二金属层，在第一金属层上，并且被布置在第一绝缘层的开口中；第二绝缘层，在第一绝缘层上，并且包括第二金属层上方的开口；第二基板，包括逻辑电路和至少一个电极；以及微凸块，将至少一个凸块焊盘电连接至至少一个电极，并且位于第二绝缘层的开口中。

Description

摄像装置和半导体装置
本申请是申请日为2016年10月7日、发明名称为“半导体装置和用于制造半导体装置的方法”的申请号为201680058117.2的专利申请的分案申请。
技术领域
本发明涉及半导体装置和用于制造半导体装置的方法，并且特别地涉及如下的一种半导体装置和用于制造这种半导体装置的方法：在该半导体装置中，堆叠起来的半导体元件的电极通过Sn基焊料而电气地相互连接。
相关申请的交叉引用
本申请要求2015年10月21日提交的日本在先专利申请JP2015-207233的优先权权益，并且该日本在先专利申请的全部内容以引用的方式并入本文中。
背景技术
在现有技术中，在由堆叠起来的半导体元件形成的半导体装置的制造步骤中，当把被堆叠的半导体元件的电极相互连接时，使用了用于形成由Sn基焊料(SnAg等)制成的微凸块的方法。
图1示出了当将半导体元件堆叠时在现有技术中使用的用于形成由Sn基焊料制成的微凸块的方法的概要。
如图1所示，在第一半导体元件1的一侧上在Al焊盘2的位置上形成开口部，并且在此处形成Ni等以作为阻挡金属3。在第二半导体元件4的一侧上形成有由Sn基焊料制成的微凸块6，并且通过甲酸还原使阻挡金属3和Sn基焊料6以扩散的方式进行连接。
图2示出了以时间为横坐标、Sn与可以用作阻挡金属的各种金属之间的理论扩散距离(在200℃的情况下)。从该图中可以清楚的看出，当通过甲酸还原以扩散的方式进行连接被实施时并且考虑到向Sn基焊料中扩散的扩散性，阻挡金属3的厚度应当被设定为微米(μm)量级，特别地，不小于3μm。
然而，在半导体装置的制造处理中，让阻挡金属3以μm量级发生流动是很困难的。
此外，专利文献PTL 1公开了如下的贴片(die bond)技术：其采用Ti作为Sn基焊料的阻挡金属，并且利用溅射技术在晶片工艺中形成可以流动的大约200纳米(nm)的Ti。
引用列表
专利文献
[PTL 1]日本专利申请特开JP 2006-108604A公报
发明内容
[要解决的技术问题]
然而，在PTL 1中所公开的方法中，作为贴片技术仅仅将半导体元件物理地连接，因而显然可知的是，就如本发明的申请人所做的高温搁置(high temperature shelf)实验的结果一样，在Sn基焊料和Ti之间的界面处出现了因合金生长和氧化而产生的高电阻。因此，可以理解的是，通过PTL 1中所公开的方法，尽管被堆叠的半导体元件的电极可以物理地相互连接，但这些电极不是电气地相互连接。
本发明是在上述这种状况下获得的，并且本发明所期望的是，被堆叠的半导体元件的电极电气地相互连接。
[技术方案]
根据本发明的一些方面，提供了一种半导体装置，其包括：第一半导体元件，所述第一半导体元件包括至少一个具有凹陷形状的凸块焊盘，所述至少一个凸块焊盘包括第一金属层和所述第一金属层上的第二金属层；第二半导体元件，所述第二半导体元件包括至少一个电极；和微凸块，所述微凸块将所述至少一个凸块焊盘电气地连接到所述至少一个电极。这里，所述微凸块包括所述第二金属层的扩散部，并且所述第一半导体元件或者所述第二半导体元件包括像素单元。
根据本发明的一些方面，提供了一种用于制造半导体装置的方法，其包括：在第一基板上形成至少一个触点；在所述至少一个触点上形成绝缘层；蚀刻所述绝缘层，以提供使所述至少一个触点的一部分露出的至少一个开口部；在所述开口部中形成至少一个凸块焊盘，且所述至少一个凸块焊盘具有凹陷形状；以及通过使所述至少一个凸块焊盘的一部分扩散到与第二基板的电极连接的微凸块中，将所述至少一个凸块焊盘电气地连接到所述第二基板的所述电极。这里，所述第一基板或所述第二基板包括像素单元。
根据本发明的第一方面，在由堆叠起来的半导体元件形成的半导体装置中，对置的半导体元件的电极电气地相互连接。在该半导体装置中，第二半导体元件是所述对置的半导体元件中的一者，在所述第二半导体元件的电极上形成有由Sn基焊料制成的微凸块；并且，第一半导体元件是所述对置的半导体元件中的另一者、且经由所述微凸块与所述第二半导体元件的所述电极连接，在所述第一半导体元件的电极上形成有与所述微凸块相对的凹陷状凸块焊盘。
在所述凸块焊盘上，从所述微凸块侧可以依次形成有：扩散到所述微凸块中的第三金属层；和由Co形成的第二金属层。
在所述第一半导体元件上可以设置有具有不同直径的多个凸块焊盘。
所述凸块焊盘的直径可以是根据待连接的电极的用途而彼此不同的。
所述第二半导体元件的所述微凸块的直径可以对应于相应的所述第一半导体元件的所述凸块焊盘的直径。
在所述凸块焊盘上，从所述微凸块侧可以依次形成有所述第三金属层、所述第二金属层和由TiN形成的第一金属层。
所述第二金属层的平均厚度可以设定为15nm以上。
所述第一金属层的平均厚度可以设定为10nm以上。
所述第一金属层可以由TiN、Ta或者TaN形成。
所述第三金属层可以由Cu、Ni、Pd、Au或者Pt形成。
所述凸块焊盘可以由被设置为从所述第一半导体元件的表面到所述第一半导体元件中的贯通电极的开口部形成。
所述凸块焊盘可以由被设置为从所述第一半导体元件的表面到所述第一半导体元件中的金属布线的开口部形成。
所述半导体装置可以是堆叠型CMOS图像传感器，其中，相当于所述第二半导体元件的逻辑芯片通过CoW连接(晶片上芯片连接(chip on wafer connection))而被连接到相当于所述第一半导体元件的像素基板。
根据本发明的第二方面的制造方法是用于制造半导体装置的制造设备的制造方法，其中所述半导体装置由堆叠起来的半导体元件形成，并且在所述半导体装置中，对置的半导体元件的电极电气地相互连接。该制造方法包括：通过所述制造设备来形成微凸块的步骤，其用于在第二半导体元件的电极上形成由Sn基焊料制成的微凸块，所述第二半导体元件是所述对置的半导体元件中的一者；和通过所述制造设备来形成凸块焊盘的步骤，其用于在第一半导体元件的电极上形成与所述微凸块相对的凹陷状凸块焊盘，所述第一半导体元件是所述对置的半导体元件中的另一者、且经由所述微凸块与所述第二半导体元件的所述电极连接。
在形成所述凸块焊盘的步骤中，可以在经由所述微凸块与所述第二半导体元件的所述电极连接的、且作为所述对置的半导体元件中的另一者的所述第一半导体元件的所述电极上形成由Co制成的第二金属层，在所述第二金属层上形成将要扩散到所述微凸块中的第三金属层，使所述微凸块与所述第三金属层接触，在还原氛围下通过热处理来还原所述第三金属层的表面上和所述微凸块的表面上的氧化膜，且使所述第三金属层扩散至所述微凸块中，由此，就使得所述微凸块与所述第二金属层接触，并且将所述第一半导体元件的所述电极和所述第二半导体元件的所述电极电气地连接。
另外，在形成所述凸块焊盘的步骤中，可以在所述第一半导体元件的所述第三金属层上形成钝化层，并且蚀刻所述钝化层以提供使所述第三金属层露出的开口部。
另外，在形成所述凸块焊盘的步骤中，在形成所述第二金属层之前，可以在经由所述微凸块与所述第二导体元件的所述电极连接的、且作为所述对置的半导体元件中的另一者的所述第一半导体元件的所述电极上形成由TiN制成的第一金属层。
在形成所述凸块焊盘的步骤中，可以通过设置从所述第一半导体元件的表面到所述第一半导体元件中的贯通电极的开口部来形成所述凸块焊盘。
在形成所述凸块焊盘的步骤中，可以通过设置从所述第一半导体元件的表面到所述第一半导体元件中的金属布线的开口部来形成所述凸块焊盘。
[本发明的有益效果]
根据本发明的第一方面，可以获得其中第一半导体元件的电极和第二半导体元件的电极电气地连接的半导体装置。
根据本发明的第二方面，可以制造出其中第一半导体元件的电极和第二半导体元件的电极电气地连接的半导体装置。
附图说明
图1是示出了使用由Sn基焊料制成的微凸块来连接被堆叠的半导体元件的电极的方法的概要的图。
图2是示出了以时间为横坐标的、Sn与可以用作阻挡金属的各种金属之间的理论扩散距离的图。
图3是示出了应用了本发明的半导体装置的构造示例的剖视图。
图4是示出了用于制造图3中的半导体装置的方法的流程图。
图5是在制造步骤中的半导体装置的剖视图。
图6是在制造步骤中的半导体装置的剖视图。
图7是示出了在150℃高温搁置时间下的Kelvin电阻测量结果的图。
图8是示出了第一、第二、第三金属层的材料和厚度的示例的图。
图9是应用了本发明的半导体装置的第一变型例的剖视图。
图10是应用了本发明的半导体装置的第二变型例的剖视图。
图11是示出了凸块焊盘和微凸块的直径与凸块电容之间的关系的图。
图12是示出了凸块焊盘和微凸块的直径与电阻值之间的关系的图。
图13是示出了半导体装置的第二变型例的应用示例的框图。
图14是示出了应用了本发明的半导体装置在被应用于堆叠型CMOS图像传感器的情况下在堆叠之前的状态的剖视图。
图15是示出了应用了本发明的半导体装置在被应用于堆叠型CMOS图像传感器的情况下在堆叠之后的状态的剖视图。
图16是示出了I/O与形成在逻辑芯片上的WB焊盘连接的状态的剖视图。
图17是示出了与凸块焊盘的形成有关的变型例的剖视图。
图18是示出了与凸块焊盘的形成有关的变型例的剖视图。
图19是示出了与凸块焊盘的形成有关的变型例的剖视图。
具体实施方式
在下文中，参照附图来详细说明用于实施本发明的最佳方式(在下文中称为实施例)。
<半导体装置的构造示例>
图3是示出了作为本发明实施例的半导体装置的构造示例的剖视图。注意，该图仅示出了要被堆叠起来的且通过Sn基焊料电气地相互连接的第一半导体元件和第二半导体元件之中的、未形成有微凸块的第一半导体元件侧。
同时，Sn基表示该焊料的材料包括SnAg基、SnBi基、SnCu基、SnIn基、SnAgCu基等。
如图所述，在第一半导体元件10上设置有作为电极的Al焊盘11(或者触点，或者至少一个触点)，Al焊盘11的一部分被形成到用于与第二半导体元件上的微凸块连接的开口部21(图5)中，并且，在开口部21上依次形成有第一金属层13、第二金属层14和第三金属层15。在除开口部21以外的部分上形成有SiO2层(或者绝缘层)12，并且在SiO2层12上形成有SiN层16。为了方便说明，层13、层14和层15在这里分别称为第一、第二和第三金属层。然而，各示例性实施例不限于此。例如，取决于实施例，第一金属层13可以被称为第二金属层或者第三金属层，第二金属层14可以被称为第一金属层或者第三金属层，并且第三金属层15可以被称为第一金属层或者第二金属层。相同的原则也适用于本发明中的被描述为第一、第二、第三等的其他元件。
作为阻挡金属的第一金属层13例如采用TiN。第一金属层13的平均厚度被设定为大约10nm以上。据此，就使得能够在尤其可以降低微尘粒子风险的晶片加工流水线中形成第一金属层13。第一金属层也可以采用Ta或者TaN。
通过设置第一金属层(阻挡金属)13，可以防止Al焊盘11与第二金属层14之间的反应以及可能因第二半导体元件的用于形成微凸块的Sn基焊料和第二金属层14之间的反应而产生的合金层与Al焊盘11之间的反应。据此，预期能够改善半导体装置的可靠性和电气特性。此外，也可以省略第一金属层13。
第二金属层14采用具有针对Sn基焊料的相图且具有低扩散性的材料，例如Co。第二金属层14的平均厚度被设定为大约15nm以上。据此，就使得能够在尤其可以降低微尘粒子风险的晶片加工流水线中形成第二金属层14。
第三金属层15采用可以通过免清洗助焊剂(non-cleaning flux)和还原气体等来还原第二金属层14的表面上的表面氧化膜、且对Sn具有高扩散性的材料，例如Cu。第三金属层15的平均厚度被设定为大约80nm以上，从而防止第二金属层14的氧化。除了可以采用Cu外，第三金属层15也可以采用Ni、Pd、Au、或Pt等。
通过采用上述的构造，即使在第二金属层14的材料采用了极容易被氧化、且相对较难还原的Co时，Sn基焊料和第二金属层14之间的接触(反应)也变得更容易了。另外，通过采用Co作为第二金属层14，可以改善可靠性和电气特性。
<用于制造半导体装置的方法>
下面，参照附图4到图6来说明用于制造图3所示的半导体装置的方法。
图4是示出了用于制造图3中的半导体装置的方法的流程图。图5和图6是示出了制造处理的半导体装置的剖视图。
在步骤S1中，如图5中的A所示，在设置有作为电极的Al焊盘11的第一半导体元件10上形成SiO2层12。然后，在SiO2层12上，根据在下文中所说明的开口部21的位置和直径，设置用于保护除开口部21以外的部分的抗蚀剂图案(未图示)。另外，如图5中的B所示，通过干蚀刻来磨削SiO2层12直到使Al焊盘11露出，由此提供开口部21。
在步骤S2中，如图5中的C所示，通过溅射法来形成第一金属层(TiN)13、第二金属层(Co)14和第三金属层(Cu)15。然后，在步骤S3中，如图5中的D所示，通过与第三金属层15的材料相同的材料(在这种情况下，铜)的电镀过程来增加第三金属层15的厚度，并且用该第三金属层15填充开口部21的凹陷部。换句话说，第三金属层15是通过第一沉积过程和第二沉积过程来形成的。第一沉积过程形成第三金属层15的一部分且该部分为凹陷形状，并且第二沉积过程形成第三金属膜15的剩余部分以填充该凹陷形状。
在步骤S4中，如图5中的E所示，除开口部21以外的部分上的第三金属层15和第二金属层14通过化学机械研磨(CMP；chemical mechanical polishing)而被去除或者被平面化。在步骤S5中，在整个表面上形成作为钝化层的SiN层16，并且，为了Tr损伤恢复，实施例如400℃/1h的退火处理。进一步地，在SiN层16上设置抗蚀剂图案(未图示)，并且如图6中的A中所示，通过干蚀刻来磨削SiN层16，直到开口部21上的第三金属层15露出。据此，开口部21具有凹陷结构，以使得与由Sn基焊料制成的、且在第二半导体元件23上形成的微凸块24之间的位置定位变得容易。在下文中，与微凸块24相对的开口部21也称为凸块焊盘21(或者至少一个凸块焊盘)。
在步骤S6中，如图6中的B所示，使在第二半导体元件23上形成的微凸块24与凸块焊盘21的第三金属层15接触，并且在诸如甲酸等还原氛围下通过热处理来还原第三金属层15的表面上和用于形成微凸块24的Sn基焊料的表面上的氧化膜。随后，在步骤S7中，如图6中的C所示，第三金属层15扩散至Sn基焊料中并且Sn基焊料与第二金属层14发生接触(反应)，从而建立起第一半导体元件10的作为电极的Al焊盘11与第二半导体元件23的电极之间的连接。该制造方法的说明由此结束。
<在高温搁置时间下的Kelvin电阻测量结果>
下面，图7示出了在第一金属层13、第二金属层14和第三金属层15分别采用TiN、Co和Cu的情况下，当第二金属层14被连接到由Sn基焊料制成的微凸块24时在150℃高温搁置时间下的Kelvin电阻测量结果。
如图所示，电阻值在经过504个小时后没有变化。因此，第一半导体元件10的电极和第二半导体元件23的电极之间的电气连接随着时间的流逝也仍然维持着。
<第一金属层13、第二金属层14和第三金属层15的材料及厚度>
下面，图8示出了在第二金属层14的厚度以及第三金属层15的材料和厚度发生变化的情况下，第一至第四实例和各比较例(PTL 1中所公开的构造)中的评估。
在第一实例中，第一金属层13、第二金属层14和第三金属层15分别采用20nm的TiN、270nm的Co和200nm的Cu。在第二实例中，第一金属层13、第二金属层14和第三金属层15分别采用20nm的TiN、100nm的Co和200nm的Cu。在第三实例中，第一金属层13、第二金属层14和第三金属层15分别采用20nm的TiN、30nm的Co和200nm的Cu。在第四实例中，第一金属层13、第二金属层14和第三金属层15分别采用20nm的TiN、270nm的Co和80nm的Cu。
在第一至第四实例中的任一者中，可连接性和高温搁置实验的结果都不存在问题，并且建立了第一半导体元件10的电极和第二半导体元件23的电极之间的物理的且电气的连接。同时，在比较例1中，在为了Tr损伤恢复而引入的烧结退火处理的期间，第一金属层Ti扩散到第二金属层的Co中，因而阻碍了与焊料的可连接性。在比较例2中，第一金属层TiN和焊料之间的可连接性没有建立起来。在比较例3中，甚至在第二金属层Co被设定为10nm的情况下，也没有确保与焊料的可连接性。
<半导体装置的第一变型例>
图9是示出了作为本发明实施例的半导体装置的第一变型例的剖视图。
该第一变型例是通过从图3中的构造示例中省略了第一金属层13而得到的。据此，可以缩短工艺周期时间，并且可以降低成本。
<半导体装置的第二变型例>
下面，图10是示出了作为本发明实施例的半导体装置的第二变型例的剖视图。
第二变型例是通过使设置在第一半导体元件10上的凸块焊盘21的直径根据待连接的电极(线)的用途来改变而得到的。设置在第一半导体元件10上的两个凸块焊盘21被形成为：凸块焊盘21-2具有比凸块焊盘21-1的直径大的直径。
此外，可以通过改变在上述制造处理的步骤S1中在SiO2层12上设置的抗蚀剂图案和在步骤S5中在SiN层16上设置的抗蚀剂图案，来容易地改变设置在同一基板(在这种情况下，第一半导体元件10)上的多个凸块焊盘21的直径。
另一方面，第二半导体元件的由Sn基焊料制成的微凸块24的直径也根据相应的凸块焊盘21的直径而改变。
<根据凸块焊盘21及微凸块24的直径的差异的凸块电容的变化>
图11示出了根据凸块焊盘21的直径(开口部直径)和微凸块的直径的差异的凸块电容的变化。
如图所示，当凸块焊盘21和微凸块24具有小的直径的情况与凸块焊盘21和微凸块24具有大的直径的情况相比较时，凸块电容在凸块焊盘21和微凸块24具有小的直径的情况下是较小的。因此，当通过利用直径小的凸块焊盘21和微凸块24来连接信号线时，预期能够改善用于通信的电气信号的信号特性。另外，在这种情况下，待连接的布线的排布是容易的。
<根据凸块焊盘21及微凸块24的直径的差异的电阻值的变化>
图12示出了根据凸块焊盘21的直径(开口部直径)和微凸块24的直径的差异的电阻值的变化。
如图所示，凸块焊盘21和微凸块24的直径越大，则电阻值越小。因此，当通过利用直径较大的凸块焊盘21和微凸块24来连接电源线时，可以防止例如IR降(IR drop)等与电力供应有关的缺陷。
<半导体装置的第二变型例的应用示例>
下面，图13示出了图10所示的第二构造示例的应用示例。
在该应用示例中，用于将第一半导体元件10的电源单元31和第二半导体元件23的电源单元33连接起来的电源线35是通过利用具有较大直径的凸块焊盘21-2和微凸块24来进行连接的。另外，用于将第一半导体元件10的信号处理器32和第二半导体元件23的信号处理器34连接起来的信号线36和37是通过利用具有较小直径的凸块焊盘21-1和微凸块24来进行连接的。
根据图13所示的应用示例，能够改善在第一半导体元件10和第二半导体元件23之间通信的电气信号的信号特性，并且能够抑制例如IR降等与电力供应有关的缺陷。
<半导体装置的应用示例>
下面，将会说明根据本发明实施例的半导体装置在被应用于堆叠型CMOS图像传感器(在下文中，称为堆叠型CIS)的情况下的构造示例。
图14示出了应用了本发明实施例的半导体装置的堆叠型CIS在堆叠之前的状态，并且图15示出了该堆叠型CIS在堆叠之后的状态。
也就是说，该堆叠型CIS被形成得具有如下形式：在像素基板51上形成有用于执行光电转换的像素单元，用于处理从像素基板51输出的像素信号的逻辑芯片52通过晶片上芯片(CoW)连接而被堆叠在像素基板51上。
像素基板51相当于第一半导体元件10，将要与逻辑芯片52的微凸块24连接的凸块焊盘21被形成在像素基板51的光入射侧的表面上。另一方面，逻辑芯片52相当于第二半导体元件23，微凸块24被形成在逻辑芯片52的与像素基板51连接的表面上。
在凸块焊盘21和微凸块24以相互接触的方式进行堆叠的状态下，对像素基板51和逻辑芯片52进行热处理，以使得像素基板51和逻辑芯片52电气地相互连接。同时，如图16所示，在逻辑芯片52的与像素基板51连接的表面的相反表面上形成有WB焊盘71，并且I/O 72连接到WB焊盘71。
如图所示，通过将根据本发明实施例的半导体装置应用于堆叠型CMOS图像传感器，能够防止像素单元中的诸如灰尘缺陷等损害，该损害是当微凸块也被形成于像素基板51侧以供连接的时候会发生的。另外，像素基板51和逻辑芯片52被堆叠起来的高度能够降低，并且能够防止CF的扫除不均匀性(sweeping unevenness)。
<与凸块焊盘的形成有关的变型例>
下面，将会说明与凸块焊盘的形成有关的变型例。
图17示出了如下变型例：其中，在像素基板51中形成有贯通电极81的情况下，在贯通电极81的位置处形成有开口部21，并且贯通电极81成为与逻辑芯片52的微凸块24对应的凸块焊盘。当贯通电极81自身成为凸块焊盘时，可以省略第一、第二、第三金属层13～15的形成。
图18和图19示出了如下变型例：其中，从像素基板51(第一半导体元件10)中省略了Al焊盘11，开口部21被形成得到达像素基板51中的金属布线(Cu布线)91，并且该像素基板中的金属布线91成为与逻辑芯片52的微凸块24对应的凸块焊盘。
在省略了Al焊盘11并且像素基板51中的金属布线91成为凸块焊盘的情况下，可以改善定制工序(custom process)中的扫除不均匀性，并且可以实现芯片收缩(chipshrink)。另外，还可以降低逻辑芯片52的高度。
另外，根据本发明实施例的半导体装置除了可以应用于上述堆叠型CIS以外，也可以应用于其中把被堆叠的半导体元件的电极相互连接的所有类型的电子设备。
本发明的实施例不限于上述实施例，并且本发明的实施例可以在不脱离本发明的范围的前提下进行各种变化。
同时，本发明可以被设计成如下技术方案。
(1)一种半导体装置，所述半导体装置具有第一半导体元件，所述第一半导体元件包括至少一个具有凹陷形状的凸块焊盘，其中，所述至少一个凸块焊盘包括第一金属层和所述第一金属层上的第二金属层。所述半导体装置包括第二半导体元件，所述第二半导体元件包括至少一个电极。所述半导体装置包括微凸块，所述微凸块将所述至少一个凸块焊盘和至少一个电极电气地连接，其中，所述微凸块包括所述第二金属层的扩散部，并且其中，所述第一半导体元件或者所述第二半导体元件包括像素单元。
(2)根据上述(1)所述的半导体装置，
其中，所述微凸块包括Sn基焊料，并且所述第一金属层包括Co。
(3)根据上述(1)或(2)所述的半导体装置，
其中，所述至少一个凸块焊盘包括具有不同直径的多个凸块焊盘，并且，
其中，所述至少一个电极包括对应于所述多个凸块焊盘的多个电极。
(4)根据上述(1)到(3)中任一项所述的半导体装置，
其中，所述不同直径是根据待连接的所述多个电极的用途而彼此不同的。
(5)根据上述(1)到(4)中任一项所述的半导体装置，
其中，所述微凸块的直径对应于所述至少一个凸块焊盘的直径。
(6)根据上述(1)到(5)中任一项所述的半导体装置，
其中，所述至少一个凸块焊盘包括第三金属层，并且
其中，所述第一金属层在所述第三金属层上。
(7)根据上述(1)到(6)中任一项所述的半导体装置，
其中，所述第一金属层的平均厚度是15nm以上。
(8)根据上述(1)到(7)中任一项所述的半导体装置，
其中，所述第三金属层的平均厚度为10nm以上。
(9)根据上述(1)到(8)中任一项所述的半导体装置，
其中，所述第三金属层由TiN、Ta或者TaN形成。
(10)根据上述(1)到(9)中任一项所述的半导体装置，
其中，所述第二金属层由Cu、Co、Ni、Pd、Au或者Pt形成。
(11)根据上述(1)所述的半导体装置，
其中，所述至少一个凸块焊盘是在所述第一半导体元件的表面上设置的用于将所述微凸块连接到所述第一半导体元件中的贯通电极的开口部。
(12)根据上述(1)所述的半导体装置，
其中，所述至少一个凸块焊盘是在所述第一半导体元件的表面上设置的用于将所述微凸块连接到所述第一半导体元件中的金属布线的开口部。
(13)根据上述(1)所述的半导体装置，
其中，所述第一半导体元件是所述像素单元，并且所述第二半导体元件是通过晶片上芯片连接(CoW连接)而被连接到所述第一半导体元件的逻辑芯片。
(14)一种用于制造半导体装置的方法，包括：
在第一基板上形成至少一个触点；
在所述至少一个触点上形成绝缘层；
蚀刻所述绝缘层，以提供使所述至少一个触点的一部分露出的至少一个开口部；
在所述开口部中形成至少一个凸块焊盘，且所述至少一个凸块焊盘具有凹陷形状；并且
通过使所述至少一个凸块焊盘的一部分扩散至与第二基板的电极连接的微凸块中，将所述至少一个凸块焊盘电气地连接到所述第二基板的所述电极。
(15)根据上述(14)所述的方法，其中，形成所述至少一个凸块焊盘的步骤包括：
在所述至少一个触点上形成第一金属层；和
在所述第一金属层上形成第二金属层，
其中所述至少一个凸块焊盘的扩散部包括所述第二金属层。
(16)根据上述(15)所述的方法，其中，形成所述第二金属层的步骤包括：
根据第一沉积过程形成所述第二金属层的一部分，该部分为凹陷形状；并且
根据第二沉积过程形成所述第二金属层的剩余部分，以填充所述凹陷形状。
(17)根据上述(15)所述的方法，其中，形成所述至少一个凸块焊盘的步骤包括：
在形成所述第一金属层和所述第二金属层之前，在所述绝缘层上形成第三金属层。
(18)根据上述(17)所述的方法，其中，形成所述至少一个凸块焊盘的步骤包括：
将所述第一金属层、所述第二金属层和所述第三金属层平面化，由此使所述第一金属层、所述第二金属层和所述第三金属层的上表面与所述绝缘层的上表面是共面的。
(19)根据上述(18)所述的方法，
其中，所述第二金属层扩散至所述微凸块中，以使所述微凸块的顶部延伸超过所述绝缘层的所述上表面，而所述微凸块的其他部分存在于所述绝缘层的所述上表面与所述电极之间的空间中。
(20)根据上述(18)所述的方法，其中，形成所述至少一个凸块焊盘的步骤包括：
在所述绝缘层以及所述第一金属层、所述第二金属层和所述第三金属层上形成钝化层；并且
蚀刻所述钝化层，以使所述第二金属层露出，并且产生凹陷形状。
(21)一种半导体装置，由堆叠起来的半导体元件形成，其中，对置的半导体元件的电极电气地相互连接，
其中，第二半导体元件是所述对置的半导体元件中的一者，在所述第二半导体元件的电极上形成有由Sn基焊料制成的微凸块，并且，
第一半导体元件是所述对置的半导体元件中的另一者、且经由所述微凸块与所述第二半导体元件的所述电极连接，在所述第一半导体元件的电极上形成有与所述微凸块相对的凹陷状凸块焊盘。
(22)根据上述(21)所述的半导体装置，
其中，在所述凸块焊盘上，从所述微凸块侧依次形成有：扩散到所述微凸块中的第三金属层；和由Co形成的第二金属层。
(23)根据上述(21)或(22)所述的半导体装置，
其中，在所述第一半导体元件上设置有具有不同直径的多个凸块焊盘。
(24)根据上述(21)到(23)中任一项所述的半导体装置，
其中，所述凸块焊盘的直径是根据待连接的电极的用途而彼此不同的。
(25)根据上述(21)到(24)中任一项所述的半导体装置，
其中，所述第二半导体元件的所述微凸块的直径对应于相应的所述第一半导体元件的所述凸块焊盘的直径。
(26)根据上述(21)到(25)中任一项所述的半导体装置，
其中，在所述凸块焊盘上，从所述微凸块侧依次形成有所述第三金属层、所述第二金属层和由TiN形成的第一金属层。
(27)根据上述(21)到(26)中任一项所述的半导体装置，
其中，所述第二金属层的平均厚度为15nm以上。
(28)根据上述(21)到(27)中任一项所述的半导体装置，
其中，所述第一金属层的平均厚度为10nm以上。
(29)根据上述(21)到(28)中任一项所述的半导体装置，
其中，所述第一金属由TiN、Ta或者TaN形成。
(30)根据上述(21)到(29)中任一项所述的半导体装置，
其中，所述第三金属层由Cu、Ni、Pd、Au或者Pt形成。
(31)根据上述(21)所述的半导体装置，
其中，所述凸块焊盘由被设置为从所述第一半导体元件的表面到所述第一半导体元件中的贯通电极的开口部形成。
(32)根据上述(21)所述的半导体装置，
其中，所述凸块焊盘由被设置为从所述第一半导体元件的表面到所述第一半导体元件中的金属布线的开口部形成。
(33)根据上述(21)所述的半导体装置，其是堆叠型CMOS图像传感器，其中，相当于所述第二半导体元件的逻辑芯片通过CoW连接而被连接到相当于所述第一半导体元件的像素基板。
(34)一种用于制造半导体装置的制造设备的制造方法，所述半导体装置由堆叠起来的半导体元件形成，在所述半导体装置中，对置的半导体元件的电极电气地相互连接，所述制造方法包括：
通过所述制造设备来形成微凸块的步骤，用于在第二半导体元件的电极上形成由Sn基焊料制成的微凸块，所述第二半导体元件是所述对置的半导体元件中的一者；和
通过所述制造设备来形成凸块焊盘的步骤，用于在第一半导体元件的电极上形成与所述微凸块相对的凹陷状凸块焊盘，所述第一半导体元件是所述对置的半导体元件中的另一者、且经由所述微凸块与所述第二半导体元件的所述电极连接。
(35)根据上述(34)所述的制造方法，其中，在形成所述凸块焊盘的步骤中，
在作为所述对置的半导体元件中的另一者、且经由所述微凸块与所述第二半导体元件的所述电极连接的所述第一半导体元件的所述电极上形成由Co形成的第二金属层；
在所述第二金属层上形成将要扩散到所述微凸块中的第三金属层；以及
使所述微凸块与所述第三金属层接触，在还原氛围下通过热处理来还原所述第三金属层的表面上和所述微凸块的表面上的氧化膜，且使所述第三金属层扩散至所述微凸块中，由此，就使得所述微凸块与所述第二金属层接触，并且将所述第一半导体元件的所述电极和所述第二半导体元件的所述电极电气地连接。
(36)根据上述(35)所述的制造方法，其中，在形成所述凸块焊盘的步骤中，
在所述第一半导体元件的所述第三金属层上还形成钝化层，并且蚀刻所述钝化层以提供使所述第三金属层露出的开口部。
(37)根据上述(35)所述的制造方法，其中，在形成所述凸块焊盘的步骤中，
在形成所述第二金属层之前，在作为所述对置的半导体元件中的另一者、且经由所述微凸块与所述第二半导体元件的所述电极连接的所述第一半导体元件的所述电极上还形成由TiN形成的第一金属层。
(38)根据上述(34)所述的制造方法，其中，在形成所述凸块焊盘的步骤中，
通过设置从所述第一半导体元件的表面到所述第一半导体元件中的贯通电极的开口部来形成所述凸块焊盘。
(39)根据上述(34)所述的制造方法，其中，在形成所述凸块焊盘步骤中，
通过设置从所述第一半导体元件的表面到所述第一半导体元件中的金属布线的开口部来形成所述凸块焊盘。
附图标记列表
10 第一半导体元件
11 Al焊盘
12 SiO2层
13 第一金属层
14 第二金属层
15 第三金属层
16 SiN层
21 开口部(凸块焊盘)
23 第二半导体元件
24 微凸块
31 电源单元
32 信号处理器
33 电源单元
34 信号处理器
35 电源线
36、37 信号线
51 像素基板
52 逻辑芯片
81 贯通电极
91 Cu布线。

Claims (20)

1.一种摄像装置，包括：
第一基板，所述第一基板包括一个或多个像素；
触点，所述触点被布置在所述第一基板上，并且包括面对所述第一基板的第一表面和与所述第一表面相对的第二表面；
第一绝缘层，所述第一绝缘层在所述第一基板上，并且包括在所述触点的所述第二表面上方的开口；
至少一个凸块焊盘，所述至少一个凸块焊盘包括：
第一金属层，所述第一金属层被布置在所述第一绝缘层的所述开口中，并且电连接至所述触点；和
第二金属层，所述第二金属层在所述第一金属层上，并且被布置在所述第一绝缘层的所述开口中；
第二绝缘层，所述第二绝缘层在所述第一绝缘层上，并且包括所述第二金属层上方的开口；
第二基板，所述第二基板包括逻辑电路和至少一个电极；以及
微凸块，所述微凸块将所述至少一个凸块焊盘电连接至所述至少一个电极，并且位于所述第二绝缘层的所述开口中。
2.根据权利要求1所述的摄像装置，
其中，所述微凸块包括所述第二金属层的扩散部，并且
其中，所述微凸块包括Sn基焊料，并且所述第一金属层包括Co。
3.根据权利要求1或2所述的摄像装置，
其中，所述至少一个凸块焊盘包括具有不同直径的多个凸块焊盘，并且
其中，所述至少一个电极包括对应于所述多个凸块焊盘的多个电极。
4.根据权利要求3所述的摄像装置，
其中，所述不同直径是根据待连接到对应的凸块焊盘的所述多个电极的用途而彼此不同的。
5.根据权利要求1或2所述的摄像装置，
其中，所述微凸块的直径对应于所述至少一个凸块焊盘的直径。
6.根据权利要求1或2所述的摄像装置，
其中，所述至少一个凸块焊盘包括第三金属层，所述第三金属层被布置在所述第一绝缘层的所述开口中，并且
其中，所述第一金属层在所述第三金属层上。
7.根据权利要求6所述的摄像装置，
其中，所述第一金属层的平均厚度为15nm以上。
8.根据权利要求6所述的摄像装置，
其中，所述第三金属层的平均厚度为10nm以上。
9.根据权利要求6所述的摄像装置，
其中，所述第三金属层包括TiN、Ta或者TaN。
10.根据权利要求6所述的摄像装置，
其中，所述第二金属层包括Cu、Ni、Pd、Au或者Pt。
11.根据权利要求1或2所述的摄像装置，
其中，所述第二金属层的表面与所述第一绝缘层的表面是共面的。
12.根据权利要求1或2所述的摄像装置，
其中，所述第一绝缘层接触所述触点的所述第二表面。
13.根据权利要求1或2所述的摄像装置，
其中，所述至少一个凸块焊盘被布置在所述第一基板的包括所述一个或多个像素的区域的外部。
14.一种半导体装置，包括：
第一基板；
触点，所述触点被布置在所述第一基板上，并且包括面对所述第一基板的第一表面和与所述第一表面相对的第二表面；
第一绝缘层，所述第一绝缘层在所述第一基板上，并且包括在所述触点的所述第二表面上方的开口；
至少一个凸块焊盘，所述至少一个凸块焊盘包括：
第一金属层，所述第一金属层被布置在所述第一绝缘层的所述开口中，并且电连接至所述触点；和
第二金属层，所述第二金属层在所述第一金属层上，并且被布置在所述第一绝缘层的所述开口中；
第二绝缘层，所述第二绝缘层在所述第一绝缘层上，并且包括所述第二金属层上方的开口；
第二基板，所述第二基板包括至少一个电极；以及
微凸块，所述微凸块将所述至少一个凸块焊盘电连接至所述至少一个电极，并且位于所述第二绝缘层的所述开口中。
15.根据权利要求14所述的半导体装置，
其中，所述微凸块包括所述第二金属层的扩散部，并且
其中，所述微凸块包括Sn基焊料，并且所述第一金属层包括Co。
16.根据权利要求14或15所述的半导体装置，
其中，所述至少一个凸块焊盘包括具有不同直径的多个凸块焊盘，并且
其中，所述至少一个电极包括对应于所述多个凸块焊盘的多个电极。
17.根据权利要求16所述的半导体装置，
其中，所述不同直径是根据待连接到对应的凸块焊盘的所述多个电极的用途而彼此不同的。
18.根据权利要求14或15所述的半导体装置，
其中，所述微凸块的直径对应于所述至少一个凸块焊盘的直径。
19.根据权利要求14或15所述的半导体装置，
其中，所述至少一个凸块焊盘包括第三金属层，所述第三金属层被布置在所述第一绝缘层的所述开口中，并且
其中，所述第一金属层在所述第三金属层上。
20.根据权利要求14或15所述的半导体装置，
其中，所述第一金属层的平均厚度为15nm以上。
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