TWI712100B - Electronic parts packaging device - Google Patents
Electronic parts packaging device Download PDFInfo
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- TWI712100B TWI712100B TW108126041A TW108126041A TWI712100B TW I712100 B TWI712100 B TW I712100B TW 108126041 A TW108126041 A TW 108126041A TW 108126041 A TW108126041 A TW 108126041A TW I712100 B TWI712100 B TW I712100B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 306
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000004065 semiconductor Substances 0.000 abstract description 41
- 238000009434 installation Methods 0.000 abstract description 8
- 235000012431 wafers Nutrition 0.000 description 39
- 238000012856 packing Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67703—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
- H01L21/67721—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations the substrates to be conveyed not being semiconductor wafers or large planar substrates, e.g. chips, lead frames
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
- H05K13/04—Mounting of components, e.g. of leadless components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
- H05K13/04—Mounting of components, e.g. of leadless components
- H05K13/0404—Pick-and-place heads or apparatus, e.g. with jaws
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Supply And Installment Of Electrical Components (AREA)
- Wire Bonding (AREA)
Abstract
本發明於包括多個封裝頭的電子零件封裝裝置中,實現設置空間的減少及封裝精度的提高。將半導體晶片16封裝於基板15的接合裝置100包括:共通的線性引導件20,於Y方向延伸;多個封裝頭21a、封裝頭21b,於Y方向排列配置,且被線性引導件20引導而於Y方向移動;以及控制部50,調整封裝頭21a、封裝頭21b的Y方向的位置;並且控制部50使封裝頭21a、封裝頭21b朝向同一方向而同時起動,且使封裝頭21a、封裝頭21b同時停止。The invention realizes the reduction of the installation space and the improvement of the packaging accuracy in an electronic part packaging device including a plurality of packaging heads. The bonding device 100 for packaging the semiconductor chip 16 on the substrate 15 includes a common linear guide 20 extending in the Y direction; a plurality of packaging heads 21a and 21b are arranged in the Y direction and are guided by the linear guide 20 Move in the Y direction; and the control unit 50 adjusts the positions of the packaging head 21a and the packaging head 21b in the Y direction; and the control unit 50 causes the packaging head 21a and the packaging head 21b to face in the same direction while starting, and causes the packaging head 21a and the packaging The head 21b stops at the same time.
Description
本發明是有關於一種電子零件封裝裝置的結構。The invention relates to a structure of an electronic component packaging device.
作為將電子零件封裝於基板的封裝裝置,使用如下封裝裝置,其包括:拾取部,從晶圓拾取(pick up)半導體晶片(semiconductor die)而載置於中間平台;以及接合(bonding)部,從中間平台上拾取半導體晶片而移送至基板上,且接合於基板上。As a packaging device for packaging electronic parts on a substrate, the following packaging device is used, which includes: a pick-up part, which picks up a semiconductor die from a wafer and places it on an intermediate platform; and a bonding part, The semiconductor wafer is picked up from the intermediate platform, transferred to the substrate, and bonded to the substrate.
另外,封裝裝置中,亦提出有包括兩個拾取部、接合部,交替進行拾取及接合而縮短接合時間的裝置(例如參照專利文獻1)。 [現有技術文獻] [專利文獻]In addition, in the packaging device, there has also been proposed a device that includes two pick-up parts and a bonding part, and alternately performs pick-up and bonding to shorten bonding time (for example, refer to Patent Document 1). [Prior Art Literature] [Patent Literature]
[專利文獻1]日本專利特開2009-130583號公報[Patent Document 1] Japanese Patent Laid-Open No. 2009-130583
[發明所欲解決之課題][The problem to be solved by the invention]
但是,專利文獻1所記載的封裝裝置中,由於將兩個封裝頭排列配置在與支持臂正交的方向,故而需要大的設置空間。另外,由於交替進行拾取及接合,故而存在如下情況:於其中一個封裝頭的接合中,由其他封裝頭的動作所引起的振動產生干擾而對封裝精度造成影響。該影響於為了縮短封裝時間而使封裝頭高速移動的情況下,變得更顯著。However, in the packaging device described in Patent Document 1, since the two packaging heads are arranged in a direction orthogonal to the support arm, a large installation space is required. In addition, since picking and bonding are performed alternately, there is a situation in which, during bonding of one of the packaging heads, vibration caused by the actions of the other packaging heads interferes and affects the packaging accuracy. This effect becomes more pronounced when the packaging head is moved at a high speed in order to shorten the packaging time.
因此,本發明的目的為於包括多個封裝頭的電子零件封裝裝置中,實現設置空間的減少及封裝精度的提高。 [解決課題之手段]Therefore, the object of the present invention is to reduce the installation space and improve the packaging accuracy in an electronic component packaging device including a plurality of packaging heads. [Means to solve the problem]
本發明的電子零件封裝裝置是將電子零件封裝於基板或者其他電子零件的電子零件封裝裝置,包括:線性引導件(linear guide),於規定方向延伸;多個封裝頭,於規定方向排列配置,且被線性引導件引導而於規定方向移動;以及控制部,調整封裝頭的規定方向的位置;並且控制部使各個封裝頭朝向同一方向而同時起動,且使各個封裝頭同時停止。The electronic component packaging device of the present invention is an electronic component packaging device that encapsulates electronic components on a substrate or other electronic components, and includes: a linear guide extending in a predetermined direction; a plurality of packaging heads arranged in a predetermined direction, It is guided by the linear guide to move in a predetermined direction; and the control unit adjusts the position of the packaging head in the predetermined direction; and the control unit makes the packaging heads start in the same direction and simultaneously starts, and stops the packaging heads at the same time.
如上所述,藉由將封裝頭於規定方向排列配置,可實現設置空間的減少。另外,藉由使多個封裝頭同時起動、停止,可抑制由各封裝頭的動作所引起的振動的干擾,可提高封裝品質。As described above, by arranging the packaging heads in a predetermined direction, the installation space can be reduced. In addition, by starting and stopping a plurality of packaging heads at the same time, the interference of vibration caused by the operation of each packaging head can be suppressed, and the packaging quality can be improved.
本發明的電子零件封裝裝置中亦可設為:各個封裝頭安裝有將電子零件拾取及封裝的封裝噴嘴,且於封裝噴嘴拾取電子零件的拾取位置、與封裝頭的封裝噴嘴將電子零件進行封裝的封裝位置之間,於規定方向移動,並且控制部使各個封裝頭從各個拾取位置或者各個封裝位置,朝向同一方向而同時起動,且使各個封裝頭同時到達各個封裝位置或者各個拾取位置而同時停止。The electronic component packaging device of the present invention can also be configured as: each packaging head is equipped with a packaging nozzle for picking up and packaging electronic parts, and the picking position of the packaging nozzle picks up the electronic parts, and the packaging nozzle of the packaging head encapsulates the electronic parts Between the packaging positions, move in a predetermined direction, and the control unit makes each packaging head from each pickup position or each packaging position, facing the same direction and start at the same time, and makes each packaging head reach each packaging position or each pickup position at the same time stop.
由於控制部使各封裝頭從拾取位置或者封裝位置,朝向同一方向而同時起動,同時到達封裝位置或者拾取位置而同時停止,故而可於其中一個封裝頭的拾取動作或者封裝動作中,抑制由其他封裝頭的移動所造成的振動產生干擾而對封裝精度造成影響。Since the control unit causes the packaging heads to start in the same direction from the pickup position or the packaging position at the same time, reach the packaging position or the pickup position at the same time and stop at the same time, it is possible to suppress the pick-up or packaging operation of one of the packaging heads. The vibration caused by the movement of the packaging head interferes and affects the packaging accuracy.
本發明的電子零件封裝裝置中亦可設為:包括多個封裝平台,於上表面保持封裝電子零件的基板或者封裝有其他電子零件的基板,並且各個拾取位置與各個封裝平台之間的規定方向的距離相等。The electronic component packaging device of the present invention can also be configured to include a plurality of packaging platforms, holding a substrate for packaging electronic parts or a substrate for packaging other electronic parts on the upper surface, and a predetermined direction between each pickup position and each packaging platform The distances are equal.
藉由該構成,可使拾取位置與封裝位置之間的距離相同,可使多個封裝頭同時起動、停止而提高封裝品質。With this configuration, the distance between the pick-up position and the packaging position can be made the same, and multiple packaging heads can be started and stopped at the same time to improve packaging quality.
本發明的電子零件封裝裝置中亦可設為:基板於規定方向封裝有多個電子零件,並且控制部是以各個拾取位置與各個封裝位置之間的各個距離成為相等的方式,使各個封裝頭移動而將多個電子零件進行封裝。The electronic component packaging device of the present invention may also be configured such that the substrate is packaged with a plurality of electronic components in a predetermined direction, and the control unit makes each packaging head equal to each distance between each pickup position and each packaging position. Move and encapsulate multiple electronic parts.
藉此,於在基板的規定方向封裝多個電子零件的情況下,亦可使拾取位置與封裝位置之間的距離相同,因此可使多個封裝頭同時起動、停止而提高封裝品質。With this, when multiple electronic components are packaged in a predetermined direction of the substrate, the distance between the pick-up position and the packaging position can be made the same. Therefore, multiple packaging heads can be started and stopped at the same time to improve the packaging quality.
本發明的電子零件封裝裝置中,於各個拾取位置與各個封裝位置之間的各個距離不同的情況下,亦可使距離短的一方的封裝頭的移動速度較距離長的一方的封裝頭的移動速度更緩慢。In the electronic component packaging device of the present invention, when the respective distances between the pick-up positions and the respective packaging positions are different, the movement speed of the packaging head of the shorter distance may be made to move the packaging head of the longer distance The speed is slower.
藉此,即便於拾取位置與封裝位置之間的各個距離不同的情況下,亦可使多個封裝頭同時起動、停止,可提高封裝品質。 [發明的效果]Thereby, even when the respective distances between the pickup position and the packaging position are different, multiple packaging heads can be started and stopped at the same time, which can improve packaging quality. [Effects of the invention]
本發明於包括多個封裝頭的電子零件封裝裝置中,可實現設置空間的減少及封裝精度的提高。In an electronic component packaging device including a plurality of packaging heads, the present invention can reduce the installation space and improve the packaging accuracy.
以下,一面參照圖式,一面對實施方式的電子零件封裝裝置即接合裝置100進行說明。接合裝置100將作為電子零件的半導體晶片16封裝於基板15或者其他半導體晶片16。Hereinafter, while referring to the drawings, the
如圖1所示,接合裝置100包括:基座10;共通的線性引導件20,安裝於基座10,且於作為規定方向的Y方向延伸;多個封裝頭21a、封裝頭21b,被線性引導件20引導而於Y方向移動;以及控制部50,調整兩個封裝頭21a、封裝頭21b的Y方向的位置。As shown in FIG. 1, the
另外,如圖1所示,於接合裝置100的基座10,安裝有將基板15於X方向搬送的兩組搬送軌道11a、搬送軌道11b以及兩個封裝平台12a、封裝平台12b。進而,於接合裝置100包括:導架(guide frame)32,安裝於基座10且於X方向延伸;拾取頭33,被導架32引導而於X方向移動;導軌(guide rail)30,安裝於基座10且於Y方向延伸;中間平台31,被導軌30引導而於Y方向移動;以及晶圓保持器(未圖示),保持晶圓35。In addition, as shown in FIG. 1, on the
兩個封裝平台12a、封裝平台12b的中心的Y方向位置分別為12c、12d,各封裝平台12a、封裝平台12b的中心的Y方向的距離為W1。另外,於中間平台31的上表面設置有將半導體晶片16放置及拾取的兩個載置台17。兩個載置台17的Y方向的間隔與封裝平台12a、封裝平台12b的Y方向的間隔相同,為W1。The Y-direction positions of the centers of the two
中間平台31是於圖1中由實線表示的第一位置、與由點虛線表示的第二位置之間,於Y方向移動。若中間平台31來到由點虛線表示的第二位置,則兩個載置台17的Y方向位置成為拾取位置13a、拾取位置13b。如上文所說明,兩個載置台17的Y方向的間隔與封裝平台12a、封裝平台12b的Y方向的間隔相同,為W1,因此各拾取位置13a、拾取位置13b與各封裝平台12a、封裝平台12b的各中心的Y方向位置12c、Y方向位置12d之間的各Y方向的距離ΔYc與ΔYd成為相等。The
如圖1所示,於在各基板15的Y方向負側端部封裝半導體晶片16的情況下,將半導體晶片16封裝的Y方向的位置成為封裝位置14a、封裝位置14b。於該情況下,封裝位置14a、封裝位置14b之間的Y方向的距離與兩個載置台17之間的Y方向的距離同樣,成為W1。於該情況下,各拾取位置13a、拾取位置13b與各封裝位置14a、封裝位置14b之間的各Y方向的距離ΔYa與ΔYb成為相等。As shown in FIG. 1, when the
各封裝頭21a、封裝頭21b於線性引導件20的其中一側,於Y方向排列而安裝,被線性引導件20引導而於Y方向移動。於各封裝頭21a、封裝頭21b,安裝有將半導體晶片16拾取及封裝的封裝噴嘴22a、封裝噴嘴22b。各封裝頭21a、封裝頭21b於封裝噴嘴22a、封裝噴嘴22b來到載置台17的正上方拾取半導體晶片16的拾取位置13a、拾取位置13b與封裝噴嘴22a、封裝噴嘴22b將半導體晶片16進行封裝的封裝位置14a、封裝位置14b之間,於Y方向移動。The
於拾取頭33,安裝有拾取噴嘴34,所述拾取噴嘴34從晶圓35拾取半導體晶片16且放置於中間平台31的載置台17上。On the
於各封裝頭21a、封裝頭21b、拾取頭33、中間平台31,安裝有線性馬達(linear motor)等驅動部,各驅動部根據控制部50的指令而運作。控制部50包括於內部包含中央處理單元(Central Processing Unit,CPU)及記憶部的電腦。Drive units such as linear motors are mounted on each of the
接著,一面參照圖2至圖8,一面對接合裝置100的運作進行說明。以下的說明中,如圖1所示,對在各基板15的Y方向負側端部封裝半導體晶片16的情況進行說明。Next, referring to FIGS. 2 to 8, the operation of the
如圖2所示,控制部50使各封裝頭21a、封裝頭21b向初始位置移動,並且使中間平台31向Y方向負側的第一位置移動。而且,控制部50使拾取頭33於X方向移動,利用拾取噴嘴34,從晶圓35拾取半導體晶片16而分別放置於中間平台31的兩個載置台17上。半導體晶片16是以Y方向的距離W1的間隔來放置於中間平台31的兩個載置台17上。As shown in FIG. 2, the
半導體晶片16的放置結束後,控制部50如圖3所示,使中間平台31於Y方向正側移動至第二位置。若中間平台31向第二位置移動,則放置於各載置台17的各半導體晶片16的Y方向位置分別成為拾取位置13a、拾取位置13b。After the placement of the
如圖4所示,控制部50是以各封裝頭21a、封裝頭21b的各封裝噴嘴22a、封裝噴嘴22b的中心成為拾取位置13a、拾取位置13b的方式,使各封裝頭21a、封裝頭21b向Y方向負側移動。此時,控制部50使各封裝頭21a、封裝頭21b同時從初始位置朝向Y方向負側而起動,使各封裝噴嘴22a、封裝噴嘴22b的中心同時到達拾取位置13a、拾取位置13b,使各封裝頭21a、封裝頭21b向Y方向負側的移動同時停止。As shown in FIG. 4, the
如圖5所示,控制部50於各封裝頭21a、封裝頭21b的各封裝噴嘴22a、封裝噴嘴22b的前端分別吸附半導體晶片16,而從中間平台31拾取半導體晶片16。拾取結束後,如圖5所示,使各封裝頭21a、封裝頭21b從拾取位置13a、拾取位置13b向封裝位置14a、封裝位置14b移動。此時,控制部50使各封裝頭21a、封裝頭21b同時朝向Y方向正側而起動,使各封裝噴嘴22a、封裝噴嘴22b的中心同時到達封裝位置14a、封裝位置14b,使各封裝頭21a、封裝頭21b向Y方向正側的移動同時停止。As shown in FIG. 5, the
如上文所說明,由於各拾取位置13a、拾取位置13b與各封裝位置14a、封裝位置14b之間的各Y方向的距離ΔYa與ΔYb相等,故而控制部50如圖7所示的虛線a、實線b般,於時刻t0,使各封裝頭21a、封裝頭21b同時起動,以相同的加速度加速至同一速度直至時刻t1,以同一的速度於Y方向移動至時刻t2,以同一減速度減速至速度零直至時刻t3,且於時刻t3同時停止。此時,如圖8的虛線c、實線d所示,各封裝頭21a、封裝頭21b同時到達封裝位置14a、封裝位置14b。圖7中,虛線a、實線b表示各封裝頭21a、封裝頭21b的速度的時間變化,圖8中,虛線c、實線d於各封裝頭21a、封裝頭21b的Y方向位置表示時間變化。As described above, since the Y-direction distances ΔYa and ΔYb between each
若各封裝頭21a、封裝頭21b向封裝位置14a、封裝位置14b的移動結束,各封裝頭21a、封裝頭21b停止,則控制部50使各封裝噴嘴22a、封裝噴嘴22b下降,將吸附於各封裝噴嘴22a、封裝噴嘴22b的前端的半導體晶片16封裝於各基板15上。When the movement of the packaging heads 21a and 21b to the
在各半導體晶片16於各基板15的封裝完畢後,如圖6所示,控制部50使各封裝頭21a、封裝頭21b向初始位置移動,使中間平台向第一位置移動,繼續進行下一個半導體晶片16的拾取封裝動作。After the packaging of each
於在基板15,將多個半導體晶片16於Y方向排列封裝的情況下,控制部50是以各拾取位置13a、拾取位置13b與各封裝位置14a、封裝位置14b之間的各距離成為相等的方式,使各封裝頭21a、封裝頭21b移動而封裝多個半導體晶片16。例如,如圖1所示,若於各基板15的Y方向負側端部封裝半導體晶片16,則接著,於從最初的封裝位置向Y方向正側分別僅偏移ΔY1的位置封裝半導體晶片16。於該情況下,各封裝位置14a、封裝位置14b之間的Y方向距離為W1,因此拾取位置13a、拾取位置13b與各封裝位置14a、封裝位置14b之間的各距離相等,與上文的說明同樣,藉由使各封裝頭21a、封裝頭21b以同一加速度、同一速度於Y方向移動,可同時起動,同時到達封裝位置14a、封裝位置14b,使各封裝頭21a、封裝頭21b同時停止。In the case where a plurality of
如以上所說明,本實施方式的接合裝置100中,由於將封裝頭21a、封裝頭21b於線性引導件20的其中一側,於Y方向排列配置,故而可將線性引導件20的未配置封裝頭21a、封裝頭21b的一側的空間作為其他機器的配置空間。因此,可實現設置空間的減少。另外,由於控制部50使各封裝頭21a、封裝頭21b從拾取位置13a、拾取位置13b,朝向同一方向而同時起動,同時到達封裝位置14a、封裝位置14b而同時停止,故而可於其中一個封裝頭21a的拾取動作或者封裝動作中,抑制由其他封裝頭21b的移動所引起的振動產生干擾而對封裝精度造成影響,從而提高封裝精度。As described above, in the
接著,對各拾取位置13a、拾取位置13b與各封裝位置14a1、封裝位置14b之間的各個距離不同的情況進行說明。Next, the case where each distance between each pick-up
如圖9所示,於在Y方向負側(近前側)的基板15的Y方向負側端部、及Y方向正側(裏側)的基板15的Y方向正側端部封裝半導體晶片16的情況下,近前側的封裝位置14b與裏側的封裝位置14a1之間的距離W2大於近前側的拾取位置13b與裏側的拾取位置13a之間的距離W1。於該情況下,裏側的拾取位置13a與裏側的封裝位置14a1的距離ΔYa1大於近前側的拾取位置13b與近前側的封裝位置14b之間的距離ΔYb。於該情況下,控制部50藉由使移動距離短的一方的封裝頭21b的移動速度,較移動距離長的一方的封裝頭21a的移動速度更緩慢,而使各封裝頭21a、封裝頭21b同時起動,使各封裝頭21a、封裝頭21b的各封裝噴嘴22a、封裝噴嘴22b同時到達各封裝位置14a1、封裝位置14b,使各封裝頭21a、封裝頭21b的Y方向的移動同時停止。As shown in FIG. 9, the
控制部50如圖11所示,控制各封裝頭21a、封裝頭21b的速度。圖11中,點虛線e、實線b表示各封裝頭21a、封裝頭21b的速度的時間變化,圖12中,點虛線f、實線d於各封裝頭21a、封裝頭21b的Y方向位置表示時間變化。As shown in FIG. 11, the
控制部50如圖11所示的點虛線e、實線b般,於時刻t0,使各封裝頭21a、封裝頭21b同時起動。近前側的封裝頭21b由於移動距離短,故而於時刻t11停止加速,以較裏側的封裝頭21a更緩慢的速度於Y方向等速移動。另一方面,裏側的封裝頭21a與上文的說明同樣,繼續加速至時刻t1,從時刻t1起成為等速移動。而且,裏側的封裝頭21a從時刻t2起開始減速,於時刻t3到達封裝位置14a1,於時刻t3成為速度零。近前側的封裝頭21b繼續等速移動至時刻t12,從時刻t12起開始減速,於時刻t3到達封裝位置14b,於時刻t3成為速度零。The
於時刻t3,各封裝頭21a、封裝頭21b的Y方向的移動停止後,控制部50將各封裝頭21a、封裝頭21b的各封裝噴嘴22a、封裝噴嘴22b所吸附的半導體晶片16封裝於各基板15上。而且,在各半導體晶片16於各基板15的封裝完畢後,如圖10所示,控制部50使各封裝頭21a、封裝頭21b向初始位置移動,使中間平台31向第一位置移動,繼續進行下一個半導體晶片16的拾取封裝動作。At time t3, after the Y-direction movement of the packaging heads 21a and 21b is stopped, the
如以上所說明,實施方式的接合裝置100中,於拾取位置13a、拾取位置13b與封裝位置14a1、封裝位置14b之間的各距離ΔYa1、距離ΔYb不同的情況下,使移動距離短的一方的封裝頭21b的移動速度較距離長的一方的封裝頭21a的移動速度更緩慢。藉此,即便於拾取位置13a、拾取位置13b與封裝位置14a1、封裝位置14b之間的各距離ΔYa1、距離ΔYb不同的情況下,亦可使兩個封裝頭21a、封裝頭21b同時起動、停止。可於其中一個封裝頭21a的拾取動作或者封裝動作中,抑制由其他封裝頭21b的移動所引起的振動產生干擾而對封裝精度造成影響,從而提高封裝精度。As described above, in the
接著,參照圖13至圖15,對其他實施方式的接合裝置200進行說明。對與先前參照圖1至圖12來說明的接合裝置100同樣的部位標註同樣的符號,省略說明。Next, referring to FIGS. 13 to 15, a
如圖13所示,接合裝置200將兩根線性引導件20於Y方向平行地配置兩根,對各線性引導件20分別安裝各為兩個的封裝頭21a、封裝頭21b以及封裝頭21c、封裝頭21d。各封裝頭21a、封裝頭21b與封裝頭21c、封裝頭21d是以於兩根線性引導件20之間相向的方式來配置。因此,可將線性引導件20的未配置封裝頭21a、封裝頭21b的一側以及未配置封裝頭21c、封裝頭21d的一側的空間設為用於其他機器的空間,較排列兩台接合裝置100而言,可進一步減少設置空間。As shown in FIG. 13, the
另外,於接合裝置200,設置有兩個導軌30以及被各導軌30引導的兩個中間平台31。進而,於向X方向延伸的導架32,安裝有兩個拾取頭33。In addition, the joining
對以所述方式構成的接合裝置200的運作進行說明。The operation of the
控制部50使兩個拾取頭33於X方向移動,從兩個晶圓35,分別於中間平台31的各載置台17各放置一個、合計四個的半導體晶片16。The
控制部50是與參照圖4的說明同樣,如圖14所示,以各封裝頭21a、封裝頭21b、封裝頭21c、封裝頭21d的各封裝噴嘴22a、封裝噴嘴22b、封裝噴嘴22c、封裝噴嘴22d的中心成為拾取位置13a、拾取位置13b的方式,使各封裝頭21a、封裝頭21b、封裝頭21c、封裝頭21d朝向Y方向負側移動。此時,控制部50使各封裝頭21a、封裝頭21b、封裝頭21c、封裝頭21d同時從初始位置朝向Y方向負側而起動,使各封裝噴嘴22a、封裝噴嘴22b、封裝噴嘴22c、封裝噴嘴22d的中心同時到達拾取位置13a、拾取位置13b,使各封裝頭21a、封裝頭21b、封裝頭21c、封裝頭21d向Y方向負側的移動同時停止。而且,於各封裝頭21a、封裝頭21b、封裝頭21c、封裝頭21d的各封裝噴嘴22a、封裝噴嘴22b、封裝噴嘴22c、封裝噴嘴22d的前端,分別吸附半導體晶片16。The
控制部50是與先前參照圖5的說明同樣,使各封裝頭21a、封裝頭21b、封裝頭21c、封裝頭21d從拾取位置13a、拾取位置13b向封裝位置14a、封裝位置14b移動。此時,控制部50使各封裝頭21a、封裝頭21b、封裝頭21c、封裝頭21d同時朝向Y方向正側而起動,使各封裝噴嘴22a、封裝噴嘴22b、封裝噴嘴22c、封裝噴嘴22d的中心同時到達封裝位置14a、封裝位置14b,使各封裝頭21a、封裝頭21b、封裝頭21c、封裝頭21d向Y方向正側的移動同時停止。The
若各封裝頭21a、封裝頭21b向封裝位置14a、封裝位置14b的移動結束,各封裝頭21a、封裝頭21b停止,則控制部50使各封裝噴嘴22a、封裝噴嘴22b下降,將吸附於各封裝噴嘴22a、封裝噴嘴22b的前端的半導體晶片16封裝於各基板15上。When the movement of the packaging heads 21a and 21b to the
本實施方式的接合裝置200除了接合裝置100的作用、效果以外,較接合裝置100而言,可進一步減少設置空間,可利用四個封裝頭21a、封裝頭21b、封裝頭21c、封裝頭21d,將四個半導體晶片16同時封裝,因此可進一步加快封裝速度。In addition to the functions and effects of the
此外,以上的說明中,已對兩個拾取頭33分別從兩個晶圓35拾取半導體晶片16而放置於中間平台31的各載置台17的情況進行說明,但並不限定於此,例如亦可構成為:各拾取頭33分別從一個晶圓35拾取半導體晶片16而放置於各中間平台31的各載置台17。In addition, in the above description, the case where the two pick-up
10‧‧‧基座
11a、11b‧‧‧搬送軌道
12a、12b‧‧‧封裝平台
12c、12d‧‧‧Y方向位置
13a、13b‧‧‧拾取位置
14a、14a1、14b‧‧‧封裝位置
15‧‧‧基板
16‧‧‧半導體晶片
17‧‧‧載置台
20‧‧‧線性引導件
21a、21b、21c、21d‧‧‧封裝頭
22a、22b、22c、22d‧‧‧封裝噴嘴
30‧‧‧導軌
31‧‧‧中間平台
32‧‧‧導架
33‧‧‧拾取頭
34‧‧‧拾取噴嘴
35‧‧‧晶圓
50‧‧‧控制部
100、200‧‧‧接合裝置
a、c‧‧‧虛線
b、d‧‧‧實線
e、f‧‧‧點虛線
t0、t1、t2、t3、t11、t12;‧‧‧時刻
X、Y、Z‧‧‧方向
ΔYa、ΔYa1、ΔYb、ΔYc、ΔYd、W1、W2‧‧‧距離10‧‧‧
圖1是表示實施方式的接合裝置的構成的平面圖。 圖2是表示圖1所示的接合裝置的利用拾取頭的半導體晶片的拾取動作的平面圖。 圖3是表示圖1所示的接合裝置的中間平台的移動動作的平面圖。 圖4是表示圖1所示的接合裝置的封裝頭向拾取位置的移動的平面圖。 圖5是表示圖1所示的接合裝置的封裝頭向封裝位置的移動的平面圖。 圖6是表示利用圖1所示的接合裝置,將半導體晶片封裝於基板之後的封裝頭向初始位置的移動、以及中間平台向第一位置的移動的平面圖。 圖7是表示圖1所示的接合裝置中,各拾取位置與各封裝位置的各距離相等的情況下的各封裝頭的速度的時間變化的圖表。 圖8是表示圖1所示的接合裝置中,各拾取位置與各封裝位置的各距離相等的情況下的各封裝頭的Y方向的位置的時間變化的圖表。 圖9是表示圖1所示的接合裝置中,各拾取位置與各封裝位置的各距離不同的情況下的封裝頭向封裝位置的移動的平面圖。 圖10是表示於圖9所示的封裝頭的移動之後,將半導體晶片封裝於基板之後的封裝頭向初始位置的移動、以及中間平台向第一位置的移動的平面圖。 圖11是表示圖9所示的封裝頭的移動時的各封裝頭的速度的時間變化的圖表。 圖12是表示圖9所示的封裝頭的移動時的各封裝頭的Y方向的位置的時間變化的圖表。 圖13是表示其他實施方式的接合裝置的構成的平面圖。 圖14是表示圖13所示的接合裝置的封裝頭向拾取位置的移動的平面圖。 圖15是表示圖13所示的接合裝置的封裝頭向封裝位置的移動的平面圖。Fig. 1 is a plan view showing the configuration of a bonding device according to an embodiment. Fig. 2 is a plan view showing a pickup operation of a semiconductor wafer by a pickup head of the bonding apparatus shown in Fig. 1. Fig. 3 is a plan view showing a movement operation of an intermediate platform of the joining device shown in Fig. 1. Fig. 4 is a plan view showing movement of the packaging head of the bonding device shown in Fig. 1 to a pick-up position. 5 is a plan view showing the movement of the packaging head of the bonding device shown in FIG. 1 to the packaging position. 6 is a plan view showing the movement of the packaging head to the initial position and the movement of the intermediate stage to the first position after the semiconductor chip is packaged on the substrate using the bonding apparatus shown in FIG. 1. FIG. 7 is a graph showing the time change of the speed of each packaging head when each distance between each pickup position and each packaging position is equal in the bonding apparatus shown in FIG. 1. FIG. 8 is a graph showing the time change of the position of each packaging head in the Y direction when the respective distances between each pickup position and each packaging position are the same in the bonding apparatus shown in FIG. 1. 9 is a plan view showing the movement of the packaging head to the packaging position in the case where the respective distances between the pick-up positions and the packaging positions are different in the bonding device shown in FIG. 1. 10 is a plan view showing the movement of the packaging head to the initial position after the semiconductor chip is packaged on the substrate after the movement of the packaging head shown in FIG. 9 and the movement of the intermediate stage to the first position. FIG. 11 is a graph showing the time change of the speed of each packaging head during the movement of the packaging head shown in FIG. 9. FIG. 12 is a graph showing the time change of the position of each packaging head in the Y direction when the packaging head shown in FIG. 9 is moved. Fig. 13 is a plan view showing the configuration of a bonding device according to another embodiment. Fig. 14 is a plan view showing the movement of the packaging head of the bonding device shown in Fig. 13 to a pickup position. 15 is a plan view showing the movement of the packaging head of the bonding device shown in FIG. 13 to the packaging position.
10‧‧‧基座 10‧‧‧Base
11a、11b‧‧‧搬送軌道 11a, 11b‧‧‧Conveying track
12a、12b‧‧‧封裝平台 12a, 12b‧‧‧Packaging platform
12c、12d‧‧‧Y方向位置 12c, 12d‧‧‧Y direction position
13a、13b‧‧‧拾取位置 13a, 13b‧‧‧Pickup position
14a、14b‧‧‧封裝位置 14a, 14b‧‧‧Packaging position
15‧‧‧基板 15‧‧‧Substrate
16‧‧‧半導體晶片 16‧‧‧Semiconductor chip
17‧‧‧載置台 17‧‧‧Mounting table
20‧‧‧線性引導件 20‧‧‧Linear guide
21a、21b‧‧‧封裝頭 21a, 21b‧‧‧Packing head
22a、22b‧‧‧封裝噴嘴 22a、22b‧‧‧Packing nozzle
30‧‧‧導軌 30‧‧‧Guide
31‧‧‧中間平台 31‧‧‧Intermediate platform
32‧‧‧導架 32‧‧‧Guide frame
33‧‧‧拾取頭 33‧‧‧Pickup head
34‧‧‧拾取噴嘴 34‧‧‧Pick up nozzle
35‧‧‧晶圓 35‧‧‧wafer
50‧‧‧控制部 50‧‧‧Control Department
100‧‧‧接合裝置 100‧‧‧Joint device
X、Y、Z‧‧‧方向 X, Y, Z‧‧‧direction
ΔYa、ΔYb、ΔYc、ΔYd、W1‧‧‧距離 ΔYa, ΔYb, ΔYc, ΔYd, W1‧‧‧Distance
Claims (5)
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JP2018-138294 | 2018-07-24 | ||
JP2018138294 | 2018-07-24 |
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TW202008495A TW202008495A (en) | 2020-02-16 |
TWI712100B true TWI712100B (en) | 2020-12-01 |
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TW108126041A TWI712100B (en) | 2018-07-24 | 2019-07-23 | Electronic parts packaging device |
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JP (1) | JP6981700B2 (en) |
KR (1) | KR102432998B1 (en) |
CN (1) | CN112368811B (en) |
SG (1) | SG11202013223TA (en) |
TW (1) | TWI712100B (en) |
WO (1) | WO2020022345A1 (en) |
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JP2022139910A (en) * | 2021-03-12 | 2022-09-26 | キヤノンマシナリー株式会社 | Bonding device and bonding method |
JP2022139913A (en) * | 2021-03-12 | 2022-09-26 | キヤノンマシナリー株式会社 | Bonding device and bonding method |
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JP5076833B2 (en) | 2007-11-22 | 2012-11-21 | ヤマハ株式会社 | Amplifier control system |
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- 2019-07-23 TW TW108126041A patent/TWI712100B/en active
- 2019-07-23 WO PCT/JP2019/028891 patent/WO2020022345A1/en active Application Filing
- 2019-07-23 JP JP2020532417A patent/JP6981700B2/en active Active
- 2019-07-23 CN CN201980044544.9A patent/CN112368811B/en active Active
- 2019-07-23 SG SG11202013223TA patent/SG11202013223TA/en unknown
- 2019-07-23 KR KR1020207030915A patent/KR102432998B1/en active IP Right Grant
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US20030098340A1 (en) * | 2001-11-28 | 2003-05-29 | Asm Technology Singapore Pte Ltd | Multiple-head wire-bonding system |
US20080092370A1 (en) * | 2006-10-19 | 2008-04-24 | Yam Mo Wong | Electronic device handler for a bonding apparatus |
Also Published As
Publication number | Publication date |
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JP6981700B2 (en) | 2021-12-17 |
WO2020022345A1 (en) | 2020-01-30 |
SG11202013223TA (en) | 2021-01-28 |
KR102432998B1 (en) | 2022-08-18 |
JPWO2020022345A1 (en) | 2020-12-17 |
TW202008495A (en) | 2020-02-16 |
CN112368811A (en) | 2021-02-12 |
CN112368811B (en) | 2024-08-30 |
KR20200138312A (en) | 2020-12-09 |
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