TWI687973B - 電子構件的製造方法 - Google Patents

電子構件的製造方法 Download PDF

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TWI687973B
TWI687973B TW107110471A TW107110471A TWI687973B TW I687973 B TWI687973 B TW I687973B TW 107110471 A TW107110471 A TW 107110471A TW 107110471 A TW107110471 A TW 107110471A TW I687973 B TWI687973 B TW I687973B
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Taiwan
Prior art keywords
organic resin
oxygen
resin layer
metal layer
layer
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TW107110471A
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English (en)
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TW201841223A (zh
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廣庭大輔
栗本孝志
植田昌久
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日商愛發科股份有限公司
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    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
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    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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Abstract

本發明之一形態中之電子構件的製造方法係於基板上形成第一金屬層，於前述第一金屬層上形成第二金屬層，於前述第二金屬層上形成由有機樹脂層所構成之遮罩，介隔前述遮罩而使用含氟之反應氣體對前述第二金屬層進行電漿蝕刻，於前述有機樹脂層與前述第二金屬層之積層膜形成凹部，對前述凹部之內部表面進行氧灰化處理，於前述氧灰化處理後，藉由電解鍍覆處理於前述凹部內形成第三金屬層。

Description

電子構件的製造方法
本發明係關於一種具有使用電解鍍覆處理之金屬層之電子構件的製造方法。
近年來，提出有如下被稱為FO(Fan-Out；扇出)之封裝(電子構件)的製造：形成再配線層代替配線基板。於FO的製造中，於利用密封樹脂將半導體晶片密封之後，使半導體晶片之電路形成面露出，於該電路形成面形成再配線層(再配線形成步驟)，將再配線區域廣泛地確保。
再配線層係透由層間絕緣膜來積層配線層而構成，不同之配線層係藉由設於層間絕緣膜之銅通道(via)而電性連接。例如，銅通道或銅配線係藉由以下方式形成：於金屬層上形成具有通道孔或溝槽(trench)之光阻圖案(photo resist pattern)，藉由電解鍍覆處理將銅填埋於通道孔內或溝槽(例如參照專利文獻1、專利文獻2)。具有通道孔或溝槽之光阻圖案係藉由以下方式形成：使用光微影 (photolithography)法對光阻劑進行曝光、顯影而於光阻劑設置通道孔或溝槽。
迄今，雖藉由使用顯影液之濕式製程(wet process)而於光阻劑形成通道孔，但有利用乾式製程(dry process)來形成通道孔之期望。例如，於銅通道之形成步驟中，於半導體基板上依序形成銅層、鈦層、由有機樹脂層所構成之遮罩後，介隔遮罩而使用含氟之反應氣體對鈦層進行電漿蝕刻(plasma etching)，來形成將鈦層及有機樹脂層之積層膜予以貫穿的通道孔。然後，藉由進行電解鍍覆處理而於通道孔內填埋銅，形成銅通道。
若使用含氟之反應氣體藉由電漿蝕刻而形成通道孔，則有機樹脂層(遮罩)之表面經氟化而於表面形成有氟化物。若有機樹脂層之表面經氟化，則有機樹脂層之表面呈疏水性，於後續之電解鍍覆處理時電解鍍覆液不易進入通道孔，難以獲得所需形狀之銅通道，而有產生配線不良之虞。
[先前技術文獻]
[專利文獻]
專利文獻1：日本特開2013-47786號公報。
專利文獻2：日本特開2014-220485號公報。
鑒於以上般之情況，本發明之目的在於提供一種電子構件的製造方法，係於電解鍍覆處理步驟中，電解鍍覆液向設於有機樹脂層之孔之進入良好。
為了達成上述目的，本發明之一形態中之電子構件的製造方法包括：形成第一金屬層，形成第二金屬層，形成遮罩，進行蝕刻，進行氧灰化(ashing)處理，形成第三金屬層。
上述第一金屬層之形成步驟係於基板上形成第一金屬層。
上述第二金屬層之形成步驟係於上述第一金屬層上形成第二金屬層。
上述遮罩之形成步驟係於上述第二金屬層上形成由有機樹脂層所構成之遮罩。
上述蝕刻步驟係介隔上述遮罩而使用含氟之反應氣體對上述第二金屬層進行電漿蝕刻，於上述有機樹脂層與上述第二金屬層之積層膜形成凹部。
上述氧灰化步驟係對上述凹部之內部表面進行氧灰化處理。
上述第三金屬層之形成步驟係於上述氧灰化處理後，藉由電解鍍覆處理於上述凹部內形成第三金屬層。
根據本發明之此種構成，因使用含氟之氣體之蝕刻而表面成為疏水性的有機樹脂層係藉由氧灰化而表面被親水化處理。因此，由於對凹部內部之有機樹脂層表面進行親水化處理，故而於第三金屬層形成時電解鍍覆液容易進入凹部，可形成所需形狀之第三金屬層。藉此，可製造無配線不良狀況之電子構件。
上述第二金屬層亦可包含鈦。
上述蝕刻步驟亦可使用氧氣、氮氣及四氟化碳之混合氣體作為反應氣體而進行。
上述氧灰化處理步驟亦可使用以氧自由基(radical)為主之氧電漿而進行。
根據此種構成，可長期維持由氧灰化所得之有機樹脂層之表面親水化效果，可穩定地獲得無配線不良狀況之電子構件。
如以上所述般，根據本發明，對有機樹脂層進行親水化處理，藉此電解鍍覆液向孔之進入變得良好，可提供一種無配線不良狀況之電子構件。
1‧‧‧半導體基板(基板)
2、2a‧‧‧銅層(第一金屬層)
3、3a‧‧‧鈦層(第二金屬層)
4‧‧‧有機樹脂層(形成第一凹部前之有機樹脂層)
5‧‧‧通道孔(第二凹部)
6‧‧‧通道用銅層(第三金屬層)
8‧‧‧銅通道
10‧‧‧製造裝置
11‧‧‧腔室(處理室)
11a‧‧‧上部內面
12‧‧‧輸送管
13‧‧‧電漿室
13a‧‧‧微波透射窗
14‧‧‧微波導波管
15‧‧‧磁控管
16‧‧‧μ波電源
17‧‧‧氣體導入管
18a、18b、18c‧‧‧質量流量控制器
19a、19b、19c‧‧‧氣體供給源
20‧‧‧基板台
21‧‧‧閘門
22‧‧‧真空預備室
23‧‧‧排氣口
24‧‧‧排氣管
25‧‧‧壓力控制器
26‧‧‧控制裝置
31‧‧‧簇射板
32‧‧‧安裝部件
33‧‧‧防擴散壁
36‧‧‧基板導件
37‧‧‧提升銷
38‧‧‧絕緣板
39‧‧‧配管
40‧‧‧高頻電源
41‧‧‧第一凹部
42、43‧‧‧遮罩
61‧‧‧電解鍍覆液
71‧‧‧氟化物
72‧‧‧氧化物及氟化物
C‧‧‧電容器
W‧‧‧半導體基板
圖1為表示本發明之一實施形態之電子構件的製造步驟(製造步驟一)的概略部分剖面圖。
圖2為表示繼圖1所示之製造步驟之後的電子構件的製造步驟(製造步驟二)的概略部分剖面圖。
圖3為上述電子構件之製造流程圖。
圖4為進行上述電子構件之蝕刻及灰化的製造裝置之概略構成圖。
圖5為上述製造裝置之腔室之概略剖面圖。
圖6為表示上述電子構件之電解鍍覆處理步驟中之狀況的示意部分剖面圖。
圖7為表示未進行氧灰化處理的電子構件之電解鍍覆處理步驟中之狀況的示意部分剖面圖。
圖8為表示蝕刻處理前、蝕刻處理後、未施加高頻偏壓(bias)情況下之氧灰化處理後、施加高頻偏壓情況下之氧灰化處理後各自的電子構件之有機樹脂層之表面之XPS(X-Ray Photoelectron Spectroscopy；X射線光電子光譜法)分析結果的圖。
圖9為表示氧灰化處理中之高頻偏壓功率之大小與灰化率(ashing rate)之關係的圖。
圖10為表示氧灰化處理時之高頻偏壓功率之大小與電解鍍覆液附著於有機樹脂層之表面時的接觸角之經時變化之關係的圖。
圖11為表示氧灰化處理時之基板台溫度與電解鍍覆 液附著於有機樹脂層之表面時的接觸角之經時變化之關係的圖。
以下，一邊參照圖式一邊對本發明之實施形態進行說明。以下，列舉如下電子構件之再配線層步驟之一部分步驟為例進行說明，但不限定於此：於晶圓上再配置多個已晶片化之半導體元件，以模製樹脂(mold resin)將該等半導體元件覆蓋，並於該模製樹脂上形成將半導體彼此加以電性連接之再配線層而成。
以下，將於晶圓上配置半導體元件並以模製樹脂將該等覆蓋之狀態的電子構件稱為半導體基板來進行說明。
本實施形態之電子構件於其製造步驟中有蝕刻處理步驟及氧灰化處理步驟，以下對進行該等處理步驟之製造裝置進行說明。
[製造裝置之構成]
圖4為製造裝置之概略構成圖，圖5為製造裝置之腔室之概略剖面圖。本實施形態中之製造裝置係以可進行蝕刻處理及灰化處理之方式構成。
如圖4所示，製造裝置10具備腔室(處理室)11、電漿室13、輸送管12、磁控管(magnetron)15、微波電源16、氣體導入管17、質量流量控制器(mass flow controller)18a至 18c、氣體供給源19a至19c、真空預備室22、控制裝置26、排氣管24及壓力控制器(pressure controller)25。
腔室11將作為被處理對象物之晶圓等半導體基板W予以收容。半導體基板W係於腔室11內被施予蝕刻處理及灰化處理。於腔室11內係配置有載置基板W之基板台20。於腔室11係經由閘門21而連接有預備室22。
於腔室11之底部係形成有排氣口23。該排氣口23經由排氣管24而連接於未圖示之排氣用泵，藉由該排氣用泵而腔室11內得以減壓。於排氣管24係配設有壓力控制器25，藉由該壓力控制器25而腔室11內之壓力得以調整。
腔室11之上部經由輸送管12而連接於電漿室13。電漿室13經由微波導波管14而連接於磁控管15。電漿室13與微波導波管14係利用由石英等所構成之微波透射窗13a而隔開。於磁控管15係連接有微波電源16，由磁控管15所產生之微波(μ波)係經由微波導波管14而引導至電漿室13內。
電漿室13經由氣體導入管17而連接於多個(本實施形態中為3個)質量流量控制器18a至18c，各質量流量控制器18a至18c分別連接於氣體供給源。於本實施形態中，氣體供給源19a蓄積氧氣(O2)，氣體供給源19b蓄積氮氣 (N2)，氣體供給源19c蓄積四氟化碳(CF4)。蓄積於各氣體供給源19a至19c之氣體之流量係藉由質量流量控制器18a至18c而調整，將預定流量之氧氣、氮氣及四氟化碳混合而成之反應氣體經由氣體導入管17而被導入至電漿室13內。
藉由上述微波及反應氣體而於電漿室13內產生電漿，該電漿中之作為活性種之自由基係經由輸送管12而被引導至腔室11內。
上述微波電源16、各質量流量控制器18a至18c以及壓力控制器25係連接於控制裝置26。控制裝置26具有未圖示之儲存裝置，於該儲存裝置係儲存有用以對各種基板進行處理之條件之資訊。控制裝置26根據對應於搬入至腔室11內的基板W之處理條件資訊，對微波電源16、各質量流量控制器18a至18c以及壓力控制器25進行控制。
繼而，使用圖5對腔室11之構成進行說明。
在連結於腔室11之上部的輸送管12之下端係與基板台20之載置面相對向而配置有簇射(shower)板(擴散板)31，該簇射板(擴散板)31係形成為圓盤狀並且具有大量之貫通孔，該基板台20係載置半導體基板W。簇射板31係固定於腔室11之上部，並且藉由簇射板具有支柱這點而恰以預定距離遠離上部內面11a而配置。腔室11之上部內 面11a與簇射板31之距離係以如下方式設定：使經由上述輸送管12而導入至腔室11內之氧自由基通過形成於簇射板31之貫通孔，並且通過簇射板31與腔室11之上部之間而被向周邊引導。
於腔室11之上部內面11a係安裝有已形成為圓筒狀之防擴散壁33之上端，簇射板31因該防擴散壁33而被包圍。防擴散壁33之內徑係設定為略大於被載置在基板台20上之基板W之外徑。
基板台20之周邊上部係由基板導件36覆蓋。於基板台20內係配設有被支持成可於上下方向移動之提升銷(lift pin)37之前端，藉由使該提升銷37上下移動，而將提升銷37與未圖示之搬送裝置之間的半導體基板W載置於基板台20上。
於基板台20與腔室11下部之間係插入有絕緣板38。另外，於基板台20係連接有配管39，經由該配管39對形成於基板台20內部之未圖示之水路供給冷卻水，進行基板台20之溫度調節。此外，於基板台20係介隔電容器(condensor)C而連接有高頻電源40，自該高頻電源40對基板台20供給有高頻偏壓(RF(Radio Frequency；射頻)偏壓)。
另一方面，上述腔室11係接地，相對於自高頻電源 40對基板台20供給之高頻偏壓而成為電性對向電極。而且，於該腔室11係透由安裝部件32而電性連接有簇射板31之第一層，並且電性連接有防擴散壁33。
[電子構件的製造方法]
繼而，對使用上述製造裝置之電子構件的製造方法加以說明。
於本實施形態中，列舉電子構件的銅通道形成步驟為例進行說明，該電子構件係於經密封樹脂覆蓋之半導體晶片之電路形成面上形成再配線層而成，該銅通道形成步驟係作為形成該電子構件的再配線層之步驟之一部分步驟。
以下，使用圖1至圖5進行說明。圖1以及圖2為表示電子構件之製造步驟的概略部分剖面圖。圖3為電子構件之製造流程圖。
首先，如圖1中的(a)所示，於經密封樹脂密封之半導體晶片(以下稱為半導體基板)1之電路形成面上，藉由例如濺鍍(sputtering)成膜法而依序積層有膜厚100nm之作為第一金屬層之銅層2、膜厚50nm之作為第二金屬層之鈦層3，進而於鈦層3上形成膜厚6μm之有機樹脂層4。關於有機樹脂層4，可使用聚醯亞胺(PI)或聚苯并噁唑(PBO)等耐熱性之有機樹脂，本實施形態中使用PBO。
鈦層3係配置於銅層2與有機樹脂層4之間，作為用以提高兩者之密接性的密接層而發揮功能。另外，形成於銅層2與有機樹脂層4之間的第二金屬層不限定於鈦，可使用鈦之合金等，該等材料為藉由使用含氟之反應氣體之電漿蝕刻而可蝕刻的材料。另外，於後續步驟之電解鍍覆處理時作為陰極而發揮功能之第一金屬層不限定於銅，可使用銀等。
繼而，如圖1中的(b)所示，對應於後續步驟中供銅通道形成之區域之有機樹脂層4係藉由雷射被去除(S101)，形成遮罩42，該遮罩42係由具有成為通道孔之一部分的第一凹部41之有機樹脂層所構成。第一凹部41並未貫通有機樹脂層，於遮罩42中之供銅通道形成之區域中，以位於遮罩42之下層的鈦層3不露出之方式殘留厚度500nm之有機樹脂層。
如此，遮罩42係以僅供銅通道形成之區域與其他區域相比而厚度變薄之方式，利用雷射將一部分有機樹脂層去除而形成。藉此，可於後續之蝕刻步驟中以如下方式進行控制：僅於供銅通道形成之區域中銅層2露出，於除此以外之區域中殘留有機樹脂層。另外，於遮罩42中之供銅通道形成之區域中，以鈦層3不露出之方式使一部分有機樹脂層殘留之原因在於：鈦層3之厚度薄，故於雷射處理中使位於鈦層3之下層的銅層2不因雷射而受到損傷。
繼而，於上述製造裝置之腔室11內搬入半導體基板1，半導體基板1係以供有機樹脂層42形成之面(處理面)朝上而被載置於基板台20上。繼而，將腔室11內部減壓，對基板台20施加高頻偏壓(RF偏壓)。另一方面，對電漿室13係自各氣體供給源19a至19c供給有氧氣(O2)、氮氣(N2)、四氟化碳(CF4)之氣體，進而經由微波導波管14而供給有由磁控管15產生之微波。於電漿室13中，藉由微波及O2/N2/CF4之混合氣體(反應氣體)而產生電漿，該電漿中之作為活性種之氧自由基或CF自由基經由輸送管12而被引導至腔室11內。
藉由氧自由基及CF自由基被引導至腔室11內，而如圖1中的(c)所示，介隔遮罩42而對應於遮罩42中之第一凹部41之有機樹脂層藉由氧自由基而被灰化並去除，進而鈦層3藉由CF自由基而被蝕刻並去除(S102)。藉此，於構成遮罩42之有機樹脂層與鈦層3之積層膜，形成有於該積層膜之厚度方向貫通的作為第二凹部之通道孔5。
於蝕刻處理步驟中，對應於遮罩42中之第一凹部41之區域之有機樹脂層被去除而形成有遮罩43，該遮罩43係形成有構成通道孔5之一部分的貫通孔。另外，形成有鈦層3a，該鈦層3a係形成有構成通道孔5之另一部分的貫通孔。
另外，雖遮罩42中之未形成有第一凹部41之區域之有機樹脂層亦因該蝕刻處理而被去除，但預估該利用混合氣體之蝕刻處理中之蝕刻量，有機樹脂層4之膜厚係被適當設定。
利用O2/N2/CF4之混合氣體之蝕刻處理(S102)係使基板台20之溫度為25℃，使O2、N2、CF4各自之流量為100sccm、100sccm、300sccm，使腔室11內為35Pa，使微波之功率為1500W，使RF偏壓為300W，以處理時間30秒而進行。
關於基板台20之溫度，為了保持形成於半導體基板1之晶片之品質，較理想為以150℃以下進行處理，更理想為以15℃至150℃之溫度進行處理。若處理溫度高於150℃則引起電子晶片之劣化、有機樹脂膜之變質。
另外，藉由提高混合氣體中之CF4之比率，可提高鈦層3之蝕刻速率(etching rate)。另外，藉由使混合氣體內含有N2，可延長O2之自由基之壽命。
於構成遮罩43之有機樹脂層之表面係因CF4而形成有氟化物71，該CF4係作為包含蝕刻處理時之混合氣體所含的氟之氣體。構成遮罩43之有機樹脂層之表面因該氟化物而呈疏水性。
繼而，於在同一腔室11內載置有半導體基板1之狀態下，停止向基板台20施加高頻偏壓(RF偏壓)。另一方面，對電漿室13係自氣體供給源19a供給有氧(O2)，進而經由微波導波管14而供給有由磁控管15產生之微波。於電漿室13中，藉由微波及O2而產生氧電漿，該氧電漿中之作為活性種之氧自由基經由輸送管12而被引導至腔室11內。
藉由氧自由基被引導至腔室11內，如圖1中的(d)所示，有機樹脂層之表面被進行氧灰化處理，成於表面之氟化物71被去除(S103)。藉由該氧灰化處理，包含通道孔5之內部表面的構成遮罩43之有機樹脂層之表面係親水化而呈親水性。
氧灰化處理係使基板台20之溫度為25℃，使O2之流量為1600sccm，使腔室11內壓力為70Pa，使微波之功率為500W，於處理時間3秒之處理條件下進行。
關於基板台20之溫度，為了保持形成於半導體基板1之晶片之品質，較理想為以150℃以下進行處理，更理想為以15℃至150℃之溫度進行處理。
繼而，半導體基板1係自上述製造裝置之腔室11被搬出後被搬入至電解鍍覆用之裝置，於該裝置中對半導體基 板1進行使用電解鍍覆處理之銅通道之形成(S104)。亦即，半導體基板1及銅源被浸漬於電解鍍覆液中後，以形成於半導體基板1之銅層2成為陰極且銅源成為陽極之方式，自外部電源供給直流電流。藉此，如圖1中的(e)所示，自銅源溶出之銅離子於銅層2上還原，藉此於通道孔5內形成有銅，成為銅通道之一部分的作為第三金屬層之通道用銅層6被形成。
於電解鍍覆處理步驟中，由於有機樹脂層43之表面因氧灰化處理進行改質處理而呈親水性，故電解鍍覆液向通道孔5內之進入變得良好。
此處，對由氧灰化處理所得之親水性化之效果進行說明。
實施雷射處理(S101)，且實施利用O2/N2/CF4之混合氣體的蝕刻處理(S102)之前，電解鍍覆液附著於半導體基板1上之遮罩42之有機樹脂層之表面時的接觸角為82.5°。
實施利用O2/N2/CF4之混合氣體之蝕刻處理(S102)，且實施氧灰化處理(S103)之前，電解鍍覆液附著於半導體基板1之遮罩43之有機樹脂層之表面時的接觸角為100°左右。
實施利用O2/N2/CF4之混合氣體之蝕刻處理(S102)，且進行氧灰化處理(S103)之後，電解鍍覆液附著於半導體基板1之遮罩43之有機樹脂層之表面時的接觸角為 5°左右。
如此而確認到以下情形：藉由實施氧灰化處理，以利用O2/N2/CF4之混合氣體之蝕刻處理而於表面形成有氟化物而呈疏水性之有機樹脂層之表面係經親水化處理而呈親水性。
圖6為示意性地表示將進行了氧灰化處理之半導體基板1浸漬於電解鍍覆液時電解鍍覆液61向通道孔5內之進入狀況的圖。圖7為示意性地表示將未實施氧灰化處理之半導體基板1浸漬於電解鍍覆液61時之狀況的圖。
對於未實施氧灰化處理之半導體基板1而言，由於遮罩43之表面呈疏水性，故而如圖7中的(a)及圖7中的(b)所示，於將基板1浸漬於電解鍍覆液時，存在以下情形：電解鍍覆液61於遮罩43之有機樹脂層之表面被排斥，電解鍍覆液61並未良好地進入通道孔5內；或即便電解鍍覆液61進入通道孔5內，電解鍍覆液61亦未遍佈至通道孔5內之角落，產生空隙。若以此種狀態進行電解鍍覆處理，則無法獲得所需形狀之通道用銅層，有時並未形成通道用銅層而成為出現配線不良之電子構件。
相對於此，如圖6所示，對於具備進行氧灰化處理而表面經改質而呈親水性之遮罩43之半導體基板1而言，電解鍍覆液61於遮罩43之有機樹脂層之表面不被排斥，於 通道孔5內不產生空隙而電解鍍覆液61良好地進入通道孔5內，銅之填埋性高。因此，可獲得所需形狀之通道用銅層，可獲得無配線不良狀況之電子構件。
繼而，進行了電解鍍覆處理之半導體基板1從電解鍍覆用之裝置被搬出，藉由已知之濕式蝕刻或乾式蝕刻而遮罩43被去除(S105)。
繼而，半導體基板1被搬入至蝕刻裝置，鈦層3a與銅層2中供通道用銅層6形成的區域以外之銅層2係藉由蝕刻依序被去除。具體而言，藉由利用氧氣、氮氣與氟系氣體之混合氣體進行電漿蝕刻處理而鈦層3被去除(S106)。然後，對銅層2以公知之濕式蝕刻將供通道用銅層6形成的區域以外之銅層2去除(S107)。藉此，如圖2中的(a)所示形成銅通道8，該銅通道8係由供通道用銅層6形成之區域中殘留的銅層2a與通道用銅層6之積層所構成。於鈦層3之蝕刻步驟時，由於使用含有氧及氟之反應氣體，故於銅通道8之表面形成有氧化物及氟化物72。
上述鈦層3之蝕刻步驟係使基板台之溫度為25℃，使O2、N2、CF4各自之流量為100sccm、100sccm、300sccm，使腔室11內為35Pa，使微波之功率為1500W，使RF偏壓為300W，於處理時間30秒之處理條件下進行。
繼而，對形成有銅通道8之半導體基板1實施氮電漿處理(S108)。藉此，形成於銅通道8之表面之氧化物及氟化物72被去除。氮電漿處理係使基板台之溫度為50℃，使N2之流量為1000sccm，使腔室11內為100Pa，使微波之功率為0W，使RF偏壓為300W，以處理時間30秒而進行。
此處，於未對半導體基板1實施氮電漿處理(S108)之情形時，於自銅通道8之表面至深度6nm之區域中，除了銅以外還存在氧及氟。相對於此，若實施氮電漿處理，則若距銅通道8表面之深度變深至3nm以上則僅存在銅，存在於自銅通道8之表面至深度3nm之區域中的氧及氟亦與未實施氮電漿處理之基板相比大幅減少。
以如此般進行了氮電漿處理之半導體基板1而言，由於銅之氧化得到抑制且於銅通道8之表面產生電阻率高之氧化銅的情形得到抑制，故可使電子構件之電氣特性良好。
藉由以上操作而形成銅通道8。
如以上般，於使用含氟之氣體之蝕刻處理後進行氧灰化處理，藉此可對形成於半導體基板1之有機樹脂層之表面進行親水化處理。藉此，於利用後續步驟之電解鍍覆處理而形成通道用銅層時，可將電解鍍覆液向通道孔內之進入良好化。因此，電解鍍覆液無空隙地進入通道孔內，故能以所需形狀形成由銅層所構成之通道，可獲得無配線不 良狀況之電子構件。
另外，藉由對形成有銅通道8之半導體基板1實施氮電漿處理，可抑制銅通道表面之氧化。
上述實施形態中，雖於停止施加RF偏壓之狀態下進行氧灰化處理而進行有機樹脂層之親水化處理，但即便於施加RF偏壓之狀態下進行氧灰化處理，亦可同樣地獲得有機樹脂層表面之親水化效果。
繼而，對由上述氧灰化處理所致之有機樹脂層表面之變化進行說明。
圖8為有機樹脂層表面之XPS分析結果。
圖8中的(a)為依照上述製造方法進行至雷射處理(S101)後的半導體基板上之有機樹脂層(遮罩42)之表面之XPS分析結果。
圖8中的(b)為依照上述製造方法進行至利用O2/N2/CF4之混合氣體之蝕刻處理(S102)後的半導體基板上之有機樹脂層(遮罩43)之表面之XPS分析結果。
圖8中的(c)為依照上述製造方法進行至氧灰化處理(S103)後的半導體基板上之有機樹脂層(遮罩43)之表面之XPS分析結果，且氧灰化處理係於未施加RF偏壓之處理條件下進行。
圖8中的(d)為大致依照上述製造方法進行至氧灰化處理(S103)後的半導體基板上之有機樹脂層(遮罩43)之表面之XPS分析結果，且與上述製造方法不同處僅在於氧灰化處理於施加了RF偏壓之處理條件下進行。
於圖8之各圖中，實線為有機樹脂層表面之XPS分析結果，虛線或鏈線係將實線所示之有機樹脂層表面之波形依各化學鍵狀態加以波形分離而成。
如圖8中的(a)及圖8中的(b)所示，雖因使用O2/N2/CF4之混合氣體之蝕刻處理而於有機樹脂層表面形成有氟化物或氧化物，但如圖8中的(c)及圖8中的(d)所示般，若進行氧灰化處理，則形成於有機樹脂層表面之氟化物被去除之情況已被確認。另外，根據圖8中的(c)及圖8中的(d)，於氧灰化處理時未施加RF偏壓之情況與施加了RF之情況相比，成為碳與氧之雙鍵(C=O)相對於碳與氧之單鍵(C-O)的比率較多之結果，可認為這一情況可能與後述親水性之經時變化有關。
繼而，示出對由氧灰化處理時之RF偏壓功率之差異所致的有機樹脂層表面之接觸角進行評價之結果。
圖9為表示氧灰化時之RF偏壓功率與樹脂層之每分鐘之灰化量之關係的圖。
圖10為表示有無氧灰化處理及使氧灰化處理時之RF 偏壓功率變化時的有機樹脂層表面之接觸角之經時變化的圖表。
任一圖中均將如下半導體基板作為試樣：準備依照上述製造方法進行至利用O2/N2/CF4之混合氣體之蝕刻處理(S102)後的半導體基板，然後僅改變氧灰化處理時之RF偏壓功率，且其他氧灰化條件係設為與上述氧灰化處理(S103)的製造方法相同而進行氧灰化處理所得之半導體基板。
如圖9所示，於RF偏壓之功率為0W至10W之範圍內，未確認到有機樹脂層之切削，若成為10W以上，則確認到灰化率亦即有機樹脂層之切削量與RF偏壓功率成比例地逐漸增大。
於圖10中，自左開始依序圖示以下半導體基板各自的氧灰化處理之1小時後、1天後、3天後之接觸角：未進行氧灰化處理之半導體基板(相當於圖中之未處理)、於RF偏壓為0W亦即未施加RF偏壓之條件下進行了氧灰化處理之半導體基板、於RF偏壓為10W之條件下進行了氧灰化處理之半導體基板、於RF偏壓為30W之條件下進行了氧灰化處理之半導體基板、於RF偏壓為100W之條件下進行了氧灰化處理之半導體基板。
如圖10所示，關於未進行氧灰化處理之半導體基板(圖中之未處理之試樣)，確認到電解鍍覆液附著於有機樹脂層時的接觸角為78°左右且有機樹脂層之表面呈疏水性。另外，無論是否施加RF偏壓，進行了氧灰化處理之半導體基板與未進行氧灰化處理之半導體基板相比皆確認到接觸角變小且藉由氧灰化處理而被親水化處理。如此，藉由進行氧灰化處理，與未進行氧灰化處理之情形相比，有機樹脂層之表面被親水化，電解鍍覆處理時電解鍍覆液向孔之進入變得良好。
另外，於氧灰化處理時未施加RF偏壓之情形時，確認到氧灰化處理之1小時後、1天後、3天後之接觸角均顯示0°，持續地維持親水性之效果。於氧灰化處理時之RF偏壓為10W之情形時，於氧灰化處理之1小時後接觸角顯示0°，於1天後顯示約7°左右，於3天後顯示約10°左右。於氧灰化處理時之RF偏壓為30W之情形時，於氧灰化處理之1小時後接觸角顯示7.5°左右，於1天後顯示約21°左右，於3天後顯示23°左右。於氧灰化處理時之RF偏壓為100W之情形時，於氧灰化處理之1小時後接觸角顯示11°左右，於1天後顯示約24°左右，於3天後顯示25°左右。
於氧灰化處理時之RF偏壓為0W至10W之處理條件下，並無接觸角之經時變化，或接觸角之經時變化得到抑制，親水性之效果維持為良好。於此種處理條件下進行了 氧灰化處理之半導體基板即便於氧灰化處理之步驟與後續的電解鍍覆處理之步驟之間有時間間隔，親水性之效果亦得以維持，故可於電解鍍覆處理時將電解鍍覆液向孔之進入良好化。尤其於未施加RF偏壓之處理條件下經處理之半導體基板即便時間經過亦將接觸角維持於0°，亦即超親水性之效果得以維持，即便存在氧灰化處理步驟與電解鍍覆處理步驟之間隔，亦可於超親水性得以維持之狀態下進行電解鍍覆處理步驟，可穩定地製造無連接不良狀況之電子構件。
如此，於0W至10W般RF偏壓功率小之處理條件下，氧灰化處理係使用以氧自由基為主之氧電漿而進行，由此於RF偏壓為0W之處理條件下，成為大致僅使用氧自由基之處理。
另外，由圖10所示之結果確認到：於氧灰化處理時，未施加RF偏壓之情況與施加了RF偏壓之情況相比，親水性之經時變化較小。上文中雖於圖8之說明中已述，於氧灰化處理時未施加RF偏壓之情況與施加了RF偏壓之情況相比，成為碳與氧之雙鍵(C=O)相對於碳與氧之單鍵(C-O)的比率較多之結果，可認為碳與氧之雙鍵(C=O)之比率較多之情況下可能親水性之經時變化小。
於本實施形態中，所謂親水性係表示電解鍍覆液附著 於樹脂層時的接觸角為20°以下，所謂疏水性係表示電解鍍覆液附著於樹脂層時的接觸角為20°以上。若電解鍍覆液附著於樹脂層時的接觸角為20°以下，進而佳為5°以下，則可將電解鍍覆液向通道孔5之進入良好化。接觸角係使用靜態液滴法而求出。將使電解鍍覆液之液滴接觸於樹脂層表面而液滴附著時的樹脂層表面與液滴所成之角度作為接觸角，取得液滴附著後之圖像，對圖像進行解析而算出接觸角。
為了將電解鍍覆液處理步驟中之電解鍍覆液向通道孔之進入良好化，亦包括接觸角之經時變化在內，氧灰化處理時之RF偏壓功率較佳為0W至30W，更佳為0W至10W。藉由使RF偏壓功率小於10W，可延長親水化效果之維持期間，可穩定地製造無連接不良狀況之電子構件。
另外，若藉由電解鍍覆處理而填埋有銅層之凹部(上述實施形態中之通道孔)之寬度變窄至例如200μm以下，或深度如例如10μm至30μm般增大，則於不施加RF偏壓而進行氧灰化處理之情形時，有時氧自由基難以進入至凹部之底部，無法充分進行凹部內部之有機樹脂層表面之親水化處理。於此種情形時，較理想為施加RF偏壓俾使氧自由基進入至凹部內部，亦可兼顧親水性效果之維持而例如將RF偏壓設為10W至30W。
藉由設為10W以上，即便於通道形成用之孔之寬度窄 或深度深之情形時，氧自由基可進入至凹部內部，可進行凹部內部之樹脂層表面之親水處理化。
另外，藉由使RF偏壓小於10W，可延長親水化效果之維持期間。另外，於本實施形態中，雖列舉銅通道之形成為例進行了說明，但亦可應用於銅配線之形成，於該情形時，供電解鍍覆液進入之凹部之形狀成為槽形狀。
於上述實施形態中，雖於氧灰化處理步驟中將壓力設為70Pa但不限定於此，例如亦可於10Pa至100Pa之範圍進行處理。有機樹脂層表面之親水化之效果於該範圍並無差異，可充分獲得親水化效果。若壓力小於10Pa則自由基之產生量不充分，若大於100Pa則到達基板之自由基量受到抑制。
另外，處理時間亦可為3秒以上之範圍。若短於3秒則無法進行充分之親水化處理。
另外，磁控管之功率亦可為500W至1500W之範圍。若小於500W則無法進行充分之親水化處理。上限值係由裝置構成上之上限值而決定，例如為1500W。
另外，關於RF偏壓功率，如上所述，無論是否施加RF偏壓均可藉由氧灰化處理而獲得親水性化之效果。進而，RF偏壓功率越小，越可使親水性效果之維持良好。
於氧灰化處理步驟中，雖於上述實施形態中將基板台溫度設定為25℃，但不限定於此。
圖11為表示電解鍍覆液附著於僅變更基板台溫度且將其他處理條件設為相同處理條件而進行氧灰化的半導體基板中之有機樹脂層時的接觸角的圖。
於圖11中，將如下半導體基板作為試樣：準備依照上述製造方法進行至利用O2/N2/CF4之混合氣體之蝕刻處理(S102)後的半導體基板，僅變更氧灰化處理時之基板台溫度，且其他氧灰化條件係設為與上述氧灰化處理(S103)的製造方法相同而進行氧灰化處理所得之半導體基板。另外，圖11中之試樣中，有機樹脂層之材料係使用DOW公司製造之材料型號SPR3012之i-line Photo resist而非PBO。
於圖11中，自左開始依序表示電解鍍覆液附著於以下半導體基板各自的有機樹脂層之表面時的接觸角：未進行氧灰化處理之半導體基板、於氧灰化處理時之基板台溫度為50℃之條件下進行了處理之半導體基板、於100℃之條件下進行了處理之半導體基板、於150℃之條件下進行了處理之半導體基板、於200℃之條件下進行了處理之半導體基板、於250℃之條件下進行了處理之半導體基板。
如圖11所示般，無論基板台溫度為幾℃，藉由進行氧 灰化處理，與未進行氧灰化處理之情形相比確認到接觸角變小的情形。另外確認到，若基板台溫度為150℃以下則接觸角變得小於20°，若為100℃以下則接觸角小於5°而進一步變小，若為50℃以下則接觸角小於3°而更進一步變小。如此，可獲得氧灰化處理時之處理溫度越低接觸角越小的有機樹脂層。
較理想為於氧灰化處理步驟中將基板台溫度設為25℃至150℃，藉由設為此種溫度條件，可充分進行有機樹脂層之親水化處理，可將後續步驟之電解鍍覆處理步驟中的電解鍍覆液向通道孔之進入良好化。若基板台溫度低於150℃，則因暴露於氧自由基下而形成C(碳)與O(氧)之鍵。若基板台溫度高於150℃，則接觸角變高而無法獲得充分之親水化效果。另外，於處理對象物為具備晶片之基板之情形時，就保持晶片之品質之觀點而言，較佳為於150°以下進行處理。
如以上般，於本發明中，在使用含氟之反應氣體之蝕刻處理後進行氧灰化處理，藉此可將有機樹脂層之表面親水化，可將後續之電解鍍覆處理步驟中的電解鍍覆液向通道孔之進入良好化。藉此，可獲得無配線不良狀況之電子構件。
以上，對本發明之實施形態進行了說明，但本發明並 非僅限定於上述實施形態，當然可於不偏離本發明之主旨之範圍內加以各種變更。於上述實施形態中，雖列舉再配線層中之銅通道形成步驟為例進行了說明，但不限定於此。可應用於以下情形：將有機樹脂層作為遮罩並藉由電解鍍覆在形成於有機樹脂層之凹部內形成第三金屬層的製造方法，且有機樹脂層表面於電解鍍覆處理步驟之前的步驟中因使用含氟之反應氣體之電漿處理而呈疏水性。

Claims (5)

  1. 一種電子構件的製造方法，係包括：於基板上形成第一金屬層；於前述第一金屬層上形成第二金屬層；於前述第二金屬層上形成由有機樹脂層所構成之遮罩；介隔前述遮罩而使用含氟之反應氣體對前述第二金屬層進行電漿蝕刻，於前述有機樹脂層與前述第二金屬層之積層膜形成在厚度方向貫穿前述有機樹脂層的凹部；對前述凹部之內部表面進行氧灰化處理；於前述氧灰化處理後，藉由電解鍍覆處理以第三金屬層對前述凹部內進行填埋；在以前述第三金屬層填埋了前述凹部內以後，去除前述有機樹脂層。
  2. 如請求項1所記載之電子構件的製造方法，其中前述第二金屬層包含鈦。
  3. 如請求項1或2所記載之電子構件的製造方法，其中前述蝕刻步驟係使用氧氣、氮氣及四氟化碳之混合氣體作為前述反應氣體而進行。
  4. 如請求項1或2所記載之電子構件的製造方法，其中前述氧灰化處理步驟係使用以氧自由基為主之氧電漿而進行。
  5. 如請求項3所記載之電子構件的製造方法，其中前述氧灰化處理步驟係使用以氧自由基為主之氧電漿而進行。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002212779A (ja) * 2001-01-10 2002-07-31 Hitachi Ltd 表面処理方法およびそれを用いた薄膜磁気ヘッドの製造方法と薄膜磁気ヘッド
US20030102284A1 (en) * 2000-01-31 2003-06-05 Walter Schmidt Method for fabricating micro-structures with various surface properties in multi-layer body by plasma etching
JP2009177152A (ja) * 2007-12-25 2009-08-06 Ngk Spark Plug Co Ltd 配線基板の製造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04196429A (ja) * 1990-11-28 1992-07-16 Nec Corp 半導体集積回路装置の製造方法
EP0877417A1 (en) 1997-05-09 1998-11-11 Lucent Technologies Inc. Method for fabrication of electrodes and other electrically-conductive structures
US6333560B1 (en) * 1999-01-14 2001-12-25 International Business Machines Corporation Process and structure for an interlock and high performance multilevel structures for chip interconnects and packaging technologies
JP4050631B2 (ja) 2003-02-21 2008-02-20 株式会社ルネサステクノロジ 電子デバイスの製造方法
KR101064336B1 (ko) * 2003-10-08 2011-09-16 허니웰 인터내셔널 인코포레이티드 실릴화제를 이용한 저-ｋ 유전물질로의 손상 보수
JP5062558B2 (ja) * 2006-07-25 2012-10-31 Ｎｌｔテクノロジー株式会社 アクティブマトリクス基板の製造方法
CN103299396B (zh) 2011-06-23 2015-11-25 旭化成电子材料株式会社 微细图案形成用积层体及微细图案形成用积层体的制造方法
JP5783142B2 (ja) 2011-07-25 2015-09-24 信越化学工業株式会社 化学増幅ポジ型レジスト材料及びパターン形成方法
KR101338225B1 (ko) 2011-10-26 2013-12-10 주식회사 케이씨씨 메틸클로로실란의 직접합성법에서 부산물로 생성되는 고비점 잔류물의 재분배 방법
KR20140130915A (ko) 2013-05-02 2014-11-12 삼성전자주식회사 범프를 갖는 반도체 소자를 제조하는 방법
KR102504833B1 (ko) * 2017-11-16 2023-03-02 삼성전자 주식회사 식각 가스 혼합물과 이를 이용한 패턴 형성 방법과 집적회로 소자의 제조 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030102284A1 (en) * 2000-01-31 2003-06-05 Walter Schmidt Method for fabricating micro-structures with various surface properties in multi-layer body by plasma etching
JP2002212779A (ja) * 2001-01-10 2002-07-31 Hitachi Ltd 表面処理方法およびそれを用いた薄膜磁気ヘッドの製造方法と薄膜磁気ヘッド
JP2009177152A (ja) * 2007-12-25 2009-08-06 Ngk Spark Plug Co Ltd 配線基板の製造方法

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