TWI685978B - 半導體元件及其製造方法 - Google Patents

半導體元件及其製造方法 Download PDF

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TWI685978B
TWI685978B TW108100348A TW108100348A TWI685978B TW I685978 B TWI685978 B TW I685978B TW 108100348 A TW108100348 A TW 108100348A TW 108100348 A TW108100348 A TW 108100348A TW I685978 B TWI685978 B TW I685978B
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layer
conductor layer
conductor
region
opening
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TW108100348A
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TW202027283A (zh
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廖宏魁
劉振強
時國昇
施詠堯
徐銘聰
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力晶積成電子製造股份有限公司
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Priority to TW108100348A priority Critical patent/TWI685978B/zh
Priority to CN201910079079.4A priority patent/CN111415933A/zh
Priority to US16/357,343 priority patent/US10784259B2/en
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Publication of TW202027283A publication Critical patent/TW202027283A/zh

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Abstract

一種半導體元件包括：基底、隔離結構、阻障結構、第一導體層、第二導體層、第一閘介電層以及第二閘介電層。基底具有第一區與第二區。阻障結構位於隔離結構上。第一導體層位於第一區上。第二導體層位於第二區上。第一閘介電層位於第一導體層與第一區的基底之間。第二閘介電層位於第二導體層與第二區的基底之間。隔離結構分隔第一閘介電層與第二閘介電層。亦提供一種半導體元件的製造方法。

Description

半導體元件及其製造方法
本發明是有關於一種積體電路及其製造方法，且特別是有關於一種半導體元件及其製造方法。
在積體電路製造技術中，對多晶矽進行預摻雜（pre-doping）植入製程可降低多晶矽的電阻值。另外，此預摻雜植入製程亦可減少多晶矽空乏現象（poly depletion phenomenon）。
然而，隨著積體電路愈變愈小，在預摻雜植入製程與退火製程之後，N型金屬氧化物半導體（N-Metal Oxide Semiconductor，NMOS）元件與P型金屬氧化物半導體（P-Metal Oxide Semiconductor，PMOS）元件之間的多晶矽閘極區域的相互擴散（inter-diffusion）情況將變得更加嚴重。此相互擴散將影響臨界電壓（threshold voltage），且進一步地限制未來微型化元件的發展。因此，如何提出一種半導體元件及其製造方法，以降低NMOS元件與PMOS元件之間多晶矽閘極區域的相互擴散將成為重要的一門課題。
本發明提供一種半導體元件，其藉由將阻障結構形成在第一導體層與第二導體層之間來降低第一導體層與第二導體層之間的相互擴散，以改善臨界電壓的控制，進而提升微型化半導體元件的能力。
本發明提供一種半導體元件及其製造方法，其利用鑲嵌製程（damascene process）形成第一導體層與第二導體層，以避免電漿損害（plasma induced damage，PID）的產生，進而提升產品的可靠度。
本發明提供一種半導體元件包括：基底、隔離結構、阻障結構、第一導體層、第二導體層、第一閘介電層以及第二閘介電層。基底具有第一區與第二區。阻障結構位於隔離結構上。第一導體層位於第一區上。第二導體層位於第二區上。第一閘介電層位於第一導體層與第一區的基底之間。第二閘介電層位於第二導體層與第二區的基底之間。隔離結構分隔第一閘介電層與第二閘介電層。
本發明提供一種半導體元件的製造方法，其步驟如下。於基底中形成隔離結構，以將基底分成第一區與第二區。於基底上全面性地形成阻障材料。圖案化阻障材料，以形成第一開口、第二開口以及位於第一開口與第二開口之間的阻障結構。於第一開口中形成第一閘介電層，並於第二開口中形成第二閘介電層。將導體材料填入第一開口與第二開口中。對導體材料進行平坦化製程，以於第一開口中形成第一導體層並於第二開口中形成第二導體層。
基於上述，本發明藉由在NMOS區域與PMOS區域之間形成阻障結構。在此情況下，本發明可在維持半導體元件的晶片使用面積時，避免NMOS元件的閘極與PMOS元件的閘極之間相互擴散，藉此改善臨界電壓的控制，進而提升微型化半導體元件的能力。另外，本發明還藉由鑲嵌製程來形成NMOS區域與PMOS區域中的閘極結構，以避免電漿損害的產生，進而提升產品的可靠度。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
參照本實施例之圖式以更全面地闡述本發明。然而，本發明亦可以各種不同的形式體現，而不應限於本文中所述之實施例。圖式中的層與區域的厚度會為了清楚起見而放大。相同或相似之標號表示相同或相似之元件，以下段落將不再一一贅述。
圖1A至圖1J是依照本發明第一實施例的一種半導體元件的製造流程的上視示意圖。圖2A至圖2J分別是沿著圖1A至圖1J的線I-I’的剖面示意圖。以下實施例是以平面式（planar）MOS元件為例來說明，但本發明不以此為限。
本發明第一實施例提供一種半導體元件的製造方法，其步驟如下所示。請參照圖1A與圖2A，首先，提供基底100。在一些實施例中，基底100是由矽或其他半導體材料製成的。另外，基底100也可包括其它元素半導體材料，例如鍺、砷化鎵或其它合適的半導體材料。此外，在替代實施例中，基底100亦可由例如矽鍺、碳化矽鍺、磷砷化鎵或磷銦化鎵的合金半導體所製成。
接著，於基底100中形成隔離結構101，以將基底100分成第一區R1與第二區R2。在一些實施例中，第一區R1與第二區R2可視為主動區AA。由上視圖1A所示，隔離結構101環繞第一區R1與第二區R2。由剖視圖2A所示，隔離結構101的頂面高於基底100的頂面。但本發明不以此為限，在其他實施例中，隔離結構101的頂面與基底100的頂面亦可實質上共平面。在一實施例中，隔離結構101的材料包括氧化矽、氮化矽、氮氧化矽或其組合。在替代實施例中，隔離結構101可以是淺溝渠隔離結構（STI）。
請參照圖1B與圖2B，於基底100上全面性地形成阻障材料102與介電層108。具體來說，阻障材料102包括第一阻障層104與第二阻障層106。第一阻障層104共形地覆蓋基底100與隔離結構101的表面。第二阻障層106覆蓋第一阻障層104的表面。介電層108覆蓋第二阻障層106的表面，使得第二阻障層106位於介電層108與第一阻障層104之間。在一實施例中，第一阻障層104可以是犧牲氧化物（例如是氧化矽），其厚度約為5.5 nm至6.5 nm，其形成方法可例如是化學氣相沉積法（CVD）、爐管氧化法、原子層沉積法（ALD）或其組合。第二阻障層106的材料包括氮化矽、氮氧化矽、碳化矽、或其組合，其厚度約為110 nm至130 nm，其形成方法可例如是CVD、ALD或其組合。介電層108的材料包括氧化矽、氮化矽、氮氧化矽、碳化矽、或其組合，其厚度約為40 nm至60 nm，其形成方法可例如是CVD、ALD或其組合。在替代實施例中，介電層108與第二阻障層106具有不同材料且第二阻障層106與第一阻障層104亦具有不同材料，以利於後續圖2C至圖2F的圖案化製程。舉例來說，第一阻障層104可例如是氧化矽層；第二阻障層106可以是氮化矽層；而介電層108可例如是四乙氧基矽烷（tetraethosiloxane，TEOS）層。
另外，在形成第一阻障層104之前，本實施例之半導體元件的製造方法更包括在基底100中形成摻雜區110、120。詳細地說，摻雜區110位於第一區R1的基底100中，其可視為P型井區，其所植入的摻質可例如是硼或銦（In），摻雜的濃度可例如是4.5´10 12/cm 3至5.5´10 12/cm 3。摻雜區120位於第二區R2的基底100中，其可視為N型井區，其所植入的摻質可例如是磷、砷或銻（Sb），摻雜的濃度可例如是5.5´10 12/cm 3至6.5´10 12/cm 3。在此情況下，具有P型井區110的第一區R1可視為NMOS區域；而具有N型井區120的第二區R2則可視為PMOS區域。
請參照圖1C與圖2C，於介電層108上形成第一罩幕圖案112。第一罩幕圖案112具有第一罩幕開口12。如上視圖1C所示，第一罩幕開口12為一條狀開口，其暴露出第一區R1、第二區R2以及第一區R1與第二區R2之間的介電層108。在一實施例中，第一罩幕圖案112的材料包括光阻材料，其形成方法可以是旋轉塗佈法與曝光顯影法。
請參照圖1C-1D與圖2C-2D，以第一罩幕圖案112為蝕刻罩幕，進行第一蝕刻製程，移除部分介電層108，以暴露出第二阻障層106。在一實施例中，第一蝕刻製程包括乾式蝕刻製程，其可例如是反應性離子蝕刻法（RIE）。在本實施例中，第二阻障層106可視為第一蝕刻製程的蝕刻停止層。
請參照圖1E與圖2E，在移除第一罩幕圖案112之後，於第二阻障層106上形成第二罩幕圖案114。如上視圖1E所示，第二罩幕圖案114位於第一區R1與第二區R2之間且橫跨第一罩幕開口12a。於此，第一罩幕開口12a複製圖1C與圖2C的第一罩幕開口12的形狀，且由介電層108a所定義。如剖視圖2E所示，第二罩幕圖案114對應於第一區R1與第二區R2之間的隔離結構101。在一實施例中，第二罩幕圖案114的材料包括光阻材料，其形成方法可以是旋轉塗佈法與曝光顯影法。
請參照圖1E-1F與圖2E-2F，以第二罩幕圖案114與介電層108a為蝕刻罩幕，進行第二蝕刻製程，移除部分第二阻障層106，以暴露出第一阻障層104。在一實施例中，第二蝕刻製程包括乾式蝕刻製程，其可例如是RIE。在本實施例中，第一阻障層104可視為第二蝕刻製程的蝕刻停止層。
請參照圖1F-1G與圖2F-2G，移除第一罩幕圖案114之後，進而移除未被第二阻障層106a所覆蓋的第一阻障層104，以暴露出第一區R1的基底100與第二區R2的基底100，進而形成了第一開口10與第二開口20。具體來說，第一開口10暴露出第一區R1的基底100（或摻雜區110）；而第二開口20暴露出第二區R2的基底100（或摻雜區120）。如圖2G所示，第一開口10與第二開口20由經圖案化的阻障材料102a的側壁所定義。在此情況下，位於第一開口10與第二開口20之間的隔離結構101上的經圖案化的阻障材料102a可視為阻障結構122，其包括下部124與上部126。在一些實施例中，阻障結構122的頂面122t與介電層108a的頂面108t具有高度差D1。高度差D1約為10 nm至20 nm。
請繼續參照圖1G與圖2G，在移除部分第一阻障層104之後，於第一開口10的基底100上形成第一閘介電層132並於第二開口20的基底100上形成第二閘介電層134。在此情況下，如圖1G所示，第一閘介電層132的頂面與第二閘介電層134的頂面低於隔離結構101的頂面。也就是說，隔離結構101分隔第一閘介電層132與第二閘介電層134。在一實施例中，第一閘介電層132與第二閘介電層134的材料包括介電材料，其可例如是氧化矽、氮化矽、氮氧化矽、高介電常數介電材料（例如介電常數大於4）或其組合，其厚度約為2 nm至7 nm，其形成方法可以是熱氧化法、CVD或其組合。在一些實施例中，第一閘介電層132與第二閘介電層134可同時形成，且具有相同厚度。在替代實施例中，第一閘介電層132與第二閘介電層134可依序形成，且具有不同厚度。
請參照圖1H與圖2H，全面性地形成導體材料128。具體來說，導體材料128填入第一開口10與第二開口20，且覆蓋阻障結構122的頂面122t與介電層108a的頂面108t。在一實施例中，導體材料128包括半導體材料，其形成方法可以是磊晶法、CVD或其組合。所述半導體材料可例如是摻雜多晶矽、非摻雜多晶矽、矽鍺、類似半導體材料或其組合。
請參照圖1H-1I與圖2H-2I，對導體材料128進行平坦化製程，以暴露出介電層108a的頂面108t。在一實施例中，所述平坦化製程可以是化學機械研磨（CMP）製程、回蝕刻製程或其組合。在此情況下，如圖2I所示，經平坦化的導體材料138包括第一部分138a、第二部分138b以及第三部分138c。具體來說，第一部分138a填入第一開口10中，其可視為第一導體層138a。第二部分138b填入第二開口20中，其可視為第二導體層138b。第三部分138c可視為第三導體層138c，其位於第一部分138a與第二部分138b之間且覆蓋阻障結構122的頂面122t。在一些實施例中，介電層108a可視為平坦化製程的研磨停止層或蝕刻停止層。在其他實施例中，在進行平坦化製程之後，導體材料138的頂面138t與介電層108a的頂面108t實質上共平面。在替代實施例中，導體材料138的頂面138t高於阻障結構122的頂面122t。另外，在進行平坦化製程期間，部分介電層108a亦會被損耗掉，使得介電層108a的厚度變薄。
請參照圖1I-1J與圖2I-2J，將第一導體層138a摻雜為N型導體層142（以下稱為第一導體層142），並將第二導體層138b摻雜為P型導體層144（以下稱為第二導體層144）。具體來說，在一實施例中，可將光阻圖案（未繪示）形成在導體材料138上，以暴露出第一導體層138a，接著，對第一導體層138a進行第一離子植入製程。所述第一離子植入製程可以是植入N型摻質，其可例如是磷、砷或銻（Sb），摻雜的濃度可例如是5.5´10 15/cm 3至6.5´10 15/cm 3。在另一實施例中，可將另一光阻圖案（未繪示）形成在導體材料138上，以暴露出第二導體層138b，接著，對第二導體層138b進行第二離子植入製程。所述第二離子植入製程可以是植入P型摻質，其可例如是硼或銦（In），摻雜的濃度可例如是3.0´10 15/cm 3至5.0´10 15/cm 3。在替代實施例中，第一離子植入製程可於第二離子植入製程之前或之後進行。
在進行第一離子植入製程與第二離子植入製程之後，進行退火（anneal）製程，以將N型摻質與P型摻質分別驅入至第一導體層142的下方與第二導體層144的下方，進而增加第一導體層142的下方與第二導體層144的下方的摻雜濃度。如此一來，便可去除第一導體層142與第一閘介電層132之間以及第二導體層144與第一閘介電層132之間的空乏層，藉此降低有效介電厚度（effective dielectric thickness）並提升飽和電流（saturation current）。在此情況下，部分N型摻質與部分P型摻質亦會分別驅入至第一導體層142與第二導體層144之間的第三導體層146。也就是說，第三導體層146具有N型摻質與P型摻質。
值得注意的是，本實施例藉由在第一區R1（或NMOS區域）與第二區R2（PMOS區域）之間形成阻障結構122。因此，本實施例可在維持半導體元件的晶片使用面積時，降低第一導體層142（其可視為NMOS元件的閘極）與第二導體層144（其可視為PMOS元件的閘極）之間的互相擴散，藉此改善臨界電壓的控制，進而提升微型化半導體元件的能力。另外，本實施例還藉由鑲嵌製程（如圖2H至圖2J所示）來形成第一導體層142與第二導體層144，以避免電漿損害的產生，進而提升產品的可靠度。
如圖2J所示，在進行退火製程之後，可在經摻雜的導體結構148上形成金屬矽化物層140。在一些實施例中，金屬矽化物層140的材料例如是矽化鎳（NiSi）、矽化鈷（CoSi）、矽化鈦（TiSi）、矽化鎢（WSi）、矽化鉬（MoSi）、矽化鉑（PtSi）、矽化鈀（PdSi）或其組合。金屬矽化物層140的形成方法為本領域技術人員所熟知，於此便不再詳述。
如圖2J所示，在形成金屬矽化物層140之後，進行濕式蝕刻製程，移除介電層108a及其下方的第二阻障層106a與第一阻障層104a，以暴露出隔離結構101。在一些實施例中，所述濕式蝕刻製程包括多道蝕刻步驟，以依序移除介電層108a、第二阻障層106a以及第一阻障層104a。舉例來說，可先利用稀釋氫氟酸（DHF）溶液來移除最上層的介電層108a，接著利用熱磷酸溶液來移除第二阻障層106a，最後再利用DHF溶液來移除最下層的第一阻障層104a。值得注意的是，由於介電層108a、第二阻障層106a以及第一阻障層104a所構成的堆疊結構與經摻雜的導體結構148以及金屬矽化物層140具有高的蝕刻選擇比，因此，在移除介電層108a、第二阻障層106a以及第一阻障層104a所構成的堆疊結構時，不會損耗或僅輕微損耗經摻雜的導體結構148以及金屬矽化物層140。
請參照圖2J，以上述方法所製造的半導體元件包括：基底100、隔離結構101、摻雜區110、120、阻障結構122、第一閘介電層132、第一導體層142、第二閘介電層134以及第二導體層144。具體來說，隔離結構101位於基底100中，以將基底100分隔成第一區R1與第二區R2。摻雜區110位於第一區R1的基底100中，以形成NMOS區域。摻雜區120位於第二區R2的基底100中，以形成PMOS區域。
如圖2J所示，阻障結構122位於第一區R1與第二區R2之間的隔離結構101上。第一導體層142位於第一區R1的基底100上，且第一閘介電層132位於第一導體層142與第一區R1的基底100之間。在一實施例中，第一閘介電層132與其上的第一導體層142可視為第一閘極結構130a。第二導體層144位於第二區R2的基底100上，且第二閘介電層134位於第二導體層144與第二區R2的基底100之間。在另一實施例中，第二閘介電層134與其上的第二導體層144可視為第二閘極結構130b。
值得注意的是，阻障結構122分隔第一導體層142與第二導體層144，其可降低第一導體層142（其可視為NMOS元件的閘極）與第二導體層144（其可視為PMOS元件的閘極）之間的互相擴散，藉此改善臨界電壓的控制。具體來說，阻障結構122包括下部124與上部126。在一些實施例中，下部124與上部126具有不同的介電材料。舉例來說，下部124可以是氧化矽層；而上部126則可以是氮化矽層。在替代實施例中，阻障結構122具有實質上垂直於基底100的頂面的側壁。
如圖2J所示，第一導體層142與第二導體層144藉由第三導體層146連接，以形成連續的導體結構148。導體結構148橫越阻障結構122且覆蓋第一閘介電層132與第二閘介電層134。在一些實施例中，由於第一導體層142與第二導體層144是藉由鑲嵌製程所形成，因此，第一導體層142與第二導體層144皆具有實質上垂直於基底100的頂面的側壁。另外，本實施例之半導體元件更包括金屬矽化物層140，其位於第一導體層142、第二導體層144以及阻障結構122（或第三導體層146）上，以降低第一導體層142與第二導體層144的阻抗。
圖3是依照本發明的第二實施例的一種半導體元件的剖面示意圖。
請參照圖3，基本上，第二實施例的半導體元件與第一實施例的半導體元件相似。上述兩者不同之處在於：第二實施例的半導體元件不具有圖2J的第三導體層146。也就是說，如圖3所示，第一導體層142的頂面142t、第二導體層144的頂面144t以及阻障結構222的頂面222t實質上共平面，且金屬矽化物層140’直接接觸第一導體層142的頂面142t、第二導體層144的頂面144t以及阻障結構222的頂面222t。
具體來說，上述第二實施例的半導體元件的製造方法的步驟如下所示。
圖4A至圖4J是依照本發明第二實施例的一種半導體元件的製造流程的上視示意圖。圖5A至圖5J分別是沿著圖4A至圖4J的線II-II’的剖面示意圖。
請參照圖4A-4C與圖5A-5C，基本上，圖4A-4C與圖5A-5C的步驟與圖1A-1C與圖2A-2C相似，且詳細步驟已於上述段落詳細說明過，於此便不再贅述。
請參照圖4C-4D與圖5C-5D，以第一罩幕圖案112為蝕刻罩幕，進行第一蝕刻製程，移除部分介電層108，以暴露出第二阻障層106。在本實施例中，部分第二阻障層106亦被移除，以在經凹蝕的第二阻障層106a上形成凹陷106r。也就是說，外露於第一罩幕開口12的第二阻障層106a的厚度降低。在一些實施例中，如圖5D所示，被介電層108a所覆蓋的第二阻障層106a的厚度大於未被介電層108a所覆蓋的第二阻障層106a的厚度。
請參照圖4E與圖5E，於經凹蝕的第二阻障層106a上或凹陷106r中形成第二罩幕圖案114。如上視圖5E所示，第二罩幕圖案114位於第一區R1與第二區R2之間且橫跨第一罩幕開口12a。於此，第一罩幕開口12a是由介電層108a所定義。如剖視圖5E所示，第二罩幕圖案114對應於第一區R1與第二區R2之間的隔離結構101。
請參照圖4E-4F與圖5E-5F，以第二罩幕圖案114與介電層108a為蝕刻罩幕，進行第二蝕刻製程，移除部分第二阻障層106a，以暴露出第一阻障層104。在本實施例中，第一阻障層104可視為第二蝕刻製程的蝕刻停止層。
請參照圖4F-4G與圖5F-5G，移除第一罩幕圖案114之後，進而移除未被第二阻障層106b所覆蓋的第一阻障層104，以暴露出第一區R1的基底100與第二區R2的基底100，進而形成了第一開口10與第二開口20。具體來說，第一開口10暴露出第一區R1的基底100（或摻雜區110）；而第二開口20暴露出第二區R2的基底100（或摻雜區120）。如圖5G所示，第一開口10與第二開口20由經圖案化的阻障材料102a的側壁所定義。在此情況下，位於第一開口10與第二開口20之間的隔離結構101上的經圖案化的阻障材料102a可視為阻障結構222，其包括下部224與上部226。在一些實施例中，阻障結構222的頂面222t與第二阻障層106b的頂面106t具有高度差D2。高度差D2約為10 nm至20 nm。在替代實施例中，阻障結構222的上部226的厚度小於第二阻障層106b的厚度。
請繼續參照圖4G與圖5G，在移除部分第一阻障層104之後，於第一開口10的基底100上形成第一閘介電層132並於第二開口20的基底100上形成第二閘介電層134。在此情況下，如圖5G所示，第一閘介電層132的頂面與第二閘介電層134的頂面低於隔離結構101的頂面。也就是說，隔離結構101分隔第一閘介電層132與第二閘介電層134。
請參照圖4H與圖5H，全面性地形成導體材料128。具體來說，導體材料128填入第一開口10與第二開口20，且覆蓋阻障結構222的頂面222t與介電層108a的頂面108t。
請參照圖4H-4I與圖5H-5I，對導體材料128進行平坦化製程，以暴露出第二阻障層106b的頂面106t。在此情況下，如圖5I所示，經平坦化的導體材料138包括第一部分138a、第二部分138b以及第三部分138c。具體來說，第一部分138a填入第一開口10中，其可視為第一導體層138a。第二部分138b填入第二開口20中，其可視為第二導體層138b。第三部分138c可視為第三導體層138c，其位於第一部分138a與第二部分138b之間且覆蓋阻障結構222的頂面222t。在一些實施例中，第二阻障層106b可視為平坦化製程的研磨停止層或蝕刻停止層。在其他實施例中，在進行平坦化製程之後，導體材料138的頂面138t與第二阻障層106b的頂面106t實質上共平面。
請參照圖4I-4J與圖5I-5J，將第一導體層138a摻雜為N型導體層142（以下稱為第一導體層142），並將第二導體層138b摻雜為P型導體層144（以下稱為第二導體層144）。接著，進行退火製程，以將N型摻質與P型摻質分別驅入至第一導體層142的下方與第二導體層144的下方。
如圖5J所示，在進行退火製程之後，進行金屬矽化製程，以於第一導體層142、第二導體層144以及阻障結構222上形成金屬矽化物層140’。在一些實施例中，所述金屬矽化製程的步驟包括：沉積金屬層，再進行加熱製程，以使金屬層與部分導體層反應，藉此形成金屬矽化物層140’。在本實施例中，阻障結構222上的第三導體層138c（如圖5I所示）會與所述金屬層反應，以完全矽化（fully silicide）為金屬矽化物層140’。在此情況下，金屬矽化物層140’覆蓋且直接接觸第一導體層142的頂面142t、第二導體層144的頂面144t以及阻障結構222的頂面222t。
綜上所述，本發明藉由在NMOS區域與PMOS區域之間形成阻障結構。在此情況下，本發明可在維持半導體元件的晶片使用面積時，避免NMOS元件的閘極與PMOS元件的閘極之間相互擴散，藉此改善臨界電壓的控制，進而提升微型化半導體元件的能力。另外，本發明還藉由鑲嵌製程來形成NMOS區域與PMOS區域中的閘極結構，以避免電漿損害的產生，進而提升產品的可靠度。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10‧‧‧第一開口
12、12a‧‧‧第一罩幕開口
20‧‧‧第二開口
100‧‧‧基底
101‧‧‧隔離結構
102、102a‧‧‧阻障材料
104、104a‧‧‧第一阻障層
106、106a、106b‧‧‧第二阻障層
106r‧‧‧凹陷
108、108a‧‧‧介電層
108t‧‧‧介電層的頂面
110、120‧‧‧摻雜區
112‧‧‧第一罩幕圖案
114‧‧‧第二罩幕圖案
122、222‧‧‧阻障結構
122t、222t‧‧‧阻障結構的頂面
124‧‧‧下部
126‧‧‧上部
128‧‧‧導體材料
130a‧‧‧第一閘極結構
130b‧‧‧第二閘極結構
132‧‧‧第一閘介電層
134‧‧‧第二閘介電層
138‧‧‧導體材料
138t‧‧‧導體材料的頂面
138a、142‧‧‧第一導體層
142t‧‧‧第一導體層的頂面
138b、144‧‧‧第二導體層
144t‧‧‧第二導體層的頂面
138c、146‧‧‧第三導體層
140、140’‧‧‧金屬矽化物層
148‧‧‧導體結構
AA‧‧‧主動區
D1、D2‧‧‧高度差
R1‧‧‧第一區
R2‧‧‧第二區
圖1A至圖1J是依照本發明第一實施例的一種半導體元件的製造流程的上視示意圖。 圖2A至圖2J分別是沿著圖1A至圖1J的線I-I’的剖面示意圖。 圖3是依照本發明的第二實施例的一種半導體元件的剖面示意圖。 圖4A至圖4J是依照本發明第二實施例的一種半導體元件的製造流程的上視示意圖。 圖5A至圖5J分別是沿著圖4A至圖4J的線II-II’的剖面示意圖。
100‧‧‧基底
101‧‧‧隔離結構
110、120‧‧‧摻雜區
122‧‧‧阻障結構
122t‧‧‧阻障結構的頂面
124‧‧‧下部
126‧‧‧上部
130a‧‧‧第一閘極結構
130b‧‧‧第二閘極結構
132‧‧‧第一閘介電層
134‧‧‧第二閘介電層
142‧‧‧第一導體層
144‧‧‧第二導體層
146‧‧‧第三導體層
140‧‧‧金屬矽化物層
148‧‧‧導體結構
R1‧‧‧第一區
R2‧‧‧第二區

Claims (9)

  1. 一種半導體元件，包括：基底，具有第一區與第二區；隔離結構，位於所述第一區與所述第二區之間的所述基底中；阻障結構，位於所述隔離結構上；第一導體層，位於所述第一區上；第二導體層，位於所述第二區上，其中所述阻障結構分隔所述第一導體層與所述第二導體層，且所述第一導體層的頂面、所述第二導體層的頂面以及所述阻障結構的頂面實質上共平面；第一閘介電層，位於所述第一導體層與所述第一區的所述基底之間；以及第二閘介電層，位於所述第二導體層與所述第二區的所述基底之間，其中所述隔離結構分隔所述第一閘介電層與所述第二閘介電層。
  2. 如申請專利範圍第1項所述的半導體元件，其中所述阻障結構包括下部與上部，所述下部與所述上部具有不同的介電材料。
  3. 如申請專利範圍第1項所述的半導體元件，其中所述第一導體層與所述第二導體層彼此連接以形成連續的導體結構，所述導體結構橫越所述阻障結構且覆蓋所述第一閘介電層與所述第二閘介電層。
  4. 如申請專利範圍第3項所述的半導體元件，其中所述導體結構包括：所述第一導體層，具有N型摻質；所述第二導體層，具有P型摻質；以及第三導體層，位於所述第一導體層與所述第二導體層之間且具有所述N型摻質與所述P型摻質。
  5. 如申請專利範圍第1項所述的半導體元件，更包括：金屬矽化物層位於所述第一導體層、所述第二導體層以及所述阻障結構上。
  6. 一種半導體元件的製造方法，包括：於基底中形成隔離結構，以將所述基底分成第一區與第二區；於所述基底上全面性地形成阻障材料；圖案化所述阻障材料，以形成第一開口、第二開口以及位於所述第一開口與所述第二開口之間的阻障結構；於所述第一開口中形成第一閘介電層，並於所述第二開口中形成第二閘介電層；將導體材料填入所述第一開口與所述第二開口中；以及對所述導體材料進行平坦化製程，以於所述第一開口中形成第一導體層並於所述第二開口中形成第二導體層。
  7. 如申請專利範圍第6項所述的半導體元件的製造方法，其中第一導體層與所述第二導體層彼此連接以形成連續的導體結 構，所述導體結構橫越所述阻障結構並填入所述第一開口與所述第二開口中。
  8. 如申請專利範圍第6項所述的半導體元件的製造方法，其中所述圖案化所述阻障材料的步驟包括：於所述阻障材料上形成第一罩幕圖案；以所述第一罩幕圖案為蝕刻罩幕進行第一蝕刻製程，以在所述阻障材料上形成凹陷；於所述凹陷中形成第二罩幕圖案；以及以所述第二罩幕圖案為蝕刻罩幕進行第二蝕刻製程，以形成所述第一開口與所述第二開口，其分別暴露出所述第一區與所述第二區的所述基底。
  9. 如申請專利範圍第6項所述的半導體元件的製造方法，更包括：進行第一離子植入製程，以將所述第一導體層摻雜為N型；進行第二離子植入製程，以將所述第二導體層摻雜為P型；以及於所述第一導體層、所述第二導體層以及所述阻障結構上形成金屬矽化物層。
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