TW471136B - Manufacturing method for MOS transistor of embedded memory - Google Patents

Abstract

The present invention provides a manufacturing method for MOS transistor of embedded memory, which includes the following steps: sequentially forming a first dielectric layer and an undoped polysilicon layer on the surface of the semiconductor chip with a memory area region and a periphery circuit region defined; then, doping the undoped polysilicon layer on the memory array region and forming a passivation layer on the surface of the semiconductor chip; conducting a first photolithography and etching process (PEP) to etch the passivation layer and the doped polysilicon layer on the memory array region for forming a plurality of gates; forming the lightly doped drain (LDD) around each of the gates; forming a silicon nitride layer and a second dielectric layer on the surface of the semiconductor chip; removing the second dielectric layer, the silicon nitride layer and the passivation layer on the periphery circuit region; finally, conducting a second PEP to etch the undoped polysilicon layer on the periphery circuit region for forming a plurality of gates; then, forming the LDD, the spacer, and the source/drain (S/D) of each of the MOS transistors in the periphery circuit region.

Description

471136 V. Description of the invention (1) Field of the invention The present invention provides a method for manufacturing a MOS transistor with embedded memory. Background Description With the continuous increase of process integration, the current trend of making semiconductor integrated circuits is to integrate memory cell arrays (mem ryce 1 1 array) and high-speed logic circuit elements. It is fabricated on a chip to form a kind of German-type memory that combines a memory array and logic circuits (10giccircuits) at the same time, so as to greatly save area and speed up signal processing. Please refer to FIG. 1 to FIG. 8. FIG. 1 to FIG. 8 are schematic diagrams of a conventional method for fabricating a MOS transistor of an embedded memory on a semiconductor wafer 10. The semiconductor wafer 10 includes a silicon substrate 16, and a memory array region 12 and a peripheral circuit region 14 have been previously defined on the surface of the silicon substrate 16. The memory array area 12 further includes a cell-well 18, and the peripheral circuit area 14 also includes a P-well 1 and an N-wel 1 ) 22, and each area is separated by a plurality of shallow trench isolations 11. As shown in Figure 1, it is known to make M0S transistors of embedded memory.

471136 V. Description of the invention (2) The method is to first form a silicon oxide layer on the surface of the silicon substrate 16 by a thermal oxidation method, which is used as the gate oxide layer 24 of each MOS transistor, and then on the gate oxide layer 2 An undoped polysilicon layer 26 and an insu 1 ati η layer 8 are sequentially formed on the 4 surface. Then, as shown in FIG. 2, a photoresist layer 30 is formed as a hard mask over the peripheral circuit area 14, and a yellow light and etching process (PEP) is used to etch the insulation layer over the memory array area 12. 28 and the undoped polycrystalline silicon layer 26 to the surface of the gate oxide layer 24. After the photoresist layer 30 has been completely removed, as shown in FIG. 3, a doped polycrystalline silicon layer 3 2, a metal silicide layer 3 4, an insulating layer 36, and Nitride stone evening layer 38. As shown in FIG. 4, a photoresist layer 40 is then formed on the surface of the semiconductor wafer 10, and a plurality of gate 41 patterns are defined in the photoresist layer 40 above the memory array area 12. Then, each gate is used. The electrode 4 1 pattern is used as a mask, and the silicon nitride layer 3 8, the insulating layer 3 6, the metal silicide layer 3 4, and the doped polycrystalline silicon layer 32 are etched in the memory array region 12 until the gate of the silicon substrate 16 is oxidized. On the surface of the layer 24, a gate 41 of each MOS transistor is formed on the memory array region 12. Then, an ion layout process is performed to form the lightly doped drain (LDD) of each M0S transistor in the memory array region 42 °. The photoresist layer 40 and the gate electrode 41 are not covered completely. After the gate oxide layer 24, as shown in FIG. 5, an insulating layer 44 is formed before the surface of the semiconductor wafer 10, and the thickness of the insulating layer 44 is greater than that of each of the peripheral circuit regions 14.

Page 6 471136 V. Description of the invention (3) The total thickness of the layer 'is followed by a chemical mechanical polishing process (chemicaliechanical ρ ο 1 ishing, abbreviated as C) using the nitrided layer 3 8 of the peripheral circuit area 14 as the stop layer' MP) so that the insulating layer 44 above the memory array region 12 and the silicon nitride layer 38 of the peripheral circuit region 14 approximately form a horizontal plane. Subsequently, as shown in FIG. 6, the silicon nitride layer 38, the insulating layer 36, the metal silicide layer 34, the doped polycrystalline silicon layer 32, and the insulating layer 2 8 ′ of the peripheral circuit region 14 are etched until the undoped polycrystalline silicon is exposed Layer 2 6 surface. Next, a photoresist layer 46 'is formed on the surface of the semiconductor wafer 10 and a yellow light process is performed to define a plurality of gates of PM0S and NM0S in the photoresist layer 46 above the peripheral circuit area 14. 4 47 patterns, and then use the gate 47 pattern in the photoresist layer 46 as a hard mask, and also use the insulating layer 4 4 above the d fe array region 12 as a mask to protect each of the memory array regions 12 The gate 41 structure is formed by engraving the undoped polycrystalline silicon layer 2 6 ′ of the peripheral circuit region 14 to the surface of the gate oxide layer 24 to form a gate 47 of ρ μOS and N M 0 S. A lightly doped drain (1 D D) 4 2 of each ρ μ s and N M 0 S is then formed using an ion-distribution process. As shown in FIG. 7, 'Next, a helium ^ chip (not shown) is formed on the surface of the semiconductor wafer 10 and an anisotropic (an 丨 s 0 tr 〇pic > | A spacer 48 is formed around each of the gates 4 7 in the area 1 4. Then, two yellow light processes are used to perform two ion implantation processes in different implantation areas to the peripheral circuit area 1. A source 50 and a drain 52 of NMOS and PMOS transistors are respectively formed above p-type well 20 and N-type well 22 of 4.

Page 7 471136 Explanation (4) Finally, as shown in FIG. 8, the surface of the semiconductor wafer 10 is reduced by: clock (spu 11 er)-a metal layer (not shown) made of metal (T i), and then a temperature The first rapid thermal processing (RTP) process with a range of 50 ° C ~ 7 0 (TC and heating time of about 30 seconds), so that titanium (Ti) atoms in the metal layer can diffuse into the peripheral circuit area 1 4 The surface of each of the source 50, the drain 52, and the gate 47. A wet etching is then performed to remove the unreacted metal layer on the surface of the semiconductor wafer 10. Finally, a temperature range of 700 ° C is performed. A second rapid thermal processing (RTP) process at ~ 90 ° C and a heating time of about 30 seconds to form a surface of each of the source 50, the drain 5 2 and the gate 4 7 on the peripheral circuit area 14 Align the metal oxide layer 5 4 by itself. Because the gate 4 1 of the memory array area 12 needs a cap 1 ayer 3 8 to facilitate subsequent self-aligned contacts (se 1 f-a 1 igned contact (SAC for short) process, and in the peripheral circuit area 14 for subsequent self-aligned metal silicidation (Salicide process) to reduce the sheet resistance (R s) on the surface of each source 50, drain 52, and gate 47, so a protective layer cannot be formed on the top of gates 4 and 7. In the conventional method of manufacturing M0S transistors of embedded memory, multiple yellow light and etching processes must be performed repeatedly to integrate gate fabrication in the memory array region and peripheral circuit regions, thereby increasing the complexity and production of the process. Cost and reduce throughput. Summary of Invention

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47113G V. Description of the invention (5) — The main purpose of the present invention is to provide a method for manufacturing MOS transistors with embedded memory, which integrates the gate process in the memory array area and the peripheral circuit area, and achieves Simplify ^ of ^. In the method of the present invention, a first dielectric layer and an undoped surface are sequentially formed on a surface of a semiconductor wafer having a memory array area (memQ; ry array area) and peripheral circuits area defined. The polycrystalline silicon layer is then doped with the undoped polycrystalline silicon layer above the memory array region, and a protective layer is formed on the surface of the semiconductor wafer. Subsequently, a first yellow light and etching process (PEP) is performed, and the protective layer and the doped polycrystalline silicon layer on the array region are etched to form a plurality of gate μ electrodes, and then formed around each of the gate electrodes. Lightly doped drain (LDD). Next, a nitrogen stone layer and a second dielectric layer are formed on the surface of the semiconductor wafer, and then the second dielectric layer, the nitrogen silicon layer, and the protective layer on the peripheral circuit area are removed, and finally a second PEP is performed. , Etching the non-doped polycrystalline silicon layer above the peripheral circuit region to form a plurality of gates, and then forming the LDD, the spacer, and the source / impulse of each M 0 S transistor in the peripheral circuit region (S / D). By using the manufacturing method of the MOS transistor of the embedded memory of the present invention, the gate process in the memory array region and the peripheral circuit region can be integrated, and the thermal budget of the automatic metal silicide process can be reduced.

Page 9 471136 V. Description of the invention (6) To reduce the complexity and production cost of the process. Detailed description of the invention Please refer to FIG. 9 to FIG. 16, which are schematic diagrams of a method for fabricating an embedded memory MOS transistor on a semi-conductor wafer 60 according to the present invention. The semiconductor chip 60 includes a silicon substrate 66, and a memory array region 62 and a peripheral circuit region 64 have been defined on the surface of the silicon substrate 66. The memory array region 62 includes at least one cell well 68 and peripheral circuits. The area 64 includes at least one P-type well 70 and at least one N-type well 72, and each area is separated by a plurality of shallow trench isolations 61. As shown in FIG. 9, in the method of the present invention, a dielectric layer 74 and an undoped polycrystalline silicon layer 76 are sequentially formed before the surface of the semiconductor wafer 60. The dielectric layer 74 is composed of silicon dioxide (SiO2) and is used as a gate oxide layer of each MOS transistor. Then, a yellow light (Ithography) process is used to perform an ion implantation process on the undoped polycrystalline silicon layer 7 6 above the memory array region 62 to make the undoped polycrystalline silicon layer 7 6 above the memory array region 62. Formed as a doped polycrystalline silicon layer 7 7. Next, as shown in FIG. 10, a protective layer 78 and a photoresist layer 80 are sequentially formed on the surface of the semiconductor wafer 60. The protective layer 78 is composed of a nitrogen silicon compound, and the protective layer 78 and A silicon nitride oxide (S i 0 XN y) layer (not shown) is further included between the doped polycrystalline silicon layers 7 and 6 as an anti-reflection layer.

Page 10 471136 V. Description of Invention (7) (ARC). As shown in FIG. 11, a photolithography, exposure, and development process is subsequently performed to define a plurality of photoresist layers 80 in the photoresist layer 80 above the cell well 68 in the memory array region 62. Pattern of gate 8 丨. The pattern of the photoresist layer 80 is then used as a hard mask to etch the protective layer 78 and the doped polycrystalline silicon over the memory array region 62; the layer 7 7 to the surface of the dielectric layer 74. Then, an ion implantation process is performed to form a lightly doped drain (LDD) 82 of each MOS transistor in the memory array region 62. After the photoresist layer 80 and the gate oxide layer 7 4 not covered by the gates 81 are completely removed, as shown in FIG. 12, it is then convenient to sequentially form a silicon silicon nitride on the surface of the semiconductor wafer 60. The layer 84 and a dielectric layer 86 cover the surfaces of the gates 81 on the memory array region 62. Subsequently, as shown in FIG. 13, a photoresist layer 8 8 is formed as a mask over the memory array area 62 to remove the dielectric layer 86, the nitrogen oxide layer 84 and the protective layer 78 on the peripheral circuit bar 64. . As shown in FIG. 14 ', a photoresist layer 90 is then formed on the surface of the semiconductor wafer 60. Among them, before the photoresist layer 90 is formed, a silicon nitride oxide (SiOxNy) layer (not shown) may be formed as an anti-reflection layer (ARC) before the surface of the semiconductor wafer 60. Next, a yellow light process is performed to define a plurality of gate electrodes 9 1 $ patterns in the photoresist layer 9 0 above the N-type well 72 and the p-type well 70 in the peripheral circuit area 64. The pattern of the photoresist layer 90 is then used as a hard mask, and the undoped polycrystalline silicon layer 76 above the peripheral circuit area 64 is etched to the surface of the dielectric layer 74 to form each MOS transistor on the peripheral circuit area 64. Of the gate 91. Go on

Page 11 471136 V. Description of the invention (8) An ion implantation process is performed to form a lightly doped drain (LDD) 82 in the peripheral circuit region 64. St

The B-body is then removed from the photoresist layer 90 and the gasification layer (not shown) formed below the photoresist layer 90. As shown in FIG. 15, a nitrogen stone layer (not shown) is formed on the surface of the semiconductor wafer 60, and covers the surface of each gate 91 on the peripheral circuit area 64. Then, two yellow light and etching (PEP) processes are used to perform subsequent processes on the pM0s transistor and N M 0 S transistor, that is, the first PEP is performed first to etch the P-type of the peripheral circuit area 64. The nitrogen-silicon layer 'around each gate 91 above the well 70 forms a sidewall 92 and performs an ion implantation process to form the source 94 and the drain 96 of the NMOS transistor in the P-well 70. Then a second PEP is performed to etch the nitrogen-silicon layer around each gate 9 1 above the N-type well 72 in the peripheral circuit area 64 to form a sidewall 92, and then perform an ion implantation process to A source 94 and a drain 96 of a PMOS transistor are formed in the N-type well 72. The above two ion implantation processes will dope the undoped polycrystalline silicon layer 76 in each gate 91 above the p-type well 0 and the% -well 72, respectively. As shown in FIG. 16, after the source 9 4 and the drain 9 6 of each MOS transistor on the peripheral circuit area 64 are prepared, the gate oxide layer 7 not covered by the gates 9 1 is removed first. 4. Next, a metal layer (not shown) made of cobalt (Co) is deposited on the surface of the semiconductor crystal plane 60, and the metal layer covers each of the source electrodes 9 4, the drain electrodes 96, and the gates on the peripheral circuit area 64. Pole 9 1 above the surface. Then, a first rapid heat treatment (RTP) process is performed at a temperature range of 40 (TC ~ 600 ° C and a heating time of 10 ~ 50 seconds), so that the cobalt (Co) atoms in the metal layer can be

Page 12 471136 V. Description of the invention (9) Diffusion into the surface of each source 9 4, drain 9 6 and gate 9 1. Then, a wet etching is performed to remove the unreacted metal layer on the surface of the semiconductor wafer 60. Finally, a second rapid thermal processing (RTP) process is performed in a temperature range of 600 ° C to 80 ° C and a heating time of 10 to 50 seconds, so that each source 9 4 on the peripheral circuit area 64 A self-aligned silicide layer 98 is formed on the surfaces of the drain electrode 96 and the gate electrode 91. The metal layer may be replaced by a metal such as titanium (Ti), nickel (Ni), or molybdenum (Mo). To sum up the above description, the method for manufacturing an M0S transistor of an embedded memory of the present invention is to form a gate oxide layer 7 4, an undoped polycrystalline silicon layer 76 and a protective layer 7 before the surface of the semiconductor wafer 60. 8. Next, a gate 81 structure of each MOS transistor is formed in the memory array region 62, and then a nitrogen oxide layer 84 and a dielectric layer 86 are sequentially formed on the surface of the semiconductor wafer 60, and then the peripheral circuits are removed. The dielectric layer 86, the nitrogen fragmentation layer 84, and the protective layer 78 above the region 64 are formed in the peripheral circuit region 64 to form a gate 91 structure of each MOS transistor. Compared with the conventional method for making M0S transistors in embedded memory, the present invention uses a polycrystalline silicon layer as a conductive layer in the peripheral circuit area and the memory array area in the manufacturing process of the M0S transistor, thus reducing many chemistry Deposition and etching procedures reduce process complexity and production costs. The above are only the preferred embodiments of the present invention. Any equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall be covered by the patent of the present invention.

Page 13 471136 V. Description of the Invention (ίο) Scope.

Hi Page 14 471136 Simple illustration of the diagrams Simple illustrations of the diagrams Figures 1 to 8 are schematic diagrams of a conventional method for making a MOS transistor of an embedded memory. Figures 9 to 16 show the methods of making an embedded memory according to the present invention. MOS transistor method schematic diagram Symbol description 10 Semiconductor wafer 11 Shallow trench isolation 12 1 Memory array area 14 Peripheral circuit area 16 Silicon substrate 18 Cell well 20 P-type well 22 N-type well 24 Gate oxide layer 26 Doped polycrystalline silicon layer 28 ^ 36 ^ 44 insulating layer 30, 40, 46 photoresist layer 32 doped polycrystalline silicon layer 34 metal silicide layer 38 silicon nitride layer 41, 47 gate 42 lightly doped drain 48 side wall 50 source Pole 52 Drain 54 White-aligned metal silicide layer 60 Semiconductor wafer 61 Shallow trench isolation 62 Memory circuit area

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47113G Schematic description

64 Peripheral circuit area 66 Silicon substrate 68 Cell well 70 P-type well 72 N-type 丼 74, 86 Dielectric layer 76 Undoped polycrystalline silicon layer 77 Doped polycrystalline silicon 78 Protective layer 80, 88> 90 Photoresistive layer 81, 91 Gate Electrode 82 lightly doped drain electrode 84 silicon nitride layer 92 side wall 94 source electrode 96 drain electrode 98 commercial alignment metal silicide layer page 16

Claims (1)

471136 VI. Application Patent Scope 1. A method for manufacturing a metal oxide semiconductor (MOS) transistor with embedded memory, the method includes the following steps: providing a semiconductor wafer, and A memory array area and a peripheral circuits region have been defined on the surface of the silicon substrate of the semiconductor wafer; a first dielectric layer is sequentially formed on the surface of the semiconductor wafer and An undoped polysilicon (unoped polysi 1 icon) layer; performing a first ion implantation process (i ο nimp 1 antati ο η) on the undoped polysilicon layer above the memory array region to make the memory array region The undoped polycrystalline silicon layer above is formed as a doped polycrystalline silicon layer; a protective layer and a first photoresist layer are sequentially formed on the surface of the semiconductor wafer; a first yellow light process is performed to over the memory array region A pattern of a plurality of interrogation electrodes (gai: e) is defined in the first photoresist layer; using the first photoresist layer The pattern is used as a hard mask to etch the protective layer and the doped polycrystalline silicon layer over the memory array area until the surface of the first dielectric layer is performed; a first ion implantation process is performed to form Lightly doped drain (LDD) of each of the MOS transistors in the memory array region; lightly doped drain (LDD); removing the first photoresist layer; Page 17 471136 VI. Patent application scope Two dielectric layers covering each gate surface on the memory array area; removing the second dielectric layer, the first silicon nitride layer and the first silicon nitride layer on the peripheral circuit area; The protective layer; forming a second photoresist layer on the surface of the semiconductor wafer; performing a second yellow light process to define a plurality of gate patterns in the second photoresist layer above the peripheral circuit area; using The pattern of the second photoresist layer is used as a hard mask, and the undoped polycrystalline silicon layer above the peripheral circuit area is etched up to the surface of the first dielectric layer to form the MOS transistors on the peripheral circuit area. An intermediate electrode; performing a third ion implantation process to form a lightly doped drain (LDD) of each of the M 0 S transistors in the peripheral circuit region; removing the second photoresist layer; forming on the surface of the semiconductor wafer A second silicon nitride layer and covering each gate surface on the peripheral circuit area: an etching process is used to remove a part of the second silicon nitride layer in the peripheral circuit area to the peripheral circuit area Formed around each of the gates Side wall sub (spacer); and performing a fourth ion implantation process to form each of the of the peripheral circuit region of the Μ source 0 S transistor pole (s square u r c e) and without pole (d r a i η). 2. The method according to item 1 of the scope of patent application, wherein the first dielectric layer is composed of silicon dioxide (SiO 2) and is used as a gate oxide layer of each MOS transistor. Page 18 471136 VI. Application for Patent Scope 3. For the method of applying for the scope of patent application item 1, wherein the protective layer is composed of a nitrogen silicon compound, and the protective layer and the undoped polycrystalline silicon layer further include a The first silicon-oxy-nitride (SiOxNy) layer is used as an anti-reflection coating (ARC). 4. The method according to item 1 of the patent application, wherein before the second photoresist layer is formed on the surface of the semiconductor wafer, a second silicon oxynitride (Si 0xNy) layer may be formed on the surface of the semiconductor wafer as an anti-resistance. Reflective layer (ARC). 5. If the method of claim 4 is applied, after the second photoresist layer is removed, the second oxynitride layer formed under the second photoresist layer must also be removed. 6. The method of claim 1, wherein after forming the source and drain of each of the MOS transistors on the peripheral circuit area, the method further includes the following steps: forming a semiconductor wafer surface A metal layer covering the source, drain, and gate surfaces on the far peripheral circuit area; performing a first rapid thermal process (RTP) process; and performing a wet etch etch), removing the unreacted metal layer on the surface of the semiconductor wafer; and performing a second rapid thermal processing (RTP) process. Page 19, 471136 6. Application for Patent Scope 7. The method of claim 6 for patent application, wherein the metal layer is made of cobalt (Co), titanium (Ti), titanium (nickel, Ni) or molybdenum ( molybdenum, Mo). 8. The method according to item 6 of the patent application, wherein the temperature range of the first rapid heat treatment (RTP) process is 40 (TC ~ 60 0 ° C, the heating time is 10 ~ 50 seconds, and the second fast The temperature range of the heat treatment (RTP) process is 600 ° C to 80 (TC, and the heating time is 10 to 50 seconds.) 9. A method for manufacturing a metal oxide semiconductor (M0S) transistor with embedded memory The manufacturing method includes the following steps: A semiconductor wafer is provided. A silicon array surface of the semiconductor wafer has a memory array region and a peripheral circuit region defined thereon, and the memory array region includes at least one cell-well. ), And the peripheral circuit region includes at least one N-well and at least one P-well; a first dielectric layer and an undoped layer are sequentially formed on the surface of the semiconductor wafer; Heteropolycrystalline silicon layer; performing a first ion implantation process on the undoped polycrystalline silicon layer above the memory array region, so that the undoped polycrystalline silicon layer above the memory array region is formed into a pile of heteropolycrystalline silicon layer Sequentially shaped on the surface of the semiconductor wafer A first protective layer and a light-blocking layer; performing a first photolithography process, the memory cell array in a single zone to Inoue Page 20 471136 6. The pattern of the plurality of gates is defined in the first photoresist layer in the patent application range; the pattern of the first photoresist layer is used as a hard mask to etch the upper part of the memory array area. The protective layer and the doped polycrystalline silicon layer up to the surface of the first dielectric layer; removing the first photoresist layer; performing a second ion implantation process to form a light weight of each of the MOS transistors in the memory array region Doped drain (LDD); sequentially forming a first silicon nitride layer and a second dielectric layer on the surface of the semiconductor wafer and covering each gate surface on the memory array region; removing the peripheral circuit region Forming the second dielectric layer, the first silicon nitride layer, and the protective layer; forming a second photoresist layer on the surface of the semiconductor wafer; performing a second yellow light process for the N-type of the peripheral circuit area Wells and the second photoresist layer above the P-type well, define a plurality of gate patterns; use the pattern of the second photoresist layer as a hard mask to etch the undoped layer over the peripheral circuit area Polycrystalline stone layer up to the surface of the first dielectric layer To form a gate electrode of each M 0S transistor on the peripheral circuit region; remove the second photoresist layer; perform a third ion implantation process to form each of the MOS transistors in the peripheral circuit region Lightly doped drain (LDD); forming a second silicon nitride layer on the surface of the semiconductor wafer and covering each gate surface on the peripheral circuit area; I etched the P-well above the peripheral circuit area Decisive Page 21 471136 VI. Patent application scope Second nitrogen silicon layer, forming a first sidewall, and performing a fourth ion implantation process to form a source and a drain of an NMOS transistor in the P-type well; and etching The second silicon nitride layer around each of the gate electrodes above the N-type well in the peripheral circuit area forms a second sidewall, and a fifth ion implantation process is performed to form a PMOS transistor in the N-type well. Source and drain. 10. The method according to item 9 of the scope of patent application, wherein the first dielectric layer is composed of silicon dioxide (Si 02) and is used as a gate oxide layer of each MOS transistor. 1 1. The method according to item 9 of the scope of patent application, wherein the protective layer is composed of a silicon nitrogen compound, and a first alumina oxide is further included between the protective layer and the undoped polycrystalline silicon layer (S i 0 XN y) layer is used as an anti-reflection layer (ARC). 1 2. The method according to item 9 of the patent application, wherein before the second photoresist layer is formed on the surface of the semiconductor wafer, a second silicon oxynitride (Si OxNy) layer may be formed on the surface of the semiconductor wafer as Anti-reflective layer (ARC). 13. The method according to item 12 of the scope of patent application, wherein after the second photoresist layer is removed, the second silicon oxynitride layer formed under the second photoresist layer must also be removed. 1 4. The method according to item 9 of the scope of patent application, wherein the fourth and fifth Page 22 471136 6. Scope of patent application The ion implantation process will dope the undoped polycrystalline silicon layer in the P-well and the gate above the N-well, respectively. 1 5. The method according to item 9 of the patent application, wherein after forming the source and drain of each of the MOS transistors on the peripheral circuit area, the method further includes the following steps: forming on the surface of the semiconductor wafer A metal layer covering the source, drain and gate surfaces on the peripheral circuit region; performing a first rapid thermal processing (RTP) process; performing a wet etch to remove the semiconductor The metal layer not reacted on the wafer surface; and a second rapid thermal processing (RTP) process is performed. 16. The method according to item 15 of the scope of patent application, wherein the metal layer is composed of cobalt (Co), titanium (Ti), nickel (Ni), or molybdenum (Mo). 1 7. The method according to item 15 of the scope of patent application, wherein the temperature range of the first rapid heat treatment (RTP) process is 400 ° T: ~ 600 ° C, and the heating time is 10-50 seconds, and The temperature range of the second rapid heat treatment (RTP) process is from 600 ° C to 80 ° C, and the heating time is from 10 to 50 seconds. Page 23