JPH11121745A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the silicide layer on a gate electrode thick without restriction of the depth of the layer, to suppress the rising of the resistance of the layer and the increase of variation caused by miniaturization and to improve heat resistance. SOLUTION: A silicon nitride film 5 is formed on polycrystalline silicon 4 and patterned as a gate electrode. Then, a side wall 6 of an oxide film is formed, and diffused layer 7 is formed by ion implantation. Then a first titanium layer 8 is deposited, and RTA(rapid thermal annealing) is performed in a nitride atmosphere. A titanium silicide layer is formed only on the diffused layer 7. After unreacted titanium is removed, an interlayer insulating film 10 is formed. Polishing is performed until the surface of the silicon nitride film 5 on the gate electrode is exposed by chemical/mechanical polishing(CMP), and the interlayer insulating film 10 is planarized. At this time, the silicon nitride film 5 becomes a CMP stopper. Then, after the silicon nitride film 5 is removed, a second titanium layer is deposited thicker than that of the first titanium layer. RTA is performed in a nitride atmosphere. A titanium silicide layer 12 thicker than upper part of the diffused layer 7 is formed on the gate electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a MOS transistor in which a silicide layer is formed on a gate electrode and a source / drain diffusion layer in a self-aligned manner. .

[0002]

2. Description of the Related Art Higher speeds have been realized by miniaturizing semiconductor elements, but it has become important to suppress an increase in parasitic resistance that does not follow the scaling law. In order to reduce the resistance of the gate electrode and the diffusion layer, silicidation is an effective means.

A conventional method for manufacturing a MOS type semiconductor device in which a silicide layer is formed on a gate electrode and a diffusion layer in a self-aligning manner will be described with reference to FIGS.

[0004] The first method is as follows. That is, as shown in FIG. 2A, a field oxide film 202 is formed on a silicon substrate 201, a gate oxide film 203 is formed in a region surrounded by the field oxide film, and a gate electrode and a gate electrode are formed on the gate oxide film. A polycrystalline silicon 204 is formed. Next, an oxide film sidewall 205 is formed on the side surface of the gate electrode.
Is formed, and the source and drain diffusion layers 2 are formed by ion implantation.
06 is formed. Next, as shown in FIG. 2B, after removing the native oxide film on the surface of the polycrystalline silicon gate electrode 204 and the surface of the diffusion layer 206 with buffered hydrofluoric acid,
The titanium layer 207 is formed by a sputtering method. Next, FIG.
As shown in (c), rapid heat treatment (RT
A: Rapid Thermal Annealin
g), the titanium layer 207 and the gate electrode 20
4 and the diffusion layer 206 to form a titanium silicide layer 208. Next, the unreacted titanium layer is removed by wet etching, and R
TA is performed to reduce the resistance of titanium silicide. afterwards,
After depositing an interlayer insulating film and providing a contact opening,
And a process of forming an aluminum electrode.

[0005] A second method is a method described in Japanese Patent Application Laid-Open No. Hei 3-9530. This method is as follows. That is, as shown in FIG. 3A, a field oxide film 302 is formed on a silicon substrate 301, a gate oxide film 303 is formed in a region surrounded by the field oxide film, and a gate electrode and a gate electrode are formed on the gate oxide film. A polycrystalline silicon 304 is formed. Next, a sidewall 305 of an oxide film is formed on the side surface of the gate electrode. Next, as shown in FIG. 3B, a native oxide film on the surface of the polycrystalline silicon gate electrode 304 and the surface of the silicon substrate 301 serving as a source and a drain is removed by buffered hydrofluoric acid, and then titanium is removed by sputtering. A layer 306 is formed.

Next, as shown in FIG. 3C, by performing RTA in a nitrogen atmosphere, titanium 306 in contact with silicon is silicided to form titanium silicide 30.
7, and the titanium 306 in contact with the oxide film is nitrided into titanium nitride 308. Further, source and drain diffusion layers 309 are formed by ion implantation. Next, FIG.
As shown in (d), an amorphous silicon 310 is formed by a sputtering method. Next, as shown in FIG. 3E, after patterning the amorphous silicon 310 by a photolithography process and anisotropic etching, a titanium layer 311 is formed by a sputtering method. Next, FIG.
As shown in (f), by performing RTA in a nitrogen atmosphere, titanium 311 in contact with the amorphous silicon 310 is silicided to titanium silicide 312, and the remaining portion is nitrided to titanium nitride. further,
Only titanium nitride is removed by wet etching, and RTA at a higher temperature than the above-mentioned RTA is performed in a nitrogen atmosphere to lower the resistance of titanium silicide. After that, an interlayer insulating film is deposited, a contact opening is provided, and then an aluminum electrode is formed.

[0007]

However, in the first manufacturing method described above, when the thickness of the deposited titanium is increased and the thickness of the formed silicide layer is increased, the heat resistance of the silicide is improved. However, a shallow diffusion layer cannot be formed because the junction leakage current between the diffusion layer and the substrate increases. Conversely, when the thickness of the deposited titanium is reduced and the thickness of the formed silicide layer is reduced, the junction leakage current can be suppressed, so that a shallow diffusion layer can be formed, but the silicide layer on the gate electrode can be formed. The resistance cannot be reduced sufficiently. In addition, heat resistance is lowered. When the thickness of the silicide is reduced, there is a problem that the high-temperature heat treatment after the formation of the silicide causes agglomeration of the silicide and increases the layer resistance. Since the gate electrode is finer than the diffusion layer, the increase in the layer resistance and the deterioration in the heat resistance are remarkable in the silicide layer on the gate electrode. In order to speed up the operation of the device, it is necessary to reduce the parasitic resistance of the gate electrode and the diffusion layer and at the same time to form a shallow diffusion layer. In other words, a thick silicide layer must be formed on the gate electrode and a thin silicide layer must be formed on the diffusion layer. In this method, the gate is formed by one titanium deposition step and one silicidation step. Since a silicide layer is formed simultaneously on the electrode, source and drain diffusion layers, the thickness of the silicide layer on the gate electrode and the thickness of the silicide layer on the diffusion layer cannot be separately controlled. Further, a thin silicide may be formed on the side wall of the oxide film formed on the side surface of the gate electrode, and the gate electrode and the diffusion layer may be short-circuited.

In the second manufacturing method, the thickness of the silicide layer on the gate electrode is increased by the two titanium deposition steps and the two silicidation steps without being limited by the diffusion layer depth. However, an amorphous silicon deposition step, an amorphous silicon patterning step by photolithography, and an amorphous silicon etching step are required, and the number of steps is increased, thereby increasing the manufacturing cost. Further, since titanium nitride is present between the silicide layers, the layer resistance is higher than that of a single-layer silicide, which causes a variation in the layer resistance. If the amorphous silicon is not completely silicided in the second silicidation, the layer resistance will increase. In addition, 1
Thin silicide may also be formed on the side wall of the oxide film formed on the side surface of the gate electrode in the second silicidation step, and the gate electrode and the diffusion layer may be short-circuited. Similarly, even in the second silicidation step, a thin silicide may be formed on titanium nitride on the side wall of the oxide film formed on the side surface of the gate electrode, and the gate electrode and the diffusion layer may be short-circuited. is there.

An object of the present invention is to make the silicide layer on the gate electrode thicker than the silicide layer on the diffusion layer.
It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of suppressing a rise in layer resistance and an increase in variation caused by miniaturization, improving heat resistance, and forming a shallow diffusion layer.

Another object of the present invention is to provide a MOS transistor having a silicide layer, in which a gate electrode and a source / drain diffusion layer can be prevented from being short-circuited by silicide, thereby improving the yield. It is to provide a method.

[0011]

In order to achieve the above object, in a method of manufacturing a semiconductor device according to the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a region separated by an element isolation region on a semiconductor substrate of a first conductivity type; Having a gate electrode provided on a semiconductor substrate of a type via a gate oxide film and a diffusion layer of a second conductivity type, forming a silicide layer on the diffusion layer, and then forming a silicide layer on the diffusion layer And forming a silicide layer on the gate electrode in a separate step.

The silicide layer is formed by a silicidation reaction between silicon and a refractory metal selected from the group consisting of titanium, cobalt, molybdenum, and tungsten.

A step of forming an element isolation region on a semiconductor substrate of the first conductivity type; a step of forming polycrystalline silicon serving as a gate electrode on the semiconductor substrate via a gate oxide film; Forming a silicon nitride film on silicon, patterning the polycrystalline silicon and the silicon nitride film, and forming a sidewall insulating film on a side surface of the patterned laminated film of the polycrystalline silicon and the silicon nitride film Performing a step of exposing a surface of a diffusion layer forming region of a second conductivity type; a step of depositing a first refractory metal on the semiconductor substrate; Reacting with a layer forming region to form a silicide, removing the first refractory metal that did not contribute to the silicidation reaction, and forming a first insulating oxide on the semiconductor substrate. Forming a first insulating oxide film, exposing the surface of the silicon nitride film on the polycrystalline silicon at the same time, and removing the silicon nitride film to expose the polycrystalline silicon surface. A step of depositing a second refractory metal on the semiconductor substrate;
Reacting the second refractory metal with the surface of the polycrystalline silicon by heat treatment to form a silicide; removing the second refractory metal that did not contribute to the silicidation reaction; Forming a second insulating oxide film.

Further, the first and second refractory metals are each selected from the group consisting of titanium, cobalt, molybdenum, and tungsten.

Since the silicide layer on the gate electrode and the silicide layer on the source and drain diffusion layers are formed in different steps, the thickness of the silicide layer can be controlled separately. Therefore,
The silicide layer on the gate electrode is not restricted by the depth of the diffusion layer and can be made sufficiently thick, so that the resistance can be reduced. In addition, since the heat resistance is also improved, the problem that the layer resistance increases due to the aggregation of silicide is eliminated. on the other hand,
Since the silicide layer on the diffusion layer can be thinned according to the depth of the diffusion layer, a shallow diffusion layer can be formed.

Further, a defect that the gate electrode and the source / drain diffusion layers are short-circuited by silicide can be prevented, and the yield can be improved.

[0017]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing an embodiment of the present invention in the order of manufacturing steps. First, as shown in FIG.
A field oxide film 2 in an inactive region of a silicon substrate 1;
A gate oxide film 3 having a thickness of 5 to 10 nm is formed in the active region using a known technique. Next, the gate oxide film 3
After forming polycrystalline silicon 4 on the order of 150 to 200 nm, a silicon nitride film 5 is formed on the order of 50 nm.

Next, as shown in FIG. 1B, the gate electrode 4 is patterned by a photolithography process and anisotropic etching. Next, an oxide film is formed to a thickness of about 100 nm by a CVD method, and thereafter, the oxide film is etched by anisotropic etching to form a sidewall 6 of the oxide film on the side surface of the gate electrode 4. Further, ion implantation and heat treatment are performed to form the diffusion layer 7.

Next, as shown in FIG. 1C, after removing the natural oxide film on the diffusion layer 7 with buffered hydrofluoric acid, a titanium layer 8 is formed to a thickness of about 30 nm by sputtering.

Next, as shown in FIG. 1D, RTA is performed at 650 to 700 ° C. in a nitrogen atmosphere to cause the titanium layer 8 and the diffusion layer 7 to react with each other to form a titanium silicide layer 9 having a thickness of about 50 nm. Form. Next, the unreacted titanium layer is removed with a mixed solution of aqueous ammonia and aqueous hydrogen peroxide.

Next, as shown in FIG. 1E, an interlayer insulating film 10 is formed to a thickness of about 500 nm. Further, chemical mechanical polishing (CMP: Chemical Mechanical)
All polishing is performed until the surface of the silicon nitride film 5 on the gate electrode 4 is exposed, and the interlayer insulating film 10 is planarized. At this time, the silicon nitride film 5 on the gate electrode 4 serves as a CMP stopper.

Next, as shown in FIG. 1F, the silicon nitride film 5 is removed with hot phosphoric acid. Further, after removing the native oxide film on the gate electrode 4 with buffered hydrofluoric acid, a titanium layer 11 is formed to a thickness of about 50 nm by a sputtering method.

Next, as shown in FIG. 1 (g), RTA at 650 to 700 ° C. is performed in a nitrogen atmosphere to
And the gate electrode 4 (polycrystalline silicon) are reacted to form a titanium silicide layer 12 having a thickness of about 80 nm. next,
The unreacted titanium layer is removed with a mixed solution of aqueous ammonia and aqueous hydrogen peroxide. Furthermore, 800 to 8 in a nitrogen atmosphere
RTA at 50 ° C. is performed to reduce the resistance of the titanium silicides 9 and 12.

Thereafter, an interlayer insulating film is deposited, a contact opening is provided, and an aluminum electrode is formed to complete a MOS transistor.

Next, a second embodiment of the present invention will be described. The structure is the same as that of the first embodiment, but in this embodiment, cobalt is used instead of titanium 8 in the first embodiment. In the present embodiment, a field oxide film is formed on a silicon substrate as in the above-described embodiment,
A gate oxide film is formed using a known technique.
Next, polycrystalline silicon is deposited on the gate oxide
After forming about 0 nm, a silicon nitride film is formed about 50 nm.

Next, patterning is performed as a gate electrode by a photolithography process and anisotropic etching.
Next, an oxide film is formed to a thickness of about 100 nm by a CVD method,
Thereafter, the oxide film is etched by anisotropic etching to form sidewalls of the oxide film on the side surfaces of the gate electrode. Further, ion implantation and heat treatment are performed to form a diffusion layer.

Next, after removing the natural oxide film on the diffusion layer with buffered hydrofluoric acid, a cobalt layer of about 10 nm is formed by sputtering.

Next, RTA at 550 to 600 ° C. is performed in a nitrogen atmosphere to cause the cobalt layer and the diffusion layer to react with each other to form a cobalt silicide layer having a thickness of about 30 nm. next,
The unreacted cobalt layer is removed with a mixed solution of sulfuric acid and hydrogen peroxide solution.

Next, an interlayer insulating film of about 500 nm is formed. Furthermore, chemical mechanical polishing (CMP: Chemic)
The interlayer insulating film is polished by Al Mechanical Polishing until the surface of the silicon nitride film on the gate electrode is exposed. At this time, the silicon nitride film on the gate electrode becomes a CMP stopper.

Next, the silicon nitride film is removed with hot phosphoric acid. Further, after removing a natural oxide film on the gate electrode with buffered hydrofluoric acid, a titanium layer is formed to a thickness of about 50 nm by a sputtering method.

Next, RTA is performed at 650 to 700 ° C. in a nitrogen atmosphere to cause a reaction between the titanium layer and the gate electrode (polycrystalline silicon) to form a titanium silicide layer having a thickness of about 80 nm. Next, the unreacted titanium layer is removed with a mixed solution of aqueous ammonia and aqueous hydrogen peroxide. Further, RTA at 800 to 850 ° C. is performed in a nitrogen atmosphere to reduce the resistance of cobalt silicide and titanium silicide.

Thereafter, an interlayer insulating film is deposited, a contact opening is provided, and an aluminum electrode is formed to complete a MOS transistor.

By using cobalt silicide on the diffusion layer, the diffusion layer can be made shallower than titanium silicide, which is advantageous for speeding up the operation of the device.

[0034]

As described above, according to the present invention, since the silicide layer on the gate electrode and the silicide layer on the source and drain diffusion layers are formed in different steps, the thickness of the silicide layer can be controlled separately. The thickness of the formed silicide layer can be controlled by the thickness of the deposited titanium. Further, since the silicide layer on the gate electrode is not limited by the depth of the diffusion layer and can be made sufficiently thick, the resistance can be reduced. In addition, since the heat resistance is also improved, the problem that the layer resistance increases due to the aggregation of silicide is eliminated. On the other hand, since the silicide layer on the diffusion layer can be made thinner according to the depth of the diffusion layer, a shallow diffusion layer can be formed. Accordingly, the parasitic resistance of the gate electrode and the diffusion layer can be reduced, and at the same time, a shallow diffusion layer can be formed, so that the operation of the element can be performed at high speed. CMO with gate line width 0.2μm
In the S process, the layer resistance of titanium silicide is 5Ω.
/ □ or less, the diffusion layer can be formed with a depth of 0.1 μm.

Further, a defect that the gate electrode and the source / drain diffusion layers are short-circuited by silicide can be prevented, and the yield can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention in the order of manufacturing steps.

FIG. 2 is a sectional view showing a conventional manufacturing method in the order of steps.

FIG. 3 is a cross-sectional view showing a conventional manufacturing method in the order of steps.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 field oxide film 3 gate oxide film 4 gate electrode (polycrystalline silicon) 5 silicon nitride film 6 oxide film side wall 7 diffusion layer 8 titanium 9 titanium silicide 10 interlayer insulating film 11 titanium 12 titanium silicide

Claims (4)

[Claims] A first conductive type semiconductor substrate, a region separated by an element isolation region, a gate electrode provided on the first conductive type semiconductor substrate via a gate oxide film, and a second conductive type semiconductor substrate.
Having a conductive type diffusion layer, forming a silicide layer on the diffusion layer, and then forming a silicide layer on the gate electrode in a step different from the formation of the silicide layer on the diffusion layer. Semiconductor device manufacturing method. 2. The method according to claim 1, wherein the silicide layer is formed by a silicidation reaction between silicon and a refractory metal selected from the group consisting of titanium, cobalt, molybdenum, and tungsten.
13. The method for manufacturing a semiconductor device according to item 5. 3. A step of forming an element isolation region on a semiconductor substrate of a first conductivity type, a step of forming polycrystalline silicon serving as a gate electrode on the semiconductor substrate via a gate oxide film, and a step of forming the polycrystalline silicon. Forming a silicon nitride film on silicon, patterning the polycrystalline silicon and the silicon nitride film, and forming a sidewall insulating film on a side surface of the patterned laminated film of the polycrystalline silicon and the silicon nitride film Performing a step of exposing a surface of a diffusion layer forming region of a second conductivity type; a step of depositing a first refractory metal on the semiconductor substrate; Reacting with a layer forming region to form a silicide;
Removing the high melting point metal, forming a first insulating oxide film on the semiconductor substrate, flattening the first insulating oxide film, and simultaneously removing the surface of the silicon nitride film on the polycrystalline silicon. Exposing; removing the silicon nitride film to expose the polycrystalline silicon surface; depositing a second refractory metal on the semiconductor substrate; and heat-treating the second refractory metal. Forming a second insulating oxide film on the semiconductor substrate by reacting the second refractory metal with the polycrystalline silicon surface; A method of manufacturing a semiconductor device. 4. The semiconductor device according to claim 3, wherein the first and second refractory metals are each selected from the group consisting of titanium, cobalt, molybdenum, and tungsten. Method.