JPH09252124A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce parasitic resistance and parasitic capacitance, and to prevent a malfunction at high speed by forming a second side-wall insulating film on the side wall section of an inter-layer insulating film so as to cover the exposed surface of a gate electrode together with the inter-layer film. SOLUTION: The contact holes 15 of a source and a drain are formed in a self-alignment manner to a gate electrode 5, and side wall films 17 in proper film thickness are formed on the side sections of the contact holes 15 so as to be brought into contact with the side wall films 9 of the gate electrode 5. The film thickness of the side wall films 17 formed after the contact holes 15 are bored and the film thickness of the side wall films 9 are designed properly larger than alignment allowance at that time. Accordingly, parasitic resistance and parasitic capacitance can be reduced, and a semiconductor device having high performance at high speed can be acquired. Since a high melting-point metallic silicide layer 12c having low resistance is formed onto the gate electrode 5, gate resistance can be lowered, and operation at higher speed can be conducted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a MOS field effect transistor.

[0002]

2. Description of the Related Art In general, in order to realize a semiconductor device having a high-speed and high-performance MOS field effect transistor (hereinafter referred to as MOSFET), it is necessary to improve the driving ability of a single MOSFET by shortening the channel of the MOSFET. , Thorough reduction of parasitic resistance and capacitance to improve RC delay is important. Regarding the resistance component (R), a salicide structure in which a silicide film, which is a reaction product of metal and silicon, is formed in a self-aligned manner on a gate and a source / drain made of a silicon material has been effectively and positively used. It was When this salicide structure is used for the source / drain diffusion layer, the resistance of the diffusion layer can be reduced by one digit or more.

The formation of the above salicide structure will be described with reference to FIG. First, an element isolation region 42 is formed on a silicon substrate 41 by the LOCOS method, and then an oxide film and a polysilicon film are sequentially deposited on the element region and patterned to form a gate electrode 44 and a gate oxide film 43 (FIG. 5 (a)). Then, ion implantation is performed using the gate electrode as a mask to form a shallow diffusion layer 45 with a low concentration.

Next, an insulating film is deposited on the entire surface of the substrate, and a sidewall film 46 is formed on the side of the gate electrode 44 by anisotropic etching (see FIG. 5B). Then, by ion-implanting impurities with the sidewall film 46 as a mask, a high-concentration deep diffusion layer 47 is formed to form a source / drain region (see FIG. 5B).

Next, a refractory metal layer 48 is deposited on the entire surface of the substrate (see FIG. 5C) and heat-treated to form the refractory metal layer 48 and the silicon and source.
The silicide layers 49a and 49b are formed by reacting with the silicon in the drain region 47 (see FIG. 5D).

After that, the unreacted refractory metal is removed, an interlayer insulating film 50 is deposited on the entire surface of the substrate, and then a connecting hole to the source / drain region is opened in the interlayer insulating film 50 by using a lithography technique. Then, the opening is filled with a metal film and patterned to form a wiring 52.
Complete the OSFET.

On the other hand, in order to reduce the capacitance component (C), it is effective to reduce the junction area of the drain and source diffusion layers 47. However, even when the junction area is reduced, it is necessary to secure a contact region in the diffusion layer for making contact with the wiring layer and a region for the alignment margin required for lithography. For this reason, it is difficult to reduce the area of the diffusion layer beyond the lithographic technology available in each generation.

As a means for reducing the above contact margin, a self-alignment technique called SAC (Self-Alignment Contact) shown in FIG. 6 is known. For example, K.Ishimaru
et al, "Bipolar Installed CMOS Tehnology without
any Process step Increase for High speed Cache SRA
M ", IEEE IEDM, 1995, p673-675. This is because the gate electrode 65 is formed on the surface of the gate electrode 65 when forming the contact opening 75 with the diffusion layer 70 formed on the substrate 61.
Cap nitride film 71 deposited and formed before patterning
And the gate sidewall film 69 made of a nitride film, the interlayer oxide film 74 under the first layer wiring is selectively etched to substantially open the contact hole 75 in a self-aligned manner with the gate electrode 65. To do. As a result, it is not necessary to particularly set the margin x between the contact 80 and the gate electrode 65 as shown in FIG. 7, and it is intended to reduce the chip area and the diffusion layer capacitance. In FIG. 6, a metal silicide layer 85a is formed between the gate electrode 65 and the cap nitride film 71. The metal silicide layer 85a is formed on the polysilicon film which will be the gate electrode and is patterned into the shape of the gate electrode.

Although a mask designed so that the edge 81 of the contact hole 75 coincides with the edge 66 of the gate electrode 65 is used in FIG. 6, the contact hole 75 is moved to the left side on the paper surface due to misalignment of the mask. The figure shows the case where there is a shift.

[0010]

When a wide contact hole like SAC is opened in the salicide structure described above to reduce the resistance component and the capacitance component, the contact hole 75 is shifted and opened as shown in FIG. In that case, there is a problem that the gate electrode 65 and the electrode for leading out the source / drain 70 are short-circuited.

Further, as shown in FIG. 6, the gate electrode is composed of a metal silicide film 85a, and the cap film 7 is formed on the surface thereof.
According to the method of forming No. 1 and patterning the gate electrode, there is a problem that the gate resistance increases due to the abnormal oxidation of the metal silicide film 85a due to the necessity of post-oxidation of the gate insulating film 63. In patterning the gate electrode, the metal silicide film 85a and the polysilicon film 65 are also used.
Etching a two-layer structure of 1) and 2) has problems such as the effect on the substrate due to overetching and the complexity of selection and introduction of gas species corresponding to two types of gate materials.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a semiconductor device having a MOSFET that operates at high speed and does not malfunction, and a simple manufacturing method for forming such a semiconductor device. And

[0013]

[Means for Solving the Problems]

[Overview] A first aspect of a semiconductor device according to the present invention is to provide a semiconductor substrate having a gate insulating film formed on the surface thereof, a gate electrode formed on the surface of the gate insulating film, and sandwich the gate electrode from both sides. An impurity region formed in a surface region of the semiconductor substrate, a first sidewall insulating film formed on a sidewall portion of the gate electrode, and an interlayer insulating film formed on a surface of the gate electrode and provided with a sidewall portion. A second sidewall insulating film formed on a sidewall of the interlayer insulating film;
A wiring formed in the opening surrounded by the side wall insulating film and connected to the impurity region.

A second aspect of the semiconductor device according to the present invention is
In the semiconductor device according to the first aspect, the second sidewall insulating film covers the gate electrode together with the first sidewall insulating film.

According to a third aspect of the semiconductor device of the present invention,
In the semiconductor device of the first or second aspect, the first sidewall insulating film and the interlayer insulating film are made of different insulating materials.

A fourth aspect of the semiconductor device according to the present invention is the semiconductor device according to any one of the first to third aspects, characterized in that a metal silicide layer is formed in a surface region of the gate electrode. And

A first aspect of the method for manufacturing a semiconductor device according to the present invention is the step of forming an element isolation film for isolating elements in the surface region of the semiconductor substrate, and the element isolation on the surface of the semiconductor substrate. Forming a gate insulating film in a region surrounded by the film; forming a gate electrode on the surface of the gate insulating film; and an impurity region in a surface region of the semiconductor substrate so as to sandwich the gate electrode from both sides. A step of forming a first side wall insulating film on the side wall of the gate electrode, a step of forming an interlayer insulating film having a side wall on the gate electrode, and a side wall of the interlayer insulating film. And a step of forming a wiring connected to the impurity region in an opening surrounded by the second sidewall insulating film. To do.

A second aspect of the method of manufacturing a semiconductor device according to the present invention is characterized in that the gate electrode is covered by forming the interlayer insulating film and the second sidewall insulating film in the manufacturing method of the first aspect. And

A third aspect of the method for manufacturing a semiconductor device according to the present invention is the method of manufacturing according to the first or second aspect, wherein the first sidewall insulating film and the second sidewall insulating film are made of different insulating materials. It is characterized by forming.

A fourth aspect of the method of manufacturing a semiconductor device according to the present invention is characterized in that a metal silicide layer is formed on the surface of the gate electrode in the method of manufacturing according to any one of the first to third aspects. .

In the above structure, the structure in which the polycrystalline silicon film is formed on the surface of the gate electrode is also included in the scope of the present invention.

An insulating film such as a cap nitride film is formed on the gate electrode as in the conventional SAC, and the nitride film is covered with the second sidewall insulating film and the interlayer insulating film of the present invention. Therefore, it is possible to prevent conduction between the contact hole and the gate electrode due to the film reduction accompanying the etching of the cap nitride film.

Therefore, the present invention also includes a manufacturing method of performing a step of forming a conductive film to be a gate electrode or an insulating film such as a nitride film on the gate electrode before forming the interlayer insulating film.

The step of forming the metal silicide film on the surface of the gate electrode is preferably performed after the post-oxidation step of the gate insulating film performed after the gate electrode is formed, from the viewpoint of preventing the resistance of the gate electrode from increasing.

Further, in the above structure, it is preferable to form the metal silicide film on the surface region of the impurity and the surface of the gate electrode in the same step for simplification of the manufacturing process.

The formation of the impurity region may include a step of forming the first impurity region with the gate electrode as a mask and a step of forming the second impurity region with the first sidewall insulating film and the gate electrode as the mask. preferable.

[Operation] According to the semiconductor device and the method for manufacturing a semiconductor device having the above-described structure, the second sidewall is formed on the sidewall of the interlayer insulating film so as to cover the exposed surface of the gate electrode together with the interlayer insulating film. Since the insulating film is formed, the gate electrode is insulated from the wiring serving as the source / drain lead-out electrode even if the mask pattern for the contact opening is misaligned. This makes it possible to reduce the parasitic resistance and the parasitic capacitance, resulting in a high-speed operation with no malfunction.

Further, since the metal silicide layer is formed in the surface region of the gate electrode, the gate resistance can be lowered and a higher speed operation can be performed.

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In the present specification, self-alignment means the alignment margin between a contact with an impurity layer and a gate electrode during mask design. Means that it is not necessary to think with a margin as in the past.

FIG. 1 shows the configuration of an embodiment of a semiconductor device according to the present invention. In the semiconductor device of this embodiment, for example, a gate oxide film 3 and a gate electrode 5 are formed on an element region separated by an element isolation region 2 of a P-type semiconductor substrate 1. A first sidewall insulating film 9 made of an insulating film is formed on the side surface of the gate electrode 5. Further, low concentration N-type diffusion layers 7a and 7b formed in a self-aligned manner with respect to the gate electrode 5 are provided on the element region, and the gate electrode 5 and the first side wall insulating film 9 are provided. Concentration N-type diffusion layer 10 formed in self-alignment
a and 10b are provided.

The metal silicide layers 12a, 12b and 1 are formed on the surfaces of the diffusion layers 7a and 7b and the surface of the gate electrode 5, respectively.
2c is formed. Also, this metal silicide layer 12
An interlayer insulating film 14 is formed in contact with a, 12b, 12c, and a contact hole 15 for making contact with the diffusion layer is formed in the interlayer insulating film 14 in a self-aligned manner with the gate electrode 5. Has been formed. A side wall film 17 made of an insulating film is formed on the side surface of the contact hole 15. Although not shown in FIG. 1, metal wiring is formed in the contact hole 15. The sheet resistance of the gate electrode including the metal silicide layer 12c is 3Ω /
Mouth level and low. Therefore, the speed can be increased.

Next, a method of manufacturing the semiconductor device of this embodiment will be described with reference to FIGS. Further, since the contact hole is formed in a self-aligned manner without substantially considering the alignment margin, the capacity of the diffusion layer is formed sufficiently low.

First, as shown in FIG. 2A, for example, an element isolation region 2 is formed on a P-type semiconductor substrate 1 by the LOCOS method.
Then, a gate oxide film 3 is formed on the element region by heat treatment, and then a polycrystalline silicon film 5 is deposited.
After that, the gate electrode 5 is formed by patterning the polycrystalline silicon film 5 and the gate oxide film 3 by using the lithography technique and the RIE method. After that, in order to round the corners of the gate electrode and alleviate the electric field effect, oxidation of about 100 angstrom called post-oxidation may be performed. After the gate electrode 5 is formed, the gate electrode 5 is used as a mask to accelerate the P ions with an acceleration voltage of 40 KeV and a dose amount of 7.
Ions are implanted under the condition of 0 × 10 ¹³ cm ⁻² to form low-concentration N-type diffusion layers 7a and 7b (see FIG. 2A).

Next, as shown in FIG. 2B, a silicon nitride film having a thickness of 150 nm is LPCVD (Lo
w Pressure Chemical Vapor Deposition) method or the like, and then etch back using anisotropic etching such as RIE method to selectively leave the silicon nitride film on the side portion of the gate electrode 5 to form the sidewall film 9. Form. Then, using the sidewall film 9 and the gate electrode 5 as a mask, As ions are accelerated at a voltage of 50 KeV and a dose amount of 3.0 × 10 ¹⁵ c.
Implantation is performed under the condition of m ⁻² to form high-concentration N-type diffusion layers 10a and 10b to be source / drain layers (see FIG. 2B).

After that, annealing at 1000 ° C. for 20 seconds is performed to activate the ion-implanted impurities P and As. Next, an acid-based solution (for example, H diluted to 1/100)
After removing the oxide film on the diffusion layers 10a and 10b using a F solution), a film of refractory metal (for example, Ti) is deposited on the entire surface to a thickness of 300 Å. Then, by annealing at a temperature of 600 ° C. to 750 ° C. in a nitrogen atmosphere, the silicide film T is formed on the regions where silicon contacts Ti, that is, on the diffusion layers 10 a and 10 b and the gate electrode 5.
iSi ₂ layers 12a, 12b, 12c are formed. Subsequently, the unreacted Ti film on the sidewall film 9 and the element isolation region 2 is selectively removed by using, for example, a mixed solution of H ₂ O ₂ and H ₂ SO ₄ , and then at 800 ° C. in an N ₂ atmosphere. By annealing at a temperature of 900 ° C., the TiSi ₂ layers 12a, 12
Lower the sheet resistance of b and 12c. This is because the crystal structure of the TiSi ₂ layer is changed from C49 to C54 by the above annealing. By doing so, the diffusion layer 12a,
TiSi ₂ films 12a, 12b, 12c having a thickness of about 600 Å are formed on the gate electrode 12b and the gate electrode 5 (see FIG. 2C).

Next, as shown in FIG. 3A, the first layer Al
As the interlayer film 14 under the wiring, for example, LP-TEOS
(Low Pressure Tetra-Etoxy-Ortho Silicate) film and LP-BPSG (Low Pressure Borophosphosilicate)
Glass) film, 1000 angstrom, 12,
000 angstrom deposited and CMP (Chemical Mec
The interlayer film 14 is flattened by using a hanical polish technique. By performing such height control, the step difference of the conventional cap film can be reduced. After that, the source / drain layers 10a, 10 of the MOSFET are formed by using the photolithography technique.
The contact hole 15 with b is opened in self-alignment with the gate electrode 5. At this time, the interlayer film 14 that has been planarized and left on the gate silicide film is a sidewall film 17 to be formed later.
It is preferable that the thickness is such that the silicide film 12c is not exposed during the etching for formation, and that an extra step is not formed under the AI wiring to be formed later.

FIG. 4B is a plan view of the semiconductor device of this embodiment, and FIG. 4A is a sectional view taken along the line A--A shown in FIG. 4B. is there. In FIG. 4, in order to facilitate understanding, a case where the position of the contact 20a is largely shifted to the gate electrode 5 side by L is shown.

When the contact hole 15 is opened,
Using the Monegtron RIE apparatus, the interlayer film 14 is etched in a mixed gas system of CHF ₃ and CO, for example, under the condition that the nitride film 9 has a sufficient selection ratio. This selection ratio is preferably 25 or more, and Ar or the like can be added if necessary. Also, the contact hole 1
It has been confirmed that the silicide film 12c formed on the gate electrode serves as a sufficient etching stopper when the contact hole 15 is opened even when the alignment of 5 is deviated.
Further, the sidewall insulating film and the interlayer insulating film are made of a nitride film and TEOS.
The combination is not limited to the combination of the film and the BPSG film, and may be any combination as long as the selection ratio is obtained. Even in this case, the selection ratio is 2
It is preferably 5 or more.

Next, an insulating film made of, for example, a nitride film is formed on the substrate 1.
1500 angstrom is deposited on the entire surface of the substrate and is etched back using the RIE method, so that the sidewall film 17 having a width of 1500 angstrom is formed in the contact hole 15 in a self-aligned manner (see FIG. 3B). Since the alignment accuracy of the current lithographic technique has reached ± 0.1 μm or less, the sidewall film 17 formed by the self-alignment described above has already been formed.
Will be connected.

As described above, the thickness of the insulating film 17 formed after the opening of the contact hole 15 and the thickness of the side wall film 9 are properly set.
For example, by designing the film thickness of the insulating film 17 to be larger than the alignment margin when the insulating film 17 is formed, the side wall film 17 and the side wall film 9 form the gate electrode 5 and the source / drain extraction electrodes 20a and 20b (see FIG. (See (a)) is insulated. Thereafter, if necessary, multilayer wirings such as the source / drain lead-out electrodes 20a and 20b are formed, and then a passivation film is formed to complete the semiconductor device.

As described above, according to the semiconductor device of the present embodiment, the source / drain contact hole 15 is formed in a self-aligned manner with respect to the gate electrode 5, and the side portion of the contact hole 15 is suitable. Since the side wall film 17 having a different thickness is formed so as to be in contact with the side wall film 9 of the gate electrode 5, the gate electrode 5 and the source / drain extraction electrodes are insulated. As a result, the parasitic resistance and the parasitic capacitance can be reduced, and a high-speed and high-performance semiconductor device can be obtained. In addition, since the low-melting-point refractory metal silicide layer 12c is formed on the gate electrode 5, the gate resistance can be lowered, and a higher speed operation can be performed.

Although the transistor of the semiconductor device of the above embodiment is an N-channel MOSFET,
It goes without saying that the present invention can also be used in the case of a channel MOSFET or CMOS structure.

Although Ti is used as the silicide material in the above embodiment, a silicide material such as Co or V can be used by appropriately selecting the film forming temperature.

In the above embodiment, TiSi
₂ was formed by depositing a Ti film and then silicidized.
After forming the Ti film, TiN may be deposited and then silicidized. In this case, the T
The iN film is also peeled off at the same time as the Ti film.

Further, in the semiconductor device of the above embodiment, the refractory metal silicide layers 12a, 12b, 12c are formed on the gate electrode 5 and the diffusion layers 10a, 10b, but these silicide layers 12a, 12b, 12c. Since the parasitic capacitance can be reduced without providing the above, a high-speed and high-performance semiconductor device can be obtained. When the refractory metal silicide layer is provided on only one of the gate electrode 5 or the diffusion layers 7a and 7b, the parasitic resistance can be reduced as compared with the case where the refractory metal silicide layer is not provided at all.

Further, in the above embodiment, a tungsten silicide layer may be formed instead of the refractory metal silicide film 12c provided on the gate electrode 5. In this case, it is possible to obtain the same effect as that of the above-described embodiment, and it is possible to prevent the thin line effect, so that higher integration can be achieved.

When the tungsten silicide layer is provided on the gate electrode 5, the parasitic capacitance can be reduced as compared with the conventional case without providing the refractory metal silicide layers 12a and 12b on the diffusion layers 10a and 10b. Therefore, a high-speed and high-performance semiconductor device can be obtained. Further, it is possible to prevent the thin line effect, and it is possible to achieve high integration.

Further, in the above-described embodiment, the sidewall film 17 provided in the contact hole is formed of the silicon nitride film, but it may be formed of another insulating film such as SiO ₂ .

In the present invention, the gate electrode structure is NMOS.
The present invention can be applied to a semiconductor device having a CMOS with a dual gate structure in which N ⁺ polysilicon is used for the PMOS and P ⁺ polysilicon is used for the PMOS.

Further, in the semiconductor device of the present embodiment, after opening the contact hole 15, as shown in FIG. 4, the tungsten 20a, 20b is selectively formed on the salicide layers 12a, 12b at the bottom of the contact hole 15 as a base. Wiring may be provided after the contact hole 15 is filled.

[0051]

As described above, according to the present invention, a high speed and high performance semiconductor device can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional view showing the configuration of an embodiment of a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of a semiconductor device according to the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing process of a semiconductor device according to the present invention.

FIG. 4 is an explanatory diagram illustrating a positional relationship between contacts and gate electrodes of a semiconductor device according to the present invention.

FIG. 5 is a process drawing of a MOSFET having a salicide structure.

FIG. 6 is a configuration diagram showing a configuration of a conventional semiconductor device.

FIG. 7 is an explanatory diagram illustrating a contact margin.

[Explanation of symbols]

 1 semiconductor substrate 2 element isolation region 3 gate insulating film 5 gate electrode 6 gate electrode edge 7a, 7b low concentration N type diffusion layer 9 side wall films 10a, 10b high concentration N type diffusion layer 12a, 12b, 12c refractory metal Silicide layer 14 Interlayer film 15 Contact hole 17 Side wall film 20a, 20b Contact 41 Silicon substrate 42 Element isolation region 43 Gate insulating film 44 Polysilicon film 45 Low concentration diffusion layer 46 Side wall film 47 High concentration diffusion layer 48 Ti-based high Melting point metal film 49a Silicide layer 49b Silicide film 50 Interlayer insulation film 52 Wiring 61 Semiconductor substrate 62 Element isolation region 63 Gate insulation film 65 Gate electrode 66 Gate electrode edge 69 Sidewall film 70 Diffusion layer 71 Cap layer 74 Interlayer insulation film 75 Contact hole 80 contacts 85a, 85b Silisa Id layer

Claims (8)

[Claims] 1. A semiconductor substrate having a gate insulating film formed on the surface thereof, a gate electrode formed on the surface of the gate insulating film, and a gate electrode formed on the surface region of the semiconductor substrate so as to sandwich the gate electrode from both sides. An impurity region, a first sidewall insulating film formed on the sidewall of the gate electrode, an interlayer insulating film formed on the surface of the gate electrode and having a sidewall, and a sidewall of the interlayer insulating film. A semiconductor device comprising: a formed second sidewall insulating film; and a wiring formed in an opening surrounded by the second sidewall insulating film and connected to the impurity region. 2. The semiconductor device according to claim 1, wherein the second sidewall insulating film covers the gate electrode together with the first sidewall insulating film. 3. The semiconductor device according to claim 1, wherein the first sidewall insulating film and the interlayer insulating film are made of different insulating materials. 4. The semiconductor device according to claim 1, wherein a metal silicide layer is formed on the surface region of the gate electrode. 5. A step of forming an element isolation region for isolating elements in a surface region of a semiconductor substrate, and forming a gate insulating film in a region surrounded by the element isolation region on the surface of the semiconductor substrate. A step of forming a gate electrode on the surface of the gate insulating film, a step of forming an impurity region in a surface region of the semiconductor substrate so as to sandwich the gate electrode from both sides, A step of forming a sidewall insulating film of No. 1, a step of forming an interlayer insulating film having a sidewall on the gate electrode, a step of forming a second sidewall insulating film on a sidewall of the interlayer insulating film, And a step of forming a wiring connected to the impurity region in an opening surrounded by the second sidewall insulating film, the method for manufacturing a semiconductor device. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the gate electrode is covered by forming the interlayer insulating film and the second sidewall insulating film. 7. The method of manufacturing a semiconductor device according to claim 5, wherein the first sidewall insulating film and the second sidewall insulating film are formed of different insulating materials. 8. The method of manufacturing a semiconductor device according to claim 5, wherein a metal silicide layer is formed on the surface of the gate electrode.