KR100400288B1 - Method for manufacturing transistor of semiconductor device - Google Patents
Method for manufacturing transistor of semiconductor device Download PDFInfo
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- KR100400288B1 KR100400288B1 KR1019960079877A KR19960079877A KR100400288B1 KR 100400288 B1 KR100400288 B1 KR 100400288B1 KR 1019960079877 A KR1019960079877 A KR 1019960079877A KR 19960079877 A KR19960079877 A KR 19960079877A KR 100400288 B1 KR100400288 B1 KR 100400288B1
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- South Korea
- Prior art keywords
- thin film
- semiconductor device
- cobalt
- layer
- silicide
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 229910017052 cobalt Inorganic materials 0.000 claims abstract description 31
- 239000010941 cobalt Substances 0.000 claims abstract description 31
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 28
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 27
- 239000010409 thin film Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000002955 isolation Methods 0.000 claims abstract description 5
- 239000010408 film Substances 0.000 claims description 16
- 238000010438 heat treatment Methods 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 238000004544 sputter deposition Methods 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 24
- 239000010703 silicon Substances 0.000 abstract description 23
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 238000004151 rapid thermal annealing Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 22
- 239000010410 layer Substances 0.000 description 22
- 238000006243 chemical reaction Methods 0.000 description 10
- 150000001875 compounds Chemical class 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910000531 Co alloy Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
Abstract
Description
본 발명은 반도체 소자의 트랜지스터 제조 방법에 관한 것으로, 특히 산소환원력이 뛰어난 VA 족 원소인 Ta 와 V 를 중간층으로 형성한 Co/Ta(V) 이중층을 이용하여 코발트 실리사이드를 형성하는 기술로서, 이를 반도체소자이 게이트, 소오스, 드레인 전극을 동시에 형성하는 샐리사이드 ( salicide : self-aligned silicide ) 공정에 적용하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor of a semiconductor device, and more particularly, to a cobalt silicide formed using a Co / Ta (V) bilayer in which Ta and V, which are group VA elements having excellent oxygen reduction power, are formed as an intermediate layer. A device is applied to a salicide (self-aligned silicide) process in which a device simultaneously forms a gate, a source, and a drain electrode.
최근, 반도체소자의 디자인 룰 ( design rule ) 이 작아지고 동작속도가 빠라짐에 따라 MOS 회로의 성능개선에 대한 필요성이 커지고 있다. 이에 따라 MOS 전극부의 얕은 접합의 형성과 기생저항의 감소방법이 주된 관심사로 떠오르고 있으며 이러한 문제를 극복하는 해결책의 하나가 MOS 의 게이트와 소오스, 드레인 전극을 동시에 실리사이드화하는 샐리사이드공정이다.In recent years, as the design rules of semiconductor devices become smaller and the operating speeds become faster, the necessity for improving the performance of MOS circuits is increasing. Accordingly, the formation of shallow junctions and reduction of parasitic resistance have emerged as major concerns. One of the solutions for overcoming these problems is the salicide process that silicides the gate, source, and drain electrodes of the MOS simultaneously.
현재 사용되고 있는 코발트 실리사이드공정은 코발트 단일층을 이용하고 있으며, 그 방법은 다음과 같다.Currently used cobalt silicide process using a cobalt monolayer, the method is as follows.
먼저, 단일 코발트층을 형성하고 열처리하여 실리콘과의 계면, 즉 게이트, 소오스, 드레인 전극 부분에서 실리콘과의 접촉부분에서 실리사이드 반응이 일어나게 하는 방법이다.First, a single cobalt layer is formed and heat treated to cause a silicide reaction to occur at an interface with silicon, that is, at a gate, source, and drain electrode part, with a contact part with silicon.
그러나, 단일 코발트층을 사용할 경우는, 실리콘층 상부에 형성되어 있는 산화막을 코발트가 환원시킬 수 없기 때문에 부분적으로 남아있는 산화막 사이로 실리사이드가 형성되어 전체적으로 균일하게 형성되지않고 부분적으로 형성되어 실리사이드와 실리콘 계면, 즉 실리사이드와 반도체기판의 계면이 거칠어 지는 문제점이 있다.However, in the case of using a single cobalt layer, since the cobalt cannot reduce the oxide film formed on the silicon layer, silicide is formed between the partially remaining oxide films and is not formed uniformly as a whole. That is, there is a problem that the interface between the silicide and the semiconductor substrate is rough.
또한, 실리사이드의 형성시 실리콘의 소모가 크기 때문에 얕은 접합을 형성한 경우는 접합이 파괴되는 문제가 있으며 열적으로 불안정하여 MOS 전극부의 얕은 접합형성에 어려움이 있다.In addition, when the silicide is formed, a large amount of silicon is consumed, and thus, when the shallow junction is formed, the junction is broken and thermally unstable, thus making it difficult to form the shallow junction of the MOS electrode.
따라서, 본 발명은 종래 기술의 위와 같은 문제점을 해결하기 위하여, 산소환원력이 뛰어난 VA 족 원소인 Ta, V 등을 이용하여 코발트 실리사이드를 형성함으로써 후속공정으로 반도체기판 상부의 산화막을 완전히 제거할 수 있어 실리콘의 과다한 소모를 억제하여 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 트랜지스터 제조방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the above problems of the prior art, by forming a cobalt silicide using Ta, V, etc., which is a group VA element having excellent oxygen reduction power, the oxide film on the upper portion of the semiconductor substrate can be completely removed in a subsequent process. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a transistor of a semiconductor device which suppresses excessive consumption of silicon to improve the characteristics and reliability of the semiconductor device and thereby enable high integration of the semiconductor device.
도 1a 및 도 1b 는 본 발명의 실시예에 따른 반도체소자의 트랜지스터 제조방법에 관한 것을 도시한 단면도.1A and 1B are sectional views showing a transistor manufacturing method of a semiconductor device according to an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11 : 반도체 기판 13 : 소자분리산화막11 semiconductor substrate 13 device isolation oxide film
15 : 게이트산화막 17 : 게이트전극용 다결정실리콘막15 gate oxide film 17 polycrystalline silicon film for gate electrode
19 : 소오스/드레인 접합영역 21 : Ta(V)19: source / drain junction region 21: Ta (V)
23 : 코발트 박막23: cobalt thin film
이상의 목적을 달성하기 위한 본 발명인 반도체 소자의 트랜지스터 제조방법은,A transistor manufacturing method of a semiconductor device of the present invention for achieving the above object,
소자분리절연막이 형성된 반도체기판 상부에 게이트전극용 도전층을 형성하는 공정과,Forming a conductive layer for the gate electrode on the semiconductor substrate on which the device isolation insulating film is formed;
상기 반도체기판 상부에 산화성향이 큰 VA 족 박막을 형성하는 공정과,Forming a VA group thin film having a high oxidation tendency on the semiconductor substrate;
상기 VA 족 박막 상부에 코발트 박막을 형성하는 공정과,Forming a cobalt thin film on the VA thin film,
상기 VA 족 박막/코발트 박막의 적층구조를 급속열처리하여 코발트 실리사이드를 형성하는 공정을 포함하는 것을 특징으로한다.And rapidly forming a stack structure of the group VA thin film / cobalt thin film to form cobalt silicide.
한편, 이상의 목적을 달성하기 위한 본 발명의 원리는, Co/Ta(V) 이중층을 이용하여 코발트 실리사이드를 형성하는 것으로, 중간층으로 사용하는 VA 족 원소인 Ta, V 는 산화성향이 커서 코발트와 실리콘의 균일한 반응을 방해하는 실리콘표면의 산화막을 충분히 제거시켜줄 뿐만아니라 열처리 중 코발트와 결합하여 화합물을 형성하여 기판의 실리콘 과잉소모를 막아주게 된다. 결과적으로, 전 계면에 걸쳐 균일한 반응이 일어나 평탄한 계면을 얻을 수 있으며 중간에 형성된 화합물 및Ta2O5(V2O5)층이 실리사이드 반응을 제어하여 실리콘의 과다한 소모를 방지함으로써 MOS 전극부에 얕은 접합을 유지할 수 있게 되는 것이다.On the other hand, the principle of the present invention for achieving the above object is to form a cobalt silicide using a Co / Ta (V) bilayer, Ta, V, which is a group VA element used as an intermediate layer has a high oxidation tendency and cobalt and silicon Not only does it sufficiently remove the oxide film on the silicon surface that hinders the uniform reaction, but also combines with cobalt during heat treatment to form a compound to prevent excess silicon consumption of the substrate. As a result, a uniform reaction occurs over the entire interface to obtain a flat interface, and the compound formed in the middle and the Ta 2 O 5 (V 2 O 5 ) layer control the silicide reaction to prevent excessive consumption of silicon, thereby preventing the MOS electrode portion. To maintain a shallow junction.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 및 도 1b 는 본 발명의 실시예에 따른 반도체소자의 트랜지스터 제조방법을 도시한 단면도로서, 상기 도 1b 는 실리사이드를 형성하기 위한 급속열처리 공정시 박막의 구조변화를 도시한다.1A and 1B are cross-sectional views illustrating a method of manufacturing a transistor of a semiconductor device according to an embodiment of the present invention, and FIG. 1B illustrates a structural change of a thin film during a rapid heat treatment process for forming silicide.
먼저, 반도체기판(11) 상부에 소자분리산화막(13)을 형성한다. 그리고, 상기 반도체기판(11)의 활성영역에 패터닝된 게이트산화막(15)과 게이트용 다결정실리콘막(17)을 형성한다.First, an isolation oxide layer 13 is formed on the semiconductor substrate 11. A gate oxide film 15 and a gate polysilicon film 17 are formed in the active region of the semiconductor substrate 11.
그리고, 상기 반도체기판(11)에 불순물을 주입하여 소오스/드레인 접합영역(19)을 형성한다.An impurity is implanted into the semiconductor substrate 11 to form a source / drain junction region 19.
그 다음에, 전체표면상부에 VA 족 원소인 Ta 또는 V 로 이루어진 Ta 또는 V 박막(21)을 형성하고, 상기 Ta 또는 V 박막(21) 상부에 코발트 박막(23)을 형성함으로써 Co/Ta(V)(23,21)의 이중층을 형성한다.Next, a Ta or V thin film 21 made of Ta or V, which is a Group VA element, is formed on the entire surface, and a cobalt thin film 23 is formed on the Ta or V thin film 21 to form Co / Ta ( V) (23, 21) to form a double layer.
여기서, 상기 Ta(V) 박막(21)은 100 ∼ 500 Å 정도의 두께로 형성하고, 상기 코발트 박막(23)은 100 ∼ 300 Å 정도의 두께로 형성하되, 상기 Ta(V) 박막(21)과 코발트 박막(23)은 스퍼터링 또는 화학기상증착방법으로 형성한다. (도 1a)Here, the Ta (V) thin film 21 is formed to a thickness of about 100 to 500 kPa, and the cobalt thin film 23 is formed to a thickness of about 100 to 300 kPa, but the Ta (V) thin film 21 The cobalt thin film 23 is formed by sputtering or chemical vapor deposition. (FIG. 1A)
그 다음에, 550 ∼ 850 ℃ 정도의 온도에서 급속열처리하여 코발트 실리사이드(도시안됨)를 형성한다.Next, rapid heat treatment at a temperature of about 550 to 850 ° C. forms cobalt silicide (not shown).
이때, 상기 Co/Ta(V)(23,21)의 이중층은 다음과 같이 변화한다. 열처리 초기에는 상기 Co/Ta(V)(23,21)의 계면으로 부터 Co-Ta(V) 화합물이 형성되며, Ta(V)/Si 계면에서는 Ta(V)-산화막이 형성됨과 동시에 약간의 실리콘이 Ta(V)층으로 확산하여 Co-Ta(V)-Si 의 삼원계, 화합물도 형성된다. 그리고, 중간층으로 사용한 Ta(V)는 Si 에 비하여 산화성향이 커서 Co 와 Si 의 균일한 반응을 방해하는 실리콘 표면의 산화막을 환원시키고 Si 과의 계면에 균일한 Ta2O5(V2O5)층을 형성한다. 또한, 실리사이드 열처리가 계속 진행되는 동안 코발트가 확산하여 Ta(V)층과 Ta2O5(V2O5)층을 통과하여 Ta2O5(V2O5)층과 실리콘 계면에서 실리사이드 반응이 일어나게 된다. 열처리중 형성된 Co-Ta(V)합금이나 Ta2O5(V2O5)층은 실리사이드 반응을 중간에서 제어하는 역할을 하여 실리콘의 과다한 소모를 방지함으로써 평탄한 계면을 가지는 얇은 코발트 실리사이드층을 얻을 수 있다.At this time, the double layer of the Co / Ta (V) (23, 21) is changed as follows. At the initial stage of the heat treatment, a Co-Ta (V) compound is formed from the interface of Co / Ta (V) (23,21), and at the same time, a Ta (V) -oxide film is formed at the Ta (V) / Si interface. Silicon diffuses into the Ta (V) layer to form a ternary, compound of Co-Ta (V) -Si. In addition, Ta (V) used as an intermediate layer has a higher oxidation tendency than Si, thereby reducing an oxide film on the silicon surface that hinders uniform reaction between Co and Si, and makes Ta 2 O 5 (V 2 O 5 uniform at the interface with Si). Form a layer. In addition, cobalt diffuses during the silicide heat treatment, and passes through the Ta (V) layer and the Ta 2 O 5 (V 2 O 5 ) layer to react with the silicide at the Ta 2 O 5 (V 2 O 5 ) layer and the silicon interface. This will happen. The Co-Ta (V) alloy or Ta 2 O 5 (V 2 O 5 ) layer formed during the heat treatment serves to control the silicide reaction in the middle to prevent excessive consumption of silicon to obtain a thin cobalt silicide layer having a flat interface. Can be.
결과적으로, 산화성향이 강한 VA 족 원소인 Ta, V 를 중간층으로 이용함으로써 코발트와 실리콘의 균일한 반응을 방해하는 산화막을 제거하여 평탄한 실리사이드/실리콘 계면을 얻을 수 있으며, 중간에 형성된 Ta(V)-Co 합금과 Ta2O5(V2O5)층은 실리사이드 반응을 중간에서 제어하는 역할을 하여 실리콘의 과다한 소모를 방지하여 MOS 전극부에 얕은 접합을 유지할 수 있게 된다. (도 1b)As a result, by using Ta, V, which is a group of VA elements having a strong oxidation tendency, as an intermediate layer, an oxide film that prevents cobalt and silicon from uniformly reacting can be removed to obtain a flat silicide / silicon interface. The -Co alloy and the Ta 2 O 5 (V 2 O 5 ) layer serve to control the silicide reaction in the middle to prevent excessive consumption of silicon to maintain a shallow junction on the MOS electrode. (FIG. 1B)
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 트랜지스터 제조방법은, Co/Ta(V) 이중층을 이용하여 코발트 실리사이드를 형성함으로써 실리콘 표면에 산화막의 존재로 인하여 실리사이드와 실리콘 계면이 거칠다는 것, 실리사이드 반응이 빠르게 일어나 실리콘층이 과다하게 소모되므로 얕은 접합을 형성하기가 어렵다는 것 등과 같이 단일 코발트 실리사이드의 단점을 보완하여 실리콘 표면의 산화막을 충분히 제거시킬 뿐아니라 열처리 중 코발트와 결합하여 화합물을 형성하여 기판의 실리콘이 과잉소모되는 것을 방지한다. 결과적으로, 전계면에 걸쳐 균일한 반응이 일어나 평탄한 계면을 얻을 수 있으며 중간에 형성된 화합물 및 Ta2O5(V2O5) 층이 실리사이드 반응을 제어하여 실리콘의 과다한 소모를 방지함으로써 MOS 전극부에 얕은 접합을 유지할 수 있도록 하여 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 효과가 있다.As described above, in the method of manufacturing a transistor of a semiconductor device according to the present invention, a cobalt silicide is formed by using a Co / Ta (V) bilayer, so that the silicide and silicon interfaces are rough due to the presence of an oxide film on the silicon surface. The reaction takes place quickly, and the silicon layer is excessively consumed, making it difficult to form a shallow junction. Thus, the shortcomings of the single cobalt silicide are compensated for, and the oxide film on the silicon surface is sufficiently removed, and the compound is formed by combining with the cobalt during the heat treatment. To prevent the silicon from being consumed excessively. As a result, a uniform reaction occurs across the entire surface to obtain a flat interface, and the compound formed in the middle and the Ta 2 O 5 (V 2 O 5 ) layer control the silicide reaction to prevent excessive consumption of silicon, thereby preventing the MOS electrode portion. It is possible to maintain a shallow junction to the semiconductor device has the effect of improving the characteristics and reliability of the semiconductor device.
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| KR950012753A (en) * | 1992-10-09 | 1995-05-16 | 야마자끼 순페이 | Thin film type semiconductor device and its manufacturing method |
| JPH07321069A (en) * | 1994-05-26 | 1995-12-08 | Nec Corp | Manufacture of semiconductor integrated circuit device |
| JPH0878358A (en) * | 1994-09-06 | 1996-03-22 | Sony Corp | Manufacture of semiconductor device |
| JPH08116054A (en) * | 1994-10-14 | 1996-05-07 | Nec Corp | Semiconductor device comprising cobalt silicide film and its manufacture |
| JPH08260143A (en) * | 1995-03-20 | 1996-10-08 | Fujitsu Ltd | Method for forming magnetic material thin film and production of semiconductor device |
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| KR950012753A (en) * | 1992-10-09 | 1995-05-16 | 야마자끼 순페이 | Thin film type semiconductor device and its manufacturing method |
| JPH07321069A (en) * | 1994-05-26 | 1995-12-08 | Nec Corp | Manufacture of semiconductor integrated circuit device |
| JPH0878358A (en) * | 1994-09-06 | 1996-03-22 | Sony Corp | Manufacture of semiconductor device |
| JPH08116054A (en) * | 1994-10-14 | 1996-05-07 | Nec Corp | Semiconductor device comprising cobalt silicide film and its manufacture |
| JPH08260143A (en) * | 1995-03-20 | 1996-10-08 | Fujitsu Ltd | Method for forming magnetic material thin film and production of semiconductor device |
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