TW488035B - Manufacturing method of MOS transistor of embedded memory - Google Patents

Abstract

This invention provides a manufacturing method of MOS transistor of embedded memory on semiconductor wafer surface. A memory array and a periphery circuit are defined on a semiconductor wafer surface. A gate oxide layer, an undoped polysilicon layer and a dielectric layer are deposited sequentially. The undoped polysilicon layer on top of the memory array area is implanted into a doped polysilicon layer, which is etched to a predetermined depth. The dielectric layer on top of the memory array is removed. A metal silicide layer and a protection layer are formed on the wafer surface. A plural number of gate electrodes are formed on the memory array area through etching process, which is accompanied with in-situ removal of the protection layer and the silicide layer on top of the periphery circuit area. Finally, a plural number of gate electrodes are formed on the undoped polysilicon layer on top of the periphery circuit area and a spacer, a source electrode and a drain electrode are formed around the gate electrode.

Description

488035 V. Description of the invention (1) Field of the invention The present invention provides a method for manufacturing a MOS transistor with embedded memory. Background Description With the continuous improvement of process integration, the current trend of making semiconductor integrated circuits is to integrate mem ryce 1 1 array with high-speed logic circuit elements. At the same time, It is fabricated on a chip (ch ip) to form a kind of scattered memory that combines a memory array and logic circuits (10giccircuits) at the same time, so as to greatly save area and speed up signal processing speed. Please refer to FIGS. 1 to 5. FIGS. 1 to 5 are schematic diagrams of a conventional method for fabricating a metal oxide semiconductor (MOS) transistor with an embedded memory on a semiconductor wafer 10. As shown in Figure 1, a memory array region 14 and a peripheral circuit region 16 have been defined on the surface of the silicon substrate 12 of the semiconductor wafer 10, and the memory array region 14 includes a single cell well (ce 1 1 we 1 1) 18, and the peripheral circuit area 16 includes at least one N-type well 20 and at least one P-type well 22, and each area is separated by several shallow trench isolations 2 3. A conventional method is to sequentially form a gate oxide layer 21, a polycrystalline stone layer 24, and a polycide metal layer 26 before the surface of the semiconductor wafer 10 sequentially.

Page 5 488035 V. Description of the invention (2) and the top protective layer (c a p 1 a y e r) 2 8 formed by the gasification stone. Then, as shown in FIG. 1, a photoresist layer 30 is formed on the top protective layer 28, and a yellow light process (lithography) is used to simultaneously define the memory array area 14 and the peripheral circuit area in the photoresist layer 30. Pattern of gate positions of 16 (P a 11 er η). Subsequently, the patterned photoresist layer 30 is used as a mask layer to perform an etching process to remove the top protective layer 28, the polysilicon metal layer 26, and the polycrystalline polysilicon layer 2 4, until the gate oxide layer 21 surface, so that a plurality of gates 32 are formed above the cell wells 18 in the memory array area 14 and simultaneously in the N-type well 20 and the p-type well 22 in the peripheral circuit area 16 A plurality of gates 3 4 are formed above. As shown in FIG. 3, the photoresist layer 30 ′ above the top protective layer 28 is completely removed and an ion distribution process (i0ri impiantati) is performed on the silicon on both sides of the gates 3 2 and 3 4. A doped region (not shown) is formed on the surface of the substrate 12, and then a rapid thermal process (RTP) is used to make the dopant in the doped region into the silicon substrate 1 2 To form a lightly doped drain (LDD) 36 of each MOS electric solar heliosphere. 'As shown in Figure 4, a nitrogen oxide layer (not shown) is then deposited on the surface of the semiconductor wafer 10' and a non-isotropic epitaxial process is used to back and forth the nitrogen stone layer to the memory array area. A side wall 38 is formed around the gates 3 2 and 3 4 of 14 and the peripheral circuit area 16. Then, an ion layout process is performed to form the source and the source of each M 0 S transistor in the peripheral circuit area 16.

488035 V. Description of the invention (3) (drain). That is, first, a photoresist is used for the gates 32 and 34 of the N-type well 20 and the N-type well 20, and the iron '22 two-dimensional array region 14 is doped on the surface to form a doped layer ^ 1 ^; dopant Another photoresist is formed for the p-type well 22. In addition to the photoresist layer, the gate 34 above the well 2 2 is connected, and a p-type dopant is used to align the N-type well 2 of the peripheral circuit area μ. Doping is performed in 0 to form a doped region 40. The rapid heat treatment process causes the dopants of each doped region 40 and 42 to reach another 12 to form the source and sink of each Mos transistor in the peripheral circuit region 16. pole. Finally, as shown in FIG. 5, a metal silicide block (SAB) 44 is formed on the surface of the silicon substrate 4 in the memory array region 4 and a self-aligned metal silicide is performed in the peripheral circuit region 16 (Self-aligned silicide) process to form a self-aligned metal oxide layer 46 on the surface of each source and drain electrode, which completes the fabrication of metal oxide semiconductor (MOS) transistors, which are known to be embedded in memory. . ~ As the PMOS gates in the peripheral circuit area are undergoing an ion layout process, Boron penetrati0I1 issue is prone to occur, so ti prevents boron dopants in the PM0S gate from penetrating the gate oxide layer and diffusing to In stone substrates, the thickness of the polycrystalline silicon layer of the gate electrode is generally increased, so that the thickness of the polycrystalline silicon layer is increased to about 2000 to 300 angstroms. Therefore, in the process of manufacturing a memory chip, the conventional technology Integrate the fabrication of the gates in the peripheral circuit area and the memory area V. The thickness of the gate polycrystalline silicon layer in the memory array area is aligned with the thickness of the gate polycrystalline silicon layer in the peripheral circuit area. Therefore, = shoulder

488035 V. Description of the invention (4) It will be much thicker than the general memory system process (approximately 60 ~ 120 Angstroms), and as the accumulation degree of the memory array area increases, it will surely make it between the gates. The aspect ratio (aspectrati 〇) has increased greatly, so it is more likely to cause an overhang between adjacent gates in the memory array region when the interlayer dielectric layer is filled, forming a hole bridge. (Void bridge), which in turn leads to subsequent contact plugs (contact p 1 ug) prepared between the two adjacent gate structures, which can be electrically connected through conductive objects formed in the holes, resulting in a short circuit. Ask the gold column of the array beam body Li Yiqiao Yi array cave memory in the hole type to prevent birth into a low pre-production mountain Xin Jiang, the intercropping method is one pole, the lower gate supply method is wider than the two mention square is to make deeper When it is easy to control the body, the main body of the thyristor layer needs the main electricity of the thyristor layer to make the electricity body and to introduce the half of the electricity into the body. The method of the present invention is to define a memory array area and a peripheral circuits area on the surface of the semiconductor wafer, and then sequentially deposit a gate oxide layer, an undoped polysilicon layer, and An undoped polysilicon layer and a dielectric layer, and then the undoped polycrystalline silicon layer on the memory array region is implanted into a doped polycrystalline silicon layer. Subsequently, the doped polycrystalline silicon layer on the memory array region is etched to a predetermined depth, and the dielectric layer on the memory array region is removed. Then on the semiconductor

Page 8 488035 V. Description of the invention (5) A metal silicide (Si 1icide) layer and a protective layer are formed on the surface of the body wafer, and an etching process is used to form a plurality of gates on the memory array region, and ( in-si tu) removing the protection layer and the metal silicide layer on the peripheral circuit area. Finally, the surname of the undoped polycrystalline chip on the peripheral circuit area is engraved into a plurality of gates', and a spacer, a source, and a drain are formed around each of the gates. 0 The metal-oxide semiconductor transistor using the embedded memory fabricated by the present invention, because the doped polycrystalline silicon layer in the memory array region is etched to about half the original thickness, the gate height is greatly reduced, so the gate can be reduced In order to prevent the short circuit phenomenon caused by the formation of a hole bridge when an interlayer dielectric layer is formed in the memory array region. Detailed description of the invention ❿ Please refer to FIG. 6 to FIG. 18 ′ FIG. 6 to FIG. 18 are schematic diagrams of a method for fabricating a MOS transistor of an embedded memory on a semi-conductor wafer 60 according to the present invention. As shown in FIG. 6, a memory array region 62 and a peripheral circuit region 64 have been defined on the surface of the silicon substrate 71 of the semiconductor chip 60. The memory array region 62 includes a single cell well 76 and a peripheral circuit region 64. It includes at least one N-type well 72 and at least one P-type well 74, and each area is separated by a plurality of shallow trench isolations 61. In the present invention, a dielectric layer is sequentially formed before the surface of the semiconductor wafer 60.

Page 9 488035 V. Description of the invention (6) 6 6. An undoped polycrystalline silicon layer 68 and a dielectric layer 70. Then, as shown in FIG. 7, a photoresist layer is formed as the mask layer 78 above the peripheral circuit region 64, and an N-type ion implantation is performed on the undoped polycrystalline silicon layer 68 above the memory array region 62. A process is performed so that the undoped polycrystalline silicon layer 6 8 above the memory array region 62 is formed as an N-doped polycrystalline silicon layer 80. Then, as shown in FIG. 8, an etching process is performed to completely remove the dielectric layer 70 above the memory array region 62, and then etching the doped polycrystalline silicon layer 80 down to the original undoped polycrystalline silicon layer 68 One half of the total thickness is about 100 to 190 angstroms (angstrom). As shown in FIG. 9, after removing the mask layer 78 above the peripheral circuit area 64, a metal silicide layer 82 is sequentially formed on the surface of the semiconductor wafer 60 to reduce the contact interface of the doped polycrystalline silicon layer 80. For the resistor, a silicon nitride oxide layer 84 serves as an anti-reflection layer, a silicon nitride oxide layer 86 serves as a protective layer, and a photoresist layer 88. Then, a yellow light process is performed to define a plurality of patterns of the gate electrodes 90 in the photoresist layer 8 8 above the single cell well 7 6 in the memory array area 62, and then use the pattern of the photoresist layer 88 as A hard mask to etch the silicon-nitrogen layer 86, silicon oxynitride layer 84, metal silicide layer 82, and doped polycrystalline silicon layer 80 above the memory array region 62, to the surface of the dielectric layer 66, so that Gates 90 of a plurality of MOS transistors are formed on the memory array region 62. Simultaneously (in-situ) the silicon nitride layer 86, silicon oxynitride layer 84, and metal silicide layer 82 above the peripheral circuit region 64 are etched up to the surface of the dielectric layer 70, as shown in FIG.

Page 10 488035 V. Description of the invention (7) Then each of the array regions 6 2 is shown in FIG. 11 and the photoresist layer 9 4 above the side circuit region 64 is shown in FIG. Figure 3 shows the patterns of the gates of the N-type well 72 and the p-type well. The peripheral circuit area 64 has 6 surfaces on the peripheral electrodes 96, 97. As shown, an ion implantation process is performed to form a lightly doped drain (LDD) 92 that is a MOS transistor. After removing the photoresist layer 88, the peripheral electrical layer 70 is removed, and a silicon oxynitride layer (not shown) is formed on the surface of the semiconductor wafer 60 as an anti-reflection layer. However, a one-page optical process is performed, so that in the photoresist layer 94 above the peripheral circuit area 64 ^ 4, a plurality of photoresist layers 94 are used as a hard mask to etch the undoped polysilicon. The spar layer 6 8 until a plurality of mS transistor gates are formed on the dielectric layer circuit area 64

As shown in FIG. 14, the electrical schematic region f is subjected to an ion implantation process to form a lightly doped diode (LDD) 92 of each of the MOS transistors after forming the periphery as shown in FIG. As shown in Table 15 below, after removing the photoresist layer 94, a silicon nitride layer 9 8 is formed on the surface of the semiconductor wafer and covers the gate electrodes 90, 96, and 97 as shown in the table. Then, a photoresist layer 90 and a yellow light process are used to define the position of the NMOS on the peripheral circuit area 64 as shown in Fig. 10, and then #etch $ 路 区 6 4 of the P-shaped well 7 4 above the pole 9 7 surrounding nitrogen silicon layer 9 8,

^ Cheng Jia 丨 Positioner 99 in female 74, followed by an ion implantation process to form the source 102 and drain 104 of the NMOS transistor in the P-type well layer, and remove the photoresistance k as As shown in FIG. 17, a photoresist layer 93 and a yellow light are used again.

Page 11 488035 V. Description of the invention (8) The process is to define the position of PM0S on the peripheral circuit area 64, and then first engraved the nitrogen surrounding the gate electrode 9 6 above the N-type well 7 2 of the peripheral circuit area 64. A silicon layer 98 was formed to form a sidewall 100, and then an ion implantation process was performed to form a source 110 and a drain 104 of the PM0S transistor in the N-type well 72, and finally the photoresist layer 9 3 was removed. . After forming the source 102 and the drain 104 of each MOS transistor on the peripheral circuit region 64, a metal layer (not shown) made of cobalt (co) is formed on the surface of the semiconductor wafer 60, In addition, the metal layer covers the surfaces of the source electrodes 102, the drain electrodes 104, and the question electrodes 96 and 97 on the peripheral circuit area 64. Subsequently, a first rapid thermal processing (RTP) process is performed in a temperature range of 400 ° C to 600 ° C and a heating time of 10 to 50 seconds, so that each source electrode on the peripheral circuit area 64 is 10 2. A self-aligned silicide layer 106 is formed on the surface of the drain electrode 104 and the gate electrodes 96 and 97. A wet etching is then performed to remove the unreacted metal layer on the surface of the semiconductor wafer 60. Finally, a second rapid thermal processing (RTP) process is performed in a temperature range of 60 ° C to 80 ° C and a heating time of 〇0 ~ 50 seconds to align the self-alignment in the silicide layer 106. Co2Si and CoS i react to CoS i 2 with lower resistance, as shown in FIG. 18. The cobalt (Co) metal layer may be replaced with a metal layer such as titanium (Ti), nickel (Ni), or molybdenum (Mo). Since the method for making a MOS transistor of an embedded memory according to the present invention is to first etch the doped polycrystalline silicon layer in the memory array region to about half the original thickness, it can not affect the problem of boron penetration in the peripheral circuit region Considering that the gate thickness in the memory array area can be greatly reduced, so it can be reduced.

Page 12 488035 V. Description of the invention (9) The aspect ratio between the gates, thus avoiding the short circuit caused by the hole bridge. Compared with the conventional method for fabricating a metal oxide semiconductor transistor of an embedded memory, the gate height of the memory array region produced by using the present invention is reduced by about 100 to 1990 angstroms, so it is greatly reduced. The height of the gates in the memory array area can effectively prevent the formation of holes between two adjacent gates due to the high aspect ratio of the gates in the memory array area when the interlayer dielectric layer is formed. The problem of bridges. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the invention patent.

Page 13 488035 Simple illustration of the diagrams Simple illustration of the diagrams Figures 1 to 5 are schematic diagrams of the conventional method for making an M0S transistor of an embedded memory. FIG. 6 to FIG. 18 are schematic diagrams of a method for fabricating a MOS transistor of an embedded memory according to the present invention. Explanation of symbols in the diagram 38 40 44 46 60 62 66 42 70 Side wall Doping region Metallic material resist layer Self-aligned metal material layer Semiconductor wafer Memory array area Dielectric layer 61 Shallow trench isolation 64 Peripheral circuit area

10 Semiconductor wafer 12 Broken substrate 14 Memory array area 16 Peripheral circuit area 18 Single cell well 20 N-type well 21 Gate oxide layer 22 P-type well 23 Shallow trench isolation 24 Polycrystalline silicon layer 26 Polycrystalline siliconized metal layer 28 Top cap layer 30 Photoresistive layer 32 ^ 34 Intermediate pole 36 Lightly doped nonpolarity Page 14 488035 Simple illustration of the diagram 68 Undoped polycrystalline silicon layer 72 N-type well 71 Silicon substrate 76 Single cell well 74 P-type well 88 ^ 94 Photoresistive layer 78 Mask layer 82 Metal silicide 80 Doped polysilicon layer 86 ^ 98 Nitrogen silicon layer 84 Nitrogen oxide layer 92 Lightly doped drain electrode 90 ^ 96 ^ 97 Gate 102 Source 99 ^ 100 Side wall 106 Silicide Physical layer 104 Drain «

Page 15

Claims (1)

488035 VI. Application Scope of Patent 1 · A method for fabricating a metal oxide semiconductor of "embedded memory (embedded memory) with" 〇xide semi-conductor (MOS) "method, which includes The following steps: Provide a semiconductor wafer, and a silicon substrate surface of the semiconductor wafer has a memory array area and a peripheral circuit area (perimeter circuit area) defined thereon. -Sequentially forming a first dielectric layer, an undoped polysilicon (undoped polySilicon) layer and a second dielectric layer on the surface of the semiconductor wafer; ten undoped polycrystalline silicon layers above the memory array region; Performing a first ion implantation process (i 〇nimp 丨 antat 丨 〇n), so that the undoped polycrystalline silicon layer above the memory array region is formed into a doped polycrystalline silicon layer; | inspection-a meal engraving process To completely remove the second dielectric layer above the memory array region, and etch the doped polycrystalline silicon layer to a predetermined depth; • sequentially on the surface of the semiconductor wafer Forming a metal silicide (S 1 1 1 c 1 de) layer, a protective layer, and a < photoresist layer; performing a first yellow light process in the first photoresist layer above the memory array region A plurality of gate patterns are defined, and the pattern of the first photoresist layer is used as a hard mask. The protective layer, the metal silicide layer, and The doped polycrystalline silicon layer is up to the surface of the first dielectric layer, and the protective layer and the metal vermiculite layer above the peripheral circuit area are in-situ 'etched up to the surface of the second dielectric layer. Performing a first ion implantation process to form each of the memory array regions; Page 16 488035 VI. Application scope of patent The lightly doped electrode (1 igh 11 yd 〇peddrai η, LDD) of the MOS transistor; remove the first photoresist layer and the second over the peripheral circuit area A dielectric layer; forming a second photoresist layer on the surface of the semiconductor wafer; performing a second yellow light process to define a plurality of gate patterns in the second photoresist layer above the peripheral circuit area; using The pattern of the second photoresist layer is used as a hard mask, and the undoped polycrystalline silicon layer above the peripheral circuit area is etched up to the surface of the first dielectric layer to form each MO on the peripheral circuit area. The gate of the S transistor is subjected to a third ion implantation process to form a lightly doped drain (LDD) of each of the MOS transistors in the peripheral circuit area; removing the second photoresist layer; on the semiconductor wafer A nitrogen silicon layer is formed on the surface and covers each of the gate surfaces; an etching process is used to remove a portion of the nitrogen silicon layer in the peripheral circuit area to form around each of the gates in the peripheral circuit area A spacer; and Fourth ion implantation process' to form each of the peripheral circuit region on the source Μ 0 S pole transistor (s square u r c e) and without pole (d r a i η). 2. The method according to item 1 of the scope of patent application, wherein the first dielectric layer is composed of silicon dioxide (SiO 2) and is used as a gate oxide layer of each MOS transistor. Page 17 488035 6. Scope of patent application 3. The method according to item 1 of the patent scope, wherein the predetermined depth is approximately half of the total thickness of the undoped polycrystalline silicon layer. 4. The method according to item 1 of the scope of patent application, wherein the protective layer is composed of a silicon nitride compound, and between the protective layer and the metal silicide layer _ further contains a silicon-oxygen oxide (silicon-oxy -nitride (SiOxNy) layer, which is used as an anti-reflection coating (ARC). 5. If the method of claim 1 is applied, before the second photoresist layer is formed on the surface of the semiconductor wafer, a silicon oxynitride (SiOxNy) layer may be formed on the surface of the semiconductor wafer as an anti-reflection layer ( ARC). 6. If the method of claim 5 is applied, after the second photoresist layer is removed, the oxynitride fragment layer formed under the second photoresist layer must also be removed. 7. The method of claim 1, wherein after forming the source and drain of each of the MOS transistors on the peripheral circuit area, the method further includes the following steps: forming a semiconductor wafer surface A metal layer, and the metal layer covers each of the source, drain, and gate surfaces on the peripheral circuit area; and a first rapid thermal process (RTP) is performed Page 18 488035 6. Scope of patent application; performing a wet name engraving (wet e t c h) to remove the unreacted metal layer on the surface of the semiconductor wafer; and performing a second rapid thermal processing (RTP) process. 8. The method according to item 7 of the patent application, wherein the metal layer is composed of cobalt (Co), titanium (Ti), nickel (Ni) or platinum (Molybdenum, Mo). 9 For example, the method of claim 7 of the patent scope, wherein the temperature range of the first rapid heat treatment (RTP) process is 400 ° C ~ 60 ° C, the heating time is 10 ~ 50 seconds, and the second rapid The temperature range of the heat treatment (RTP) process is from 60 ° C to 80 ° C, and the heating time is from 10 to 50 seconds. 10. A method for fabricating a metal oxide semiconductor (MOS) transistor with embedded memory, the method includes the following steps: a semiconductor wafer is provided; a surface of a broken substrate of the semiconductor wafer has a memory array region and a A peripheral circuit region, and the memory array region includes at least one cell-well, and the peripheral circuit region includes at least one N-well and at least one P-well (P- well); sequentially forming a first dielectric layer, an undoped polycrystalline silicon layer and a second dielectric layer on the surface of the semiconductor wafer; performing an undoped polycrystalline silicon layer on the memory array region; A first ion implantation process to make the undoped polycrystalline silicon above the memory array region Page 19 488035 6. The patent application layer is formed as a doped polycrystalline silicon layer; an etching process is performed to completely remove the second dielectric layer above the memory array region, and the doped polycrystalline silicon layer is etched to a predetermined depth Forming a metal silicide layer, a protective layer, and a first photoresist layer in sequence on the surface of the semiconductor wafer; performing a first yellow light process on the first light above the cell well in the memory array region; A plurality of gate patterns are defined in the resist layer; the pattern of the first photoresist layer is used as a hard mask to etch the protective layer, the metal oxide layer, and the doped polysilicon layer over the memory array region. A spar layer, up to the surface of the first dielectric layer, and in-situ engraving the protective layer and the metal oxide layer above the peripheral circuit area until the surface of the second dielectric layer; removing The first photoresist layer; performing a second ion implantation process to form a lightly doped drain (LDD) of each of the MOS transistors in the memory array region; removing the second dielectric above the peripheral circuit region Layer; in the half A second photoresist layer is formed on the surface of the conductor wafer; a second yellow light process is performed to define a plurality of gate electrodes in the N-type well in the peripheral circuit area and the second photoresist layer above the P-type well. Pattern; using the pattern of the second photoresist layer as a hard mask, etching the undoped polycrystalline silicon layer above the peripheral circuit area up to the surface of the first dielectric layer to form each MO on the peripheral circuit area Removing the second photoresist layer between the S electrodes; Page 20 488035 VI. Apply for a third ion implantation process to form a lightly doped drain (LDD) of each M 0 S transistor in the peripheral circuit area; form a nitrogen on the surface of the semiconductor wafer Silicon layer and covering the surface of each gate; etching the nitrogen stone layer around each gate above the P-well in the peripheral circuit area to form a first side wall and performing a fourth ion implantation process, Forming a source and a drain of the NMOS transistor in the P-type well; and etching the nitrogen silicon layer around each of the gates above the N-type well in the peripheral circuit area to form a second sidewall, and perform a fifth An ion implantation process is used to form a source and a drain of a PMOS transistor in the N-well. 1 1. The method of claim 10, wherein the first dielectric layer is composed of silicon dioxide (Si 02), and is used as a gate oxide layer of each MOS transistor. 12. The method of claim 10, wherein the predetermined depth is approximately half the total thickness of the undoped polycrystalline silicon layer. 13. The method according to item 10 of the scope of patent application, wherein the protective layer is composed of a silicon nitride compound, and a silicon oxynitride (S i 0) is further included between the protective layer and the metal silicide layer. XN y) layer is used as an anti-reflection layer (ARC). 14. The method according to item 10 of the scope of patent application, wherein the semiconductor wafer is Page 21 488035 6. Scope of patent application Before the second photoresist layer is formed on the surface, a silicon oxynitride (Si 0xNy) layer may be formed as an anti-reflection layer (ARC) before the surface of the semiconductor wafer. 15. The method according to item 14 of the scope of patent application, wherein after the second photoresist layer is removed, the oxynitride layer formed under the second photoresist layer must also be removed. 16. The method according to item 10 of the scope of patent application, wherein after forming the source and terminals of each of the MOS transistors on the peripheral circuit area, the method further includes the following steps: In the semiconductor A metal layer is formed on the surface of the wafer, and the metal layer covers each of the source, drain, and gate surfaces on the peripheral circuit area; a first rapid thermal processing (RTP) process is performed; a wet etching is performed to remove The metal layer not reacted on the surface of the semiconductor wafer; and performing a second rapid thermal processing (RTP) process. 17. The method according to item 16 of the scope of patent application, wherein the metal layer is composed of cobalt (Co), titanium (Ti), nickel (Ni), or molybdenum (Mo). 1 8. The method according to item 16 of the scope of patent application, wherein the temperature range of the first rapid thermal processing (RTP) process is 400 ° C ~ 600 ° C, and the heating time is 100 ~ 50 seconds, and The temperature range of the second rapid heat treatment (RTP) process is 60 (TC ~ 800 ° C), and the heating time is 10 ~ 50 seconds. Page 22