CN111415933A - 半导体元件及其制造方法 - Google Patents

半导体元件及其制造方法 Download PDF

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CN111415933A
CN111415933A CN201910079079.4A CN201910079079A CN111415933A CN 111415933 A CN111415933 A CN 111415933A CN 201910079079 A CN201910079079 A CN 201910079079A CN 111415933 A CN111415933 A CN 111415933A
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layer
region
opening
barrier
conductor
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CN111415933B (zh
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廖宏魁
刘振强
时国昇
施咏尧
徐铭聪
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Powerchip Technology Corp
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Powerchip Technology Corp
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Abstract

本发明公开一种半导体元件及其制造方法，该半导体元件包括基底、隔离结构、阻障结构、第一导体层、第二导体层、第一栅介电层以及第二栅介电层。基底具有第一区与第二区。阻障结构位于隔离结构上。第一导体层位于第一区上。第二导体层位于第二区上。第一栅介电层位于第一导体层与第一区的基底之间。第二栅介电层位于第二导体层与第二区的基底之间。隔离结构分隔第一栅介电层与第二栅介电层。

Description

半导体元件及其制造方法
技术领域
本发明涉及一种集成电路及其制造方法，且特别是涉及一种半导体元件及其制造方法。
背景技术
在集成电路制造技术中，对多晶硅进行预掺杂(pre-doping)注入制作工艺可降低多晶硅的电阻值。另外，此预掺杂注入制作工艺也可减少多晶硅空乏现象(poly depletionphenomenon)。
然而，随着集成电路愈变愈小，在预掺杂注入制作工艺与退火制作工艺之后，N型金属氧化物半导体(N-Metal Oxide Semiconductor，NMOS)元件与P型金属氧化物半导体(P-Metal Oxide Semiconductor，PMOS)元件之间的多晶硅栅极区域的相互扩散(inter-diffusion)情况将变得更加严重。此相互扩散将影响临界电压(threshold voltage)，且进一步地限制未来微型化元件的发展。因此，如何提出一种半导体元件及其制造方法，以降低NMOS元件与PMOS元件之间多晶硅栅极区域的相互扩散将成为重要的一门课题。
发明内容
本发明提供一种半导体元件，其通过将阻障结构形成在第一导体层与第二导体层之间来降低第一导体层与第二导体层之间的相互扩散，以改善临界电压的控制，进而提升微型化半导体元件的能力。
本发明提供一种半导体元件及其制造方法，其利用镶嵌制作工艺(damasceneprocess)形成第一导体层与第二导体层，以避免等离子体损害(plasma induced damage，PID)的产生，进而提升产品的可靠度。
本发明提供一种半导体元件包括：基底、隔离结构、阻障结构、第一导体层、第二导体层、第一栅介电层以及第二栅介电层。基底具有第一区与第二区。阻障结构位于隔离结构上。第一导体层位于第一区上。第二导体层位于第二区上。第一栅介电层位于第一导体层与第一区的基底之间。第二栅介电层位于第二导体层与第二区的基底之间。隔离结构分隔第一栅介电层与第二栅介电层。
本发明提供一种半导体元件的制造方法，其步骤如下。在基底中形成隔离结构，以将基底分成第一区与第二区。在基底上全面性地形成阻障材料。图案化阻障材料，以形成第一开口、第二开口以及位于第一开口与第二开口之间的阻障结构。在第一开口中形成第一栅介电层，并于第二开口中形成第二栅介电层。将导体材料填入第一开口与第二开口中。对导体材料进行平坦化制作工艺，以于第一开口中形成第一导体层并于第二开口中形成第二导体层。
基于上述，本发明通过在NMOS区域与PMOS区域之间形成阻障结构。在此情况下，本发明可在维持半导体元件的芯片使用面积时，避免NMOS元件的栅极与PMOS元件的栅极之间相互扩散，由此改善临界电压的控制，进而提升微型化半导体元件的能力。另外，本发明还通过镶嵌制作工艺来形成NMOS区域与PMOS区域中的栅极结构，以避免等离子体损害的产生，进而提升产品的可靠度。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附的附图作详细说明如下。
附图说明
图1A至图1J是本发明第一实施例的一种半导体元件的制造流程的上视示意图；
图2A至图2J分别是沿着图1A至图1J的线I-I’的剖面示意图；
图3是本发明的第二实施例的一种半导体元件的剖面示意图；
图4A至图4J是本发明第二实施例的一种半导体元件的制造流程的上视示意图；
图5A至图5J分别是沿着图4A至图4J的线II-II’的剖面示意图。
符号说明
10：第一开口
12、12a：第一掩模开口
20：第二开口
100：基底
101：隔离结构
102、102a：阻障材料
104、104a：第一阻障层
106、106a、106b：第二阻障层
106r：凹陷
108、108a：介电层
108t：介电层的顶面
110、120：掺杂区
112：第一掩模图案
114：第二掩模图案
122、222：阻障结构
122t、222t：阻障结构的顶面
124：下部
126：上部
128：导体材料
130a：第一栅极结构
130b：第二栅极结构
132：第一栅介电层
134：第二栅介电层
138：导体材料
138t：导体材料的顶面
138a、142：第一导体层
142t：第一导体层的顶面
138b、144：第二导体层
144t：第二导体层的顶面
138c、146：第三导体层
140、140’：金属硅化物层
148：导体结构
AA：主动(有源)区
D1、D2：高度差
R1：第一区
R2：第二区
具体实施方式
参照本实施例的附图以更全面地阐述本发明。然而，本发明也可以各种不同的形式体现，而不应限于本文中所述的实施例。附图中的层与区域的厚度会为了清楚起见而放大。相同或相似的标号表示相同或相似的元件，以下段落将不再一一赘述。
图1A至图1J是依照本发明第一实施例的一种半导体元件的制造流程的上视示意图。图2A至图2J分别是沿着图1A至图1J的线I-I’的剖面示意图。以下实施例是以平面式(planar)MOS元件为例来说明，但本发明不以此为限。
本发明第一实施例提供一种半导体元件的制造方法，其步骤如下所示。请参照图1A与图2A，首先，提供基底100。在一些实施例中，基底100是由硅或其他半导体材料制成的。另外，基底100也可包括其它元素半导体材料，例如锗、砷化镓或其它合适的半导体材料。此外，在替代实施例中，基底100也可由例如硅锗、碳化硅锗、磷砷化镓或磷铟化镓的合金半导体所制成。
接着，在基底100中形成隔离结构101，以将基底100分成第一区R1与第二区R2。在一些实施例中，第一区R1与第二区R2可视为主动区AA。由上视图1A所示，隔离结构101环绕第一区R1与第二区R2。由剖视图2A所示，隔离结构101的顶面高于基底100的顶面。但本发明不以此为限，在其他实施例中，隔离结构101的顶面与基底100的顶面也可实质上共平面。在一实施例中，隔离结构101的材料包括氧化硅、氮化硅、氮氧化硅或其组合。在替代实施例中，隔离结构101可以是浅沟槽隔离结构(STI)。
请参照图1B与图2B，于基底100上全面性地形成阻障材料102与介电层108。具体来说，阻障材料102包括第一阻障层104与第二阻障层106。第一阻障层104共形地覆盖基底100与隔离结构101的表面。第二阻障层106覆盖第一阻障层104的表面。介电层108覆盖第二阻障层106的表面，使得第二阻障层106位于介电层108与第一阻障层104之间。在一实施例中，第一阻障层104可以是牺牲氧化物(例如是氧化硅)，其厚度约为5.5nm至6.5nm，其形成方法可例如是化学气相沉积法(CVD)、炉管氧化法、原子层沉积法(ALD)或其组合。第二阻障层106的材料包括氮化硅、氮氧化硅、碳化硅、或其组合，其厚度约为110nm至130nm，其形成方法可例如是CVD、ALD或其组合。介电层108的材料包括氧化硅、氮化硅、氮氧化硅、碳化硅、或其组合，其厚度约为40nm至60nm，其形成方法可例如是CVD、ALD或其组合。在替代实施例中，介电层108与第二阻障层106具有不同材料且第二阻障层106与第一阻障层104也具有不同材料，以利于后续图2C至图2F的图案化制作工艺。举例来说，第一阻障层104可例如是氧化硅层；第二阻障层106可以是氮化硅层；而介电层108可例如是四乙氧基硅烷(tetraethosiloxane，TEOS)层。
另外，在形成第一阻障层104之前，本实施例的半导体元件的制造方法还包括在基底100中形成掺杂区110、120。详细地说，掺杂区110位于第一区R1的基底100中，其可视为P型阱区，其所注入的掺质可例如是硼或铟(In)，掺杂的浓度可例如是4.5×1012/cm3至5.5×1012/cm3。掺杂区120位于第二区R2的基底100中，其可视为N型阱区，其所注入的掺质可例如是磷、砷或锑(Sb)，掺杂的浓度可例如是5.5×1012/cm3至6.5×1012/cm3。在此情况下，具有P型阱区110的第一区R1可视为NMOS区域；而具有N型阱区120的第二区R2则可视为PMOS区域。
请参照图1C与图2C，在介电层108上形成第一掩模图案112。第一掩模图案112具有第一掩模开口12。如上视图1C所示，第一掩模开口12为一条状开口，其暴露出第一区R1、第二区R2以及第一区R1与第二区R2之间的介电层108。在一实施例中，第一掩模图案112的材料包括光致抗蚀剂材料，其形成方法可以是旋转涂布法与曝光显影法。
请参照图1C～图1D与图2C～图2D，以第一掩模图案112为蚀刻掩模，进行第一蚀刻制作工艺，移除部分介电层108，以暴露出第二阻障层106。在一实施例中，第一蚀刻制作工艺包括干式蚀刻制作工艺，其可例如是反应性离子蚀刻法(RIE)。在本实施例中，第二阻障层106可视为第一蚀刻制作工艺的蚀刻停止层。
请参照图1E与图2E，在移除第一掩模图案112之后，在第二阻障层106上形成第二掩模图案114。如上视图1E所示，第二掩模图案114位于第一区R1与第二区R2之间且横跨第一掩模开口12a。在此，第一掩模开口12a复制图1C与图2C的第一掩模开口12的形状，且由介电层108a所定义。如剖视图2E所示，第二掩模图案114对应于第一区R1与第二区R2之间的隔离结构101。在一实施例中，第二掩模图案114的材料包括光致抗蚀剂材料，其形成方法可以是旋转涂布法与曝光显影法。
请参照图1E～图1F与图2E～图2F，以第二掩模图案114与介电层108a为蚀刻掩模，进行第二蚀刻制作工艺，移除部分第二阻障层106，以暴露出第一阻障层104。在一实施例中，第二蚀刻制作工艺包括干式蚀刻制作工艺，其可例如是RIE。在本实施例中，第一阻障层104可视为第二蚀刻制作工艺的蚀刻停止层。
请参照图1F～图1G与图2F～图2G，移除第一掩模图案114之后，进而移除未被第二阻障层106a所覆盖的第一阻障层104，以暴露出第一区R1的基底100与第二区R2的基底100，进而形成了第一开口10与第二开口20。具体来说，第一开口10暴露出第一区R1的基底100(或掺杂区110)；而第二开口20暴露出第二区R2的基底100(或掺杂区120)。如图2G所示，第一开口10与第二开口20由经图案化的阻障材料102a的侧壁所定义。在此情况下，位于第一开口10与第二开口20之间的隔离结构101上的经图案化的阻障材料102a可视为阻障结构122，其包括下部124与上部126。在一些实施例中，阻障结构122的顶面122t与介电层108a的顶面108t具有高度差D1。高度差D1约为10nm至20nm。
请继续参照图1G与图2G，在移除部分第一阻障层104之后，在第一开口10的基底100上形成第一栅介电层132并于第二开口20的基底100上形成第二栅介电层134。在此情况下，如图1G所示，第一栅介电层132的顶面与第二栅介电层134的顶面低于隔离结构101的顶面。也就是说，隔离结构101分隔第一栅介电层132与第二栅介电层134。在一实施例中，第一栅介电层132与第二栅介电层134的材料包括介电材料，其可例如是氧化硅、氮化硅、氮氧化硅、高介电常数介电材料(例如介电常数大于4)或其组合，其厚度约为2nm至7nm，其形成方法可以是热氧化法、CVD或其组合。在一些实施例中，第一栅介电层132与第二栅介电层134可同时形成，且具有相同厚度。在替代实施例中，第一栅介电层132与第二栅介电层134可依序形成，且具有不同厚度。
请参照图1H与图2H，全面性地形成导体材料128。具体来说，导体材料128填入第一开口10与第二开口20，且覆盖阻障结构122的顶面122t与介电层108a的顶面108t。在一实施例中，导体材料128包括半导体材料，其形成方法可以是外延法、CVD或其组合。所述半导体材料可例如是掺杂多晶硅、非掺杂多晶硅、硅锗、类似半导体材料或其组合。
请参照图1H～图1I与图2H～图2I，对导体材料128进行平坦化制作工艺，以暴露出介电层108a的顶面108t。在一实施例中，所述平坦化制作工艺可以是化学机械研磨(CMP)制作工艺、回蚀刻制作工艺或其组合。在此情况下，如图2I所示，经平坦化的导体材料138包括第一部分138a、第二部分138b以及第三部分138c。具体来说，第一部分138a填入第一开口10中，其可视为第一导体层138a。第二部分138b填入第二开口20中，其可视为第二导体层138b。第三部分138c可视为第三导体层138c，其位于第一部分138a与第二部分138b之间且覆盖阻障结构122的顶面122t。在一些实施例中，介电层108a可视为平坦化制作工艺的研磨停止层或蚀刻停止层。在其他实施例中，在进行平坦化制作工艺之后，导体材料138的顶面138t与介电层108a的顶面108t实质上共平面。在替代实施例中，导体材料138的顶面138t高于阻障结构122的顶面122t。另外，在进行平坦化制作工艺期间，部分介电层108a也会被损耗掉，使得介电层108a的厚度变薄。
请参照图1I～图1J与图2I～图2J，将第一导体层138a掺杂为N型导体层142(以下称为第一导体层142)，并将第二导体层138b掺杂为P型导体层144(以下称为第二导体层144)。具体来说，在一实施例中，可将光致抗蚀剂图案(未绘示)形成在导体材料138上，以暴露出第一导体层138a，接着，对第一导体层138a进行第一离子注入制作工艺。所述第一离子注入制作工艺可以是注入N型掺质，其可例如是磷、砷或锑(Sb)，掺杂的浓度可例如是5.5×1015/cm3至6.5×1015/cm3。在另一实施例中，可将另一光致抗蚀剂图案(未绘示)形成在导体材料138上，以暴露出第二导体层138b，接着，对第二导体层138b进行第二离子注入制作工艺。所述第二离子注入制作工艺可以是注入P型掺质，其可例如是硼或铟(In)，掺杂的浓度可例如是3.0×1015/cm3至5.0×1015/cm3。在替代实施例中，第一离子注入制作工艺可于第二离子注入制作工艺之前或之后进行。
在进行第一离子注入制作工艺与第二离子注入制作工艺之后，进行退火(anneal)制作工艺，以将N型掺质与P型掺质分别驱入至第一导体层142的下方与第二导体层144的下方，进而增加第一导体层142的下方与第二导体层144的下方的掺杂浓度。如此一来，便可去除第一导体层142与第一栅介电层132之间以及第二导体层144与第一栅介电层132之间的空乏层，由此降低有效介电厚度(effective dielectric thickness)并提升饱和电流(saturation current)。在此情况下，部分N型掺质与部分P型掺质也会分别驱入至第一导体层142与第二导体层144之间的第三导体层146。也就是说，第三导体层146具有N型掺质与P型掺质。
值得注意的是，本实施例通过在第一区R1(或NMOS区域)与第二区R2(PMOS区域)之间形成阻障结构122。因此，本实施例可在维持半导体元件的芯片使用面积时，降低第一导体层142(其可视为NMOS元件的栅极)与第二导体层144(其可视为PMOS元件的栅极)之间的互相扩散，由此改善临界电压的控制，进而提升微型化半导体元件的能力。另外，本实施例还通过镶嵌制作工艺(如图2H至图2J所示)来形成第一导体层142与第二导体层144，以避免等离子体损害的产生，进而提升产品的可靠度。
如图2J所示，在进行退火制作工艺之后，可在经掺杂的导体结构148上形成金属硅化物层140。在一些实施例中，金属硅化物层140的材料例如是硅化镍(NiSi)、硅化钴(CoSi)、硅化钛(TiSi)、硅化钨(WSi)、硅化钼(MoSi)、硅化铂(PtSi)、硅化钯(PdSi)或其组合。金属硅化物层140的形成方法为本领域技术人员所熟知，于此便不再详述。
如图2J所示，在形成金属硅化物层140之后，进行湿式蚀刻制作工艺，移除介电层108a及其下方的第二阻障层106a与第一阻障层104a，以暴露出隔离结构101。在一些实施例中，所述湿式蚀刻制作工艺包括多道蚀刻步骤，以依序移除介电层108a、第二阻障层106a以及第一阻障层104a。举例来说，可先利用稀释氢氟酸(DHF)溶液来移除最上层的介电层108a，接着利用热磷酸溶液来移除第二阻障层106a，最后再利用DHF溶液来移除最下层的第一阻障层104a。值得注意的是，由于介电层108a、第二阻障层106a以及第一阻障层104a所构成的堆叠结构与经掺杂的导体结构148以及金属硅化物层140具有高的蚀刻选择比，因此，在移除介电层108a、第二阻障层106a以及第一阻障层104a所构成的堆叠结构时，不会损耗或仅轻微损耗经掺杂的导体结构148以及金属硅化物层140。
请参照图2J，以上述方法所制造的半导体元件包括：基底100、隔离结构101、掺杂区110、120、阻障结构122、第一栅介电层132、第一导体层142、第二栅介电层134以及第二导体层144。具体来说，隔离结构101位于基底100中，以将基底100分隔成第一区R1与第二区R2。掺杂区110位于第一区R1的基底100中，以形成NMOS区域。掺杂区120位于第二区R2的基底100中，以形成PMOS区域。
如图2J所示，阻障结构122位于第一区R1与第二区R2之间的隔离结构101上。第一导体层142位于第一区R1的基底100上，且第一栅介电层132位于第一导体层142与第一区R1的基底100之间。在一实施例中，第一栅介电层132与其上的第一导体层142可视为第一栅极结构130a。第二导体层144位于第二区R2的基底100上，且第二栅介电层134位于第二导体层144与第二区R2的基底100之间。在另一实施例中，第二栅介电层134与其上的第二导体层144可视为第二栅极结构130b。
值得注意的是，阻障结构122分隔第一导体层142与第二导体层144，其可降低第一导体层142(其可视为NMOS元件的栅极)与第二导体层144(其可视为PMOS元件的栅极)之间的互相扩散，由此改善临界电压的控制。具体来说，阻障结构122包括下部124与上部126。在一些实施例中，下部124与上部126具有不同的介电材料。举例来说，下部124可以是氧化硅层；而上部126则可以是氮化硅层。在替代实施例中，阻障结构122具有实质上垂直于基底100的顶面的侧壁。
如图2J所示，第一导体层142与第二导体层144通过第三导体层146连接，以形成连续的导体结构148。导体结构148横越阻障结构122且覆盖第一栅介电层132与第二栅介电层134。在一些实施例中，由于第一导体层142与第二导体层144是通过镶嵌制作工艺所形成，因此，第一导体层142与第二导体层144皆具有实质上垂直于基底100的顶面的侧壁。另外，本实施例的半导体元件更包括金属硅化物层140，其位于第一导体层142、第二导体层144以及阻障结构122(或第三导体层146)上，以降低第一导体层142与第二导体层144的阻抗。
图3是依照本发明的第二实施例的一种半导体元件的剖面示意图。
请参照图3，基本上，第二实施例的半导体元件与第一实施例的半导体元件相似。上述两者不同之处在于：第二实施例的半导体元件不具有图2J的第三导体层146。也就是说，如图3所示，第一导体层142的顶面142t、第二导体层144的顶面144t以及阻障结构222的顶面222t实质上共平面，且金属硅化物层140’直接接触第一导体层142的顶面142t、第二导体层144的顶面144t以及阻障结构222的顶面222t。
具体来说，上述第二实施例的半导体元件的制造方法的步骤如下所示。
图4A至图4J是依照本发明第二实施例的一种半导体元件的制造流程的上视示意图。图5A至图5J分别是沿着图4A至图4J的线II-II’的剖面示意图。
请参照图4A～图4C与图5A～图5C，基本上，图4A～图4C与图5A～图5C的步骤与图1A～图1C与图2A～图2C相似，且详细步骤已于上述段落详细说明过，于此便不再赘述。
请参照图4C～图4D与图5C～图5D，以第一掩模图案112为蚀刻掩模，进行第一蚀刻制作工艺，移除部分介电层108，以暴露出第二阻障层106。在本实施例中，部分第二阻障层106也被移除，以在经凹蚀的第二阻障层106a上形成凹陷106r。也就是说，外露于第一掩模开口12的第二阻障层106a的厚度降低。在一些实施例中，如图5D所示，被介电层108a所覆盖的第二阻障层106a的厚度大于未被介电层108a所覆盖的第二阻障层106a的厚度。
请参照图4E与图5E，在经凹蚀的第二阻障层106a上或凹陷106r中形成第二掩模图案114。如上视图5E所示，第二掩模图案114位于第一区R1与第二区R2之间且横跨第一掩模开口12a。于此，第一掩模开口12a是由介电层108a所定义。如剖视图5E所示，第二掩模图案114对应于第一区R1与第二区R2之间的隔离结构101。
请参照图4E～图4F与图5E～图5F，以第二掩模图案114与介电层108a为蚀刻掩模，进行第二蚀刻制作工艺，移除部分第二阻障层106a，以暴露出第一阻障层104。在本实施例中，第一阻障层104可视为第二蚀刻制作工艺的蚀刻停止层。
请参照图4F～图4G与图5F～图5G，移除第一掩模图案114之后，进而移除未被第二阻障层106b所覆盖的第一阻障层104，以暴露出第一区R1的基底100与第二区R2的基底100，进而形成了第一开口10与第二开口20。具体来说，第一开口10暴露出第一区R1的基底100(或掺杂区110)；而第二开口20暴露出第二区R2的基底100(或掺杂区120)。如图5G所示，第一开口10与第二开口20由经图案化的阻障材料102a的侧壁所定义。在此情况下，位于第一开口10与第二开口20之间的隔离结构101上的经图案化的阻障材料102a可视为阻障结构222，其包括下部224与上部226。在一些实施例中，阻障结构222的顶面222t与第二阻障层106b的顶面106t具有高度差D2。高度差D2约为10nm至20nm。在替代实施例中，阻障结构222的上部226的厚度小于第二阻障层106b的厚度。
请继续参照图4G与图5G，在移除部分第一阻障层104之后，在第一开口10的基底100上形成第一栅介电层132并于第二开口20的基底100上形成第二栅介电层134。在此情况下，如图5G所示，第一栅介电层132的顶面与第二栅介电层134的顶面低于隔离结构101的顶面。也就是说，隔离结构101分隔第一栅介电层132与第二栅介电层134。
请参照图4H与图5H，全面性地形成导体材料128。具体来说，导体材料128填入第一开口10与第二开口20，且覆盖阻障结构222的顶面222t与介电层108a的顶面108t。
请参照图4H～图4I与图5H～图5I，对导体材料128进行平坦化制作工艺，以暴露出第二阻障层106b的顶面106t。在此情况下，如图5I所示，经平坦化的导体材料138包括第一部分138a、第二部分138b以及第三部分138c。具体来说，第一部分138a填入第一开口10中，其可视为第一导体层138a。第二部分138b填入第二开口20中，其可视为第二导体层138b。第三部分138c可视为第三导体层138c，其位于第一部分138a与第二部分138b之间且覆盖阻障结构222的顶面222t。在一些实施例中，第二阻障层106b可视为平坦化制作工艺的研磨停止层或蚀刻停止层。在其他实施例中，在进行平坦化制作工艺之后，导体材料138的顶面138t与第二阻障层106b的顶面106t实质上共平面。
请参照图4I～图4J与图5I～图5J，将第一导体层138a掺杂为N型导体层142(以下称为第一导体层142)，并将第二导体层138b掺杂为P型导体层144(以下称为第二导体层144)。接着，进行退火制作工艺，以将N型掺质与P型掺质分别驱入至第一导体层142的下方与第二导体层144的下方。
如图5J所示，在进行退火制作工艺之后，进行金属硅化制作工艺，以于第一导体层142、第二导体层144以及阻障结构222上形成金属硅化物层140’。在一些实施例中，所述金属硅化制作工艺的步骤包括：沉积金属层，再进行加热制作工艺，以使金属层与部分导体层反应，由此形成金属硅化物层140’。在本实施例中，阻障结构222上的第三导体层138c(如图5I所示)会与所述金属层反应，以完全硅化(fully silicide)为金属硅化物层140’。在此情况下，金属硅化物层140’覆盖且直接接触第一导体层142的顶面142t、第二导体层144的顶面144t以及阻障结构222的顶面222t。
综上所述，本发明通过在NMOS区域与PMOS区域之间形成阻障结构。在此情况下，本发明可在维持半导体元件的芯片使用面积时，避免NMOS元件的栅极与PMOS元件的栅极之间相互扩散，由此改善临界电压的控制，进而提升微型化半导体元件的能力。另外，本发明还通过镶嵌制作工艺来形成NMOS区域与PMOS区域中的栅极结构，以避免等离子体损害的产生，进而提升产品的可靠度。
虽然结合以上实施例公开了本发明，然而其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，可作些许的更动与润饰，故本发明的保护范围应当以附上的权利要求所界定的为准。

Claims (10)

1.一种半导体元件，其特征在于，包括：
基底，具有第一区与第二区；
隔离结构，位于所述第一区与所述第二区之间的所述基底中；
阻障结构，位于所述隔离结构上；
第一导体层，位于所述第一区上；
第二导体层，位于所述第二区上；
第一栅介电层，位于所述第一导体层与所述第一区的所述基底之间；以及
第二栅介电层，位于所述第二导体层与所述第二区的所述基底之间，其中所述隔离结构分隔所述第一栅介电层与所述第二栅介电层。
2.如权利要求1所述的半导体元件，其中所述阻障结构包括下部与上部，所述下部与所述上部具有不同的介电材料。
3.如权利要求1所述的半导体元件，其中所述阻障结构分隔所述第一导体层与所述第二导体层，且所述第一导体层的顶面、所述第二导体层的顶面以及所述阻障结构的顶面实质上共平面。
4.如权利要求1所述的半导体元件，其中所述第一导体层与所述第二导体层彼此连接以形成连续的导体结构，所述导体结构横越所述阻障结构且覆盖所述第一栅介电层与所述第二栅介电层。
5.如权利要求4所述的半导体元件，其中所述导体结构包括：
所述第一导体层，具有N型掺质；
所述第二导体层，具有P型掺质；以及
第三导体层，位于所述第一导体层与所述第二导体层之间且具有所述N型掺质与所述P型掺质。
6.如权利要求1所述的半导体元件，还包括：金属硅化物层位于所述第一导体层、所述第二导体层以及所述阻障结构上。
7.一种半导体元件的制造方法，包括：
在基底中形成隔离结构，以将所述基底分成第一区与第二区；
在所述基底上全面性地形成阻障材料；
图案化所述阻障材料，以形成第一开口、第二开口以及位于所述第一开口与所述第二开口之间的阻障结构；
在所述第一开口中形成第一栅介电层，并于所述第二开口中形成第二栅介电层；
将导体材料填入所述第一开口与所述第二开口中；以及
对所述导体材料进行平坦化制作工艺，以于所述第一开口中形成第一导体层并于所述第二开口中形成第二导体层。
8.如权利要求7所述的半导体元件的制造方法，其中第一导体层与所述第二导体层彼此连接以形成连续的导体结构，所述导体结构横越所述阻障结构并填入所述第一开口与所述第二开口中。
9.如权利要求7所述的半导体元件的制造方法，其中所述图案化所述阻障材料的步骤包括：
在所述阻障材料上形成第一掩模图案；
以所述第一掩模图案为蚀刻掩模进行第一蚀刻制作工艺，以在所述阻障材料上形成凹陷；
在所述凹陷中形成第二掩模图案；以及
以所述第二掩模图案为蚀刻掩模进行第二蚀刻制作工艺，以形成所述第一开口与所述第二开口，其分别暴露出所述第一区与所述第二区的所述基底。
10.如权利要求7所述的半导体元件的制造方法，还包括：
进行第一离子注入制作工艺，以将所述第一导体层掺杂为N型；
进行第二离子注入制作工艺，以将所述第二导体层掺杂为P型；以及
在所述第一导体层、所述第二导体层以及所述阻障结构上形成金属硅化物层。
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