TWI677902B - 硬遮罩之形成方法、硬遮罩之形成裝置及記憶媒體 - Google Patents

硬遮罩之形成方法、硬遮罩之形成裝置及記憶媒體 Download PDF

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Publication number
TWI677902B
TWI677902B TW106109563A TW106109563A TWI677902B TW I677902 B TWI677902 B TW I677902B TW 106109563 A TW106109563 A TW 106109563A TW 106109563 A TW106109563 A TW 106109563A TW I677902 B TWI677902 B TW I677902B
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TW
Taiwan
Prior art keywords
substrate
hard mask
material portion
plateable
catalyst
Prior art date
Application number
TW106109563A
Other languages
English (en)
Chinese (zh)
Other versions
TW201810374A (zh
Inventor
岩下光秋
Mitsuaki Iwashita
長尾健
Takeshi Nagao
水谷信崇
Nobutaka Mizutani
田中崇
Takashi Tanaka
八田浩一
Koichi Yatsuda
岩井和俊
Kazutoshi Iwai
稲富裕一郎
Yuichiro Inatomi
Original Assignee
日商東京威力科創股份有限公司
Tokyo Electron Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商東京威力科創股份有限公司, Tokyo Electron Limited filed Critical 日商東京威力科創股份有限公司
Publication of TW201810374A publication Critical patent/TW201810374A/zh
Application granted granted Critical
Publication of TWI677902B publication Critical patent/TWI677902B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052—Wet cleaning only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemically Coating (AREA)
  • Drying Of Semiconductors (AREA)
TW106109563A 2016-03-31 2017-03-22 硬遮罩之形成方法、硬遮罩之形成裝置及記憶媒體 TWI677902B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2016071472 2016-03-31
JP2016-071472 2016-03-31
JP2016-198426 2016-10-06
JP2016198426A JP6762831B2 (ja) 2016-03-31 2016-10-06 ハードマスクの形成方法、ハードマスクの形成装置及び記憶媒体

Publications (2)

Publication Number Publication Date
TW201810374A TW201810374A (zh) 2018-03-16
TWI677902B true TWI677902B (zh) 2019-11-21

Family

ID=60045806

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106109563A TWI677902B (zh) 2016-03-31 2017-03-22 硬遮罩之形成方法、硬遮罩之形成裝置及記憶媒體

Country Status (3)

Country Link
JP (1) JP6762831B2 (ja)
KR (1) KR102286317B1 (ja)
TW (1) TWI677902B (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI752186B (zh) * 2017-03-23 2022-01-11 日商東京威力科創股份有限公司 鍍膜處理方法、鍍膜處理裝置及記憶媒體
KR20200096577A (ko) * 2017-12-06 2020-08-12 도쿄엘렉트론가부시키가이샤 도금 처리 방법, 도금 처리 장치 및 기억 매체

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020074664A1 (en) * 2000-07-26 2002-06-20 Takeshi Nogami Semiconductor device and manufacturing method thereof
US20050282378A1 (en) * 2004-06-22 2005-12-22 Akira Fukunaga Interconnects forming method and interconnects forming apparatus

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005015885A (ja) * 2003-06-27 2005-01-20 Ebara Corp 基板処理方法及び装置
JP2008294335A (ja) * 2007-05-28 2008-12-04 Panasonic Corp 半導体装置の製造方法
JP4547016B2 (ja) * 2008-04-04 2010-09-22 東京エレクトロン株式会社 半導体製造装置、半導体製造方法
US9257142B2 (en) * 2008-10-14 2016-02-09 Asahi Kasei E-Materials Corporation Heat-reactive resist material, layered product for thermal lithography using the material, and method of manufacturing a mold using the material and layered product
JP5877705B2 (ja) * 2011-12-27 2016-03-08 旭化成イーマテリアルズ株式会社 微細パターン構造体の製造方法
US8956975B2 (en) * 2013-02-28 2015-02-17 International Business Machines Corporation Electroless plated material formed directly on metal
KR102306612B1 (ko) * 2014-01-31 2021-09-29 램 리써치 코포레이션 진공-통합된 하드마스크 프로세스 및 장치

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020074664A1 (en) * 2000-07-26 2002-06-20 Takeshi Nogami Semiconductor device and manufacturing method thereof
US20050282378A1 (en) * 2004-06-22 2005-12-22 Akira Fukunaga Interconnects forming method and interconnects forming apparatus

Also Published As

Publication number Publication date
TW201810374A (zh) 2018-03-16
KR102286317B1 (ko) 2021-08-05
JP6762831B2 (ja) 2020-09-30
JP2017188644A (ja) 2017-10-12
KR20170113370A (ko) 2017-10-12

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