TWI671868B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

Info

Publication number
TWI671868B
TWI671868B TW105112228A TW105112228A TWI671868B TW I671868 B TWI671868 B TW I671868B TW 105112228 A TW105112228 A TW 105112228A TW 105112228 A TW105112228 A TW 105112228A TW I671868 B TWI671868 B TW I671868B
Authority
TW
Taiwan
Prior art keywords
package
semiconductor device
transparent
cover
transparent portion
Prior art date
Application number
TW105112228A
Other languages
English (en)
Other versions
TW201709436A (zh
Inventor
細見剛
Original Assignee
日商三菱電機股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商三菱電機股份有限公司 filed Critical 日商三菱電機股份有限公司
Publication of TW201709436A publication Critical patent/TW201709436A/zh
Application granted granted Critical
Publication of TWI671868B publication Critical patent/TWI671868B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/06Containers; Seals characterised by the material of the container or its electrical properties
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/544Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54426Marks applied to semiconductor devices or parts for alignment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54433Marks applied to semiconductor devices or parts containing identification or tracking information
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54473Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486Located on package parts, e.g. encapsulation, leads, package substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6644Packaging aspects of high-frequency amplifiers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6683High-frequency adaptations for monolithic microwave integrated circuit [MMIC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85401Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/85411Tin (Sn) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85439Silver (Ag) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Light Receiving Elements (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Led Device Packages (AREA)

Abstract

獲得一種可在封裝體封裝後一邊觀察內部,一邊輕易辨識封裝體外觀的半導體裝置。
半導體裝置係包括:具有電子零件3的半導體晶片2;及將半導體晶片2進行封裝的封裝體1。封裝體1係具有相對可見光為不透明且相對近紅外光或近紫外光為透明的透明部5。透明部5係被配置在電子零件3可由外部藉由近紅外光或近紫外光進行觀察的位置。

Description

半導體裝置
本發明係關於可在封裝體封裝後一邊觀察內部,一邊輕易辨識封裝體外觀的半導體裝置。
將電晶體、二極體或IC等半導體晶片收納在由金屬、陶瓷或樹脂等所構成的封裝體內的半導體裝置係逐漸被使用在各種電子機器。在該半導體裝置中,若異物混入至封裝體內部,在出貨前的電特性檢查中即使未發現異常,亦會有在出貨後使用期間因異物變形或部分成分使半導體晶片劣化,因此在半導體裝置的電特性引起異常的情形。因此,在組裝時,藉由光學顯微鏡觀察封裝體內及半導體晶片上,以檢查異物混入。但是,有在由封裝體內部之異物檢查後至封裝為止的期間混入異物的情形,在封裝後的電特性檢查時點,無法檢測出對電特性未造成異常的異物混入品。相對於此,提出一種使用可輕易視認經封裝的IC的透明封裝體的半導體裝置(參照例如專利文獻1)。
【先前技術文獻】
【專利文獻】
【專利文獻1】日本特開2002-881號公報
在封裝體上係被印上表示電極方向、製品名及製造編號等的標記。但是,若使用相對可見光為透明的封裝體時,被印在封裝體上的標記、及可看透封裝體的內部構造相重疊,難以讀取標記。此外,以外觀檢查,難以檢測封裝體表面的損傷。
本發明係用以解決如上所述之課題而完成者,其目的在獲得一種可在封裝體封裝後一邊觀察內部,一邊輕易辨識封裝體外觀的半導體裝置者。
本發明之半導體裝置包括:具有電子零件的半導體晶片;及將前述半導體晶片進行封裝的封裝體,其特徵為:前述封裝體係具有相對可見光為不透明且相對近紅外光或近紫外光為透明的透明部,前述透明部係被配置在前述電子零件可由外部藉由前述近紅外光或前述近紫外光進行觀察的位置。
在本發明中,封裝體的透明部係相對可見光為不透明,因此可輕易辨識封裝體外觀。此外,透明部相對近紅外光或近紫外光為透明,因此在封裝體封裝後,可藉由近紅外光或近紫外光來觀察內部。
1‧‧‧封裝體
2‧‧‧半導體晶片
3‧‧‧電子零件
4‧‧‧封裝體本體
5‧‧‧遮蓋(透明部)
6‧‧‧封裝體主材
7‧‧‧電氣配線
8‧‧‧晶粒接合材
9‧‧‧金屬細線
10‧‧‧接著劑
11‧‧‧標記
12‧‧‧基材
13‧‧‧透明導電膜
14‧‧‧可見光吸收材的膜
15‧‧‧封裝樹脂(透明部)
第1圖係顯示本發明之實施形態1之半導體裝置的剖面圖。
第2圖係顯示本發明之實施形態1之遮蓋的剖面圖。
第3圖係顯示本發明之實施形態2之半導體裝置的剖面圖。
參照圖示,說明本發明之實施形態之半導體裝置。對於相同或對應的構成要素係有標註相同符號且省略反覆說明的情形。
實施形態1.
第1圖係顯示本發明之實施形態1之半導體裝置的剖面圖。該半導體裝置亦非為受光元件及發光元件的任一者,而是例如微波通訊用高頻訊號放大元件、切換元件、振盪器、及MMIC(Monolithic Microwave Integrated Circuit,單晶微波積體電路)等。因此,以一般的元件的功能而言,並不需要透明的封裝體。
封裝體1封裝半導體晶片2。在半導體晶片2的上面係形成有電晶體、二極體或電路等電子零件3。封裝體1係具有:封裝體本體4、及遮蓋(cap)5。
封裝體本體4係具有:陶瓷或樹脂等封裝體主材6、及電氣配線7。半導體晶片2的背面藉由銀膠、金錫焊料或環氧樹脂等晶粒接合材8被固定在封裝體本體4。電氣配線7係在銅、鐵或鎳等合金鍍敷金、銀或錫等者,具有:封裝體內部的焊墊部、及被引出至封裝體外部的電極部。半導體晶片2的電子零件3與封裝體1的電氣配線7的焊墊部以金合金或銅合金等金屬細線9相連接。其中,在封裝體1內亦可收納電阻或電容器等半導體晶片2以外的電子零件。
遮蓋5係藉由環氧樹脂等接著劑10被固定在封裝體本體4,以覆蓋封裝體本體4的主面(第1圖中為上面)全體的方式構成。遮蓋5係相對可見光波長(380nm~780nm)為不透明且相對近紅外光(波長800nm~2500nm)或近紫外光 (波長200nm~380nm)為透明的透明部。因此,可透過遮蓋5,由封裝體1的外側觀察封裝體1內的半導體晶片2的電子零件3。在本實施形態中,覆蓋封裝體本體4的上面的遮蓋5全體構成為透明部,藉此半導體裝置的上面全體形成為透明部。其中,遮蓋5並不一定必須覆蓋半導體裝置的上面全體,亦可以封裝體本體4的外形大而以遮蓋5覆蓋封裝體本體4的上面的一部分的方式構成。此外,遮蓋5不僅封裝體本體4的上面,亦可覆蓋側面,亦可覆蓋上面及側面之雙方。
遮蓋5係將例如使用有機色素或無機顏料等吸收可見光的可見光吸收材,混合在透明的環氧樹脂或含氟化聚醯亞胺等透明基材而使其硬化來製作。
對經封裝的半導體裝置使用近紅外光的光源(例如波長890nm的紅外線LED)作為照明,以紅外線攝影機觀察而進行異物檢查之後,在遮蓋5上印上表示電極方向、製品名稱或製造編號等的標記11。
在本實施形態中,封裝體1的遮蓋5相對可見光為不透明,因此可藉由目視或可見光的畫像辨識,輕易地辨識標記11或損傷等封裝體1的外觀。此外,遮蓋5係相對近紅外光或近紫外光為透明,因此在封裝體1封裝後,可藉由近紅外光或近紫外光來觀察內部。因此,可進行封裝後的半導體裝置內部的異物檢查。此外,不僅異物檢查,亦可進行半導體晶片2是否位置偏移或破裂、配線是否彎曲等檢查。
第2圖係顯示本發明之實施形態1之遮蓋的剖面圖。遮蓋5係具有:透明樹脂或玻璃的基材12;以蒸鍍或濺鍍 被形成在其下面的氧化銦錫或氧化鋅等透明導電膜13;及被塗覆在基材12的上面的可見光吸收材的膜14。藉由透明導電膜13,欲由外部侵入至半導體裝置內的微波或毫米波等電磁波被屏蔽。因此,可抑制外來的電磁波侵入至半導體裝置而對動作造成影響的情形,可減低例如輸出訊號的雜音。
此外,以將遮蓋5固定在封裝體本體4的接著劑10而言,可使用以遮蓋5顯示透明性之紫外線予以硬化的紫外線硬化樹脂。此時,在封裝體本體4上放置紫外線硬化樹脂及遮蓋5後,由遮蓋5上方照射紫外線而使紫外線硬化樹脂硬化且固定遮蓋5。藉此,無須進行加熱,即可固定遮蓋5。因此,與使用熱硬化樹脂的情形相比,可以低溫且短時間使封裝完成。因此,可使用不耐熱的材料,亦可刪減製造工序的能量消耗。
紫外線硬化樹脂一般由單體、寡聚物或光聚合起始劑及其他添加劑所構成。若被照射光,光聚合起始劑發生離子,該離子與單體或寡聚物聚合,一般而言,與熱硬化樹脂相比,以低溫且短時間硬化。在紫外線硬化樹脂係有:丙烯酸系樹脂、環氧系樹脂或矽氧系樹脂等等,可輕易由市場(ThreeBond製、日立化成製、其他等)取得。其中,以接著劑10而言,不限於紫外線硬化樹脂,可使用以遮蓋5顯示透明性之近紅外光或近紫外光予以硬化的光硬化接著劑。
此外,亦可將半導體晶片2的側方的封裝體本體4形成為透明部。此時係由側方觀察封裝體1內部,藉此除了異物檢查之外,可檢測將半導體晶片2與封裝體1的電氣配線7相連接的金屬細線9的高度方向的形狀、或半導體晶片2的傾 斜。或者,亦將半導體晶片2的下方的封裝體本體4形成為透明部。此時係可檢查在以晶粒接合材8所固定的半導體晶片2的背面是否夾著異物。亦即,透明部若以可由外部觀察檢查對象的電子零件的方式進行配置即可,較佳為將半導體裝置的上面、下面、或側面的至少任一個的面全體構成為透明部、或將遮蓋5全體構成為透明部。
此外,遮蓋5亦可在透明的樹脂或玻璃的基材表面,以塗佈等塗覆可見光吸收材來製作。此外,亦可由市場(HOYA製、SIGMA光機製、其他)取得可見光非透過濾波器而適用在遮蓋5。
此外,以在近紅外光的波長為透明的遮蓋5的材料而言,亦可使用具有以1μm以下的波長為不透明且以1.2~6μm的波長為透明的特性的單晶矽。此時,可在異物檢查的光源,使用波長1300~1600nm的紅外線LED等來檢查封裝體1內。
實施形態2.
第3圖係顯示本發明之實施形態2之半導體裝置的剖面圖。本實施形態的封裝體1係以封裝樹脂15,藉由模塑成形,覆蓋且固定半導體晶片2、電氣配線7及金屬細線9者。封裝樹脂15係將可見光吸收材及透明樹脂加以混合者,為相對可見光為不透明且相對近紅外光或近紫外光為透明的透明部。以該構成亦可得與實施形態1相同的效果。

Claims (4)

  1. 一種半導體裝置,包括:半導體晶片,具有電子零件,前述電子零件包含電晶體或電路;及封裝體,將前述半導體晶片進行封裝,其特徵為:前述封裝體係具有相對可見光為不透明且相對近紅外光或近紫外光為透明的透明部,前述透明部為具有基材、透明導電膜及可見光吸收材的膜的遮蓋,前述透明部係被配置在檢查對象的前述電子零件可由外部藉由前述近紅外光或前述近紫外光進行觀察的位置,前述半導體裝置不進行光訊號的輸入及輸出而動作,為微波通訊用高頻訊號放大元件、切換元件、振盪器、及MMIC的任一者。
  2. 如申請專利範圍第1項之半導體裝置,其中,在前述透明部印有標記。
  3. 如申請專利範圍第1或2項之半導體裝置,其中,前述透明部的至少一部分具有導電性。
  4. 如申請專利範圍第1或2項之半導體裝置,其中,前述封裝體係具有:封裝體本體;及覆蓋前述封裝體本體的至少上面的一部分且為前述透明部的遮蓋,前述遮蓋係藉由以前述遮蓋顯示透明性之前述近紅外光或前述近紫外光予以硬化的光硬化接著劑,被固定在前述封裝體本體。
TW105112228A 2015-08-20 2016-04-20 半導體裝置 TWI671868B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015-163055 2015-08-20
JP2015163055A JP6477355B2 (ja) 2015-08-20 2015-08-20 半導体装置

Publications (2)

Publication Number Publication Date
TW201709436A TW201709436A (zh) 2017-03-01
TWI671868B true TWI671868B (zh) 2019-09-11

Family

ID=58157817

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105112228A TWI671868B (zh) 2015-08-20 2016-04-20 半導體裝置

Country Status (4)

Country Link
US (1) US9711460B2 (zh)
JP (1) JP6477355B2 (zh)
CN (1) CN106469686B (zh)
TW (1) TWI671868B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10535812B2 (en) * 2017-09-04 2020-01-14 Rohm Co., Ltd. Semiconductor device
JP7417029B2 (ja) 2018-12-14 2024-01-18 日亜化学工業株式会社 発光装置及びその製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130093037A1 (en) * 2010-06-24 2013-04-18 Panasonic Corporation Infared sensor
TW201318112A (zh) * 2011-08-30 2013-05-01 Qualcomm Mems Technologies Inc 以玻璃作為基板材料以及用於微機電系統及積體電路裝置之最終封裝

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61162515A (ja) * 1985-01-11 1986-07-23 Nec Corp 樹脂組成物及びそれを用いた樹脂封止型半導体装置
JP3035021B2 (ja) * 1991-08-29 2000-04-17 株式会社リコー 液晶表示素子およびその製造方法
JP2000157702A (ja) 1998-11-24 2000-06-13 Sanyo Bussan:Kk 遊技機制御用icパッケージ
JP2000254318A (ja) 1999-03-05 2000-09-19 Sankyo Kk 遊技機
JP2002000881A (ja) 2000-06-26 2002-01-08 Toyomaru Industry Co Ltd 遊技機
TW480684B (en) 2001-04-13 2002-03-21 Taiwan Electronic Packaging Co Package of IC chip
US7807972B2 (en) * 2005-01-26 2010-10-05 Analog Devices, Inc. Radiation sensor with cap and optical elements
JP2007234763A (ja) * 2006-02-28 2007-09-13 Sharp Corp 半導体装置およびその製造方法
US20130293482A1 (en) * 2012-05-04 2013-11-07 Qualcomm Mems Technologies, Inc. Transparent through-glass via
US9161449B2 (en) * 2013-10-29 2015-10-13 Lite-On Technology Corporation Image sensor module having flat material between circuit board and image sensing chip

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130093037A1 (en) * 2010-06-24 2013-04-18 Panasonic Corporation Infared sensor
TW201318112A (zh) * 2011-08-30 2013-05-01 Qualcomm Mems Technologies Inc 以玻璃作為基板材料以及用於微機電系統及積體電路裝置之最終封裝

Also Published As

Publication number Publication date
US9711460B2 (en) 2017-07-18
CN106469686A (zh) 2017-03-01
JP2017041561A (ja) 2017-02-23
US20170053877A1 (en) 2017-02-23
CN106469686B (zh) 2019-05-14
TW201709436A (zh) 2017-03-01
JP6477355B2 (ja) 2019-03-06

Similar Documents

Publication Publication Date Title
JP5635661B1 (ja) イメージセンサの2段階封止方法
US8946664B2 (en) Optical sensor device having wiring pattern within cavity housing optical sensor element
US20110024627A1 (en) Proximity Sensor with Ceramic Housing and Light Barrier
US10714454B2 (en) Stack packaging structure for an image sensor
US10461066B2 (en) Structure and method for hybrid optical package with glass top cover
US20190081028A1 (en) Optical module, module, and methods for manufacturing optical module and module
TWI671868B (zh) 半導體裝置
JP2013077701A (ja) 電子部品および電子機器ならびにこれらの製造方法。
TW201340300A (zh) 光感測器裝置及其製造方法
CN111863843A (zh) 感测器封装结构及其感测模块
TW201820570A (zh) 具有發光功能的指紋辨識模組及其製造方法
KR20170073796A (ko) 반도체 패키지 및 패키지 제조 방법
TW202107647A (zh) 封裝元件
US10396111B2 (en) Package for an optical sensor, optical sensor arrangement and method of producing a package for an optical sensor
JP2015060869A (ja) 光結合装置
TWM449351U (zh) 感測器封裝模組
US10600835B2 (en) Electronic module and method of manufacturing the same
US20210013375A1 (en) Semiconductor device package and method of manufacturing the same
TWI528512B (zh) Chip package structure and process
KR102195081B1 (ko) 지문인식 센서 패키지
EP4318589A1 (en) Semiconductor package and method for making semiconductor package
TWM486862U (zh) 光電元件之封裝體
KR100729007B1 (ko) 접촉 이미지 캡쳐 구조
JP2006229056A (ja) 半導体装置の製造方法
JP5908627B2 (ja) 光センサ装置