CN111863843A - 感测器封装结构及其感测模块 - Google Patents

感测器封装结构及其感测模块 Download PDF

Info

Publication number
CN111863843A
CN111863843A CN201910617401.4A CN201910617401A CN111863843A CN 111863843 A CN111863843 A CN 111863843A CN 201910617401 A CN201910617401 A CN 201910617401A CN 111863843 A CN111863843 A CN 111863843A
Authority
CN
China
Prior art keywords
layer
light
sensing
outer edge
distance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910617401.4A
Other languages
English (en)
Other versions
CN111863843B (zh
Inventor
洪立群
李建成
陈建儒
彭镇滨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tong Hsing Electronic Industries Ltd
Original Assignee
Kingpak Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kingpak Technology Inc filed Critical Kingpak Technology Inc
Publication of CN111863843A publication Critical patent/CN111863843A/zh
Application granted granted Critical
Publication of CN111863843B publication Critical patent/CN111863843B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H01L27/14623—Optical shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2902—Disposition
    • H01L2224/29034—Disposition the layer connector covering only portions of the surface to be connected
    • H01L2224/29035—Disposition the layer connector covering only portions of the surface to be connected covering only the peripheral area of the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Light Receiving Elements (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Photometry And Measurement Of Optical Pulse Characteristics (AREA)

Abstract

本发明公开一种感测器封装结构及其感测模块，所述感测器封装结构包含基板、设置于基板上的感测芯片、设置于感测芯片上的光固化层、通过光固化层而设置于感测芯片上方的透光层、及设置于透光层表面上的遮蔽层。光固化层包含有分别位于相反两侧的内侧缘与外侧缘，并且内侧缘与外侧缘相隔有一第一距离。于平行所述感测芯片的顶面的一横向方向上，所述光固化层的外侧缘与所述遮蔽层的外边缘之间相隔有一第二距离，并且所述第二距离介于所述第一距离的1/2～1/3。据此，所述感测器封装结构能通过在特定位置形成遮蔽层，以降低眩光现象并有效地固化光固化层。

Description

感测器封装结构及其感测模块
技术领域
本发明涉及一种封装结构，尤其涉及一种感测器封装结构及其感测模块。
背景技术
现有的感测器封装结构是将玻璃板通过胶层而设置于感测芯片上，并且所述胶层是围绕在所述感测芯片的感测区外围。然而，由于穿过所述玻璃板的光线有可能部分会被所述胶层所反射，因而对所述感测芯片的所述感测区会造成影响(如：眩光现象)。
于是，本发明人认为上述缺陷可改善，乃特潜心研究并配合科学原理的运用，终于提出一种设计合理且有效改善上述缺陷的本发明。
发明内容
本发明实施例在于提供一种感测器封装结构及其感测模块，其能有效地改善现有的感测器封装结构的眩光问题。
本发明实施例公开一种感测器封装结构，包括：一基板；一感测芯片，设置于所述基板上，并且所述感测芯片的一顶面包含有一感测区及围绕于所述感测区的一承载区；一光固化层，呈环形且设置于所述承载区上，并且所述光固化层包含有分别位于相反两侧的一内侧缘与一外侧缘，所述内侧缘与所述外侧缘相隔有一第一距离；一透光层，通过所述光固化层而设置于所述感测芯片的上方，以使所述透光层、所述光固化层、及所述感测芯片共同包围形成有一封闭空间；其中，所述感测区面向所述透光层；一遮蔽层，设置于所述透光层的表面上，并且所述遮蔽层具有一外边缘；其中，于平行所述感测芯片的所述顶面的一横向方向上，所述光固化层的所述外侧缘与所述遮蔽层的所述外边缘之间相隔有一第二距离，并且所述第二距离介于所述第一距离的1/2～1/3。
优选地，所述透光层包含有分别位于相反两侧的一第一表面与一第二表面，并且所述第二表面是面向所述感测区；所述遮蔽层设置于所述第二表面并且至少局部埋置于所述光固化层内。
优选地，所述遮蔽层包含有：一内埋部，埋置所述光固化层内，并且所述内埋部于所述横向方向上具有一宽度，而所述宽度为所述第一距离的1/2～2/3；一裸露部，位于所述封闭空间内，并且所述裸露部朝向所述感测芯片的所述顶面正投影所形成的一投影区域，其位在所述感测区与所述光固化层之间。
优选地，所述透光层包含有分别位于相反两侧的一第一表面与一第二表面，并且所述第二表面是面向所述感测区；所述遮蔽层设置于所述第一表面。
优选地，所述遮蔽层朝向所述感测芯片的所述顶面正投影所形成的一投影区域，其位在所述感测区的外侧。
优选地，所述透光层包含有一第一表面、位于所述第一表面相反侧的一第二表面、及相连于所述第一表面与所述第二表面的一外侧面，所述第二表面是面向所述感测区，而所述外侧面切齐于所述光固化层的所述外侧缘。
优选地，所述透光层包含有一第一表面、位于所述第一表面相反侧的一第二表面、及相连于所述第一表面与所述第二表面的一外侧面，所述第二表面是面向所述感测区，而所述光固化层的所述外侧缘自所述外侧面内缩一距离。
优选地，所述基板包含有位于所述感测芯片外侧的多个第一焊垫，所述感测芯片的所述顶面包含有位于所述承载区外侧的多个第二焊垫；所述感测器封装结构进一步包括：多条金属线，其一端分别连接于所述第一焊垫，而另一端连接于所述第二焊垫；一封装体，位于所述基板上；其中，所述感测芯片、所述光固化层、所述透光层、及所述金属线埋置于所述封装体内，并且所述透光层的局部外表面裸露于所述封装体外。
本发明实施例也公开一种感测器封装结构的感测模块，包括：一感测芯片，其顶面包含有一感测区及围绕于所述感测区的一承载区；一光固化层，呈环形且设置于所述承载区上，并且所述光固化层包含有分别位于相反两侧的一内侧缘与一外侧缘，所述内侧缘与所述外侧缘相隔有一第一距离；一透光层，通过所述光固化层而设置于所述感测芯片的上方，以使所述透光层、所述光固化层、及所述感测芯片共同包围形成有一封闭空间；其中，所述感测区面向所述透光层；一遮蔽层，设置于所述透光层的表面上，并且所述遮蔽层具有一外边缘；其中，于平行所述感测芯片的所述顶面的一横向方向上，所述光固化层的所述内侧缘与所述遮蔽层的所述外边缘之间相隔有一重叠距离，并且所述重叠距离介于所述第一距离的1/2～2/3。
本发明实施例另公开一种感测器封装结构的感测模块，包括：一感测芯片，其顶面包含有一感测区及围绕于所述感测区的一承载区；一光固化层，呈环形且设置于所述承载区上，并且所述光固化层包含有分别位于相反两侧的一内侧缘与一外侧缘，所述内侧缘与所述外侧缘相隔有一第一距离；一透光层，通过所述光固化层而设置于所述感测芯片的上方，以使所述透光层、所述光固化层、及所述感测芯片共同包围形成有一封闭空间；其中，所述透光层包含有一第一表面、位于所述第一表面相反侧的一第二表面、及相连于所述第一表面与所述第二表面的一外侧面，所述第二表面是面向所述感测区；一遮蔽层，设置于所述透光层，并且所述遮蔽层具有一外边缘；其中，于平行所述感测芯片的一横向方向上，所述透光层的所述外侧面与所述遮蔽层的所述外边缘之间相隔有一第二距离，并且所述第二距离介于所述第一距离的1/2～1/3。
综上所述，本发明实施例所公开的感测器封装结构及其感测模块，通过在特定位置(如：第二距离或重叠距离)形成遮蔽层，据以能够有效地降低因为所述光固化层反光而产生的眩光现象，并且同时使所述遮蔽层下方的光固化层部位能照射到足够的固化光线(如：紫外光线)，进而能够使光固化层被完全固化。
为能更进一步了解本发明的特征及技术内容，请参阅以下有关本发明的详细说明与附图，但是此等说明与附图仅用来说明本发明，而非对本发明的保护范围作任何的限制。
附图说明
图1为本发明实施例一的感测器封装结构的剖视示意图。
图2为图1的部位II的局部放大示意图。
图3为图2的变化态样示意图。
图4为本发明实施例二的感测器封装结构的剖视示意图。
图5为图4的部位V的局部放大示意图。
具体实施方式
请参阅图1至图4，其为本发明的实施例，需先说明的是，本实施例对应附图所提及的相关数量与外型，仅用来具体地说明本发明的实施方式，以便于了解本发明的内容，而非用来局限本发明的保护范围。
[实施例一]
请参阅图1至图3所示，其为本发明的实施例一。本实施例公开一种感测器封装结构100；也就是说，内部非为封装感测器的任何封装结构，其结构设计基础不同于本实施例所指的感测器封装结构100，所以两者之间并不适于进行对比。
如图1和图2所示，所述感测器封装结构100包含有一基板1、设置于所述基板1上的一感测芯片2、电性耦接所述感测芯片2与所述基板1的多条金属线3、设置于所述感测芯片2上的一光固化层4、通过所述光固化层4而设置于所述感测芯片2上方的一透光层5、设置于所述透光层5表面上的一遮蔽层6、及形成于所述基板1上的一封装体7。
其中，所述感测器封装结构100于本实施例中虽是以包含上述组件来做说明，但所述感测器封装结构100也可以依据设计需求而加以调整变化。举例来说，在本发明未绘示的其他实施例中，所述感测器封装结构100可以省略所述金属线3，并且所述感测芯片2通过覆晶方式固定于所述基板1上。再者，于本实施例中，所述感测芯片2、所述光固化层4、所述透光层5、及所述遮蔽层6可以合并定义为一感测模块，并且所述感测模块可以独立地应用或是搭配本实施例以外的其他组件使用。
需先说明的是，为便于说明本实施例感测器封装结构100，图1是以剖视图呈现，但可以理解的是，在图1所未呈现的感测器封装结构100的部位也会形成有相对应的构造。例如：图1仅呈现两条金属线3，但在图1所未呈现的感测器封装结构100的部位还包含其他条金属线3。以下将分别就本实施例感测器封装结构100的各个组件构造与连接关系作一说明。
所述基板1于本实施例中为呈正方形或矩形的一印刷电路板(printed circuitboard，PCB)，但本发明不受限于此。其中，所述基板1于其上表面的大致中央处设有一芯片固定区11，并且所述基板1于其上表面形成有位于所述芯片固定区11(或所述感测芯片2)外侧的多个第一焊垫12。所述第一焊垫12于本实施例中是大致排列呈环状，但本发明不限于此。举例来说，在本发明未绘示的其他实施例中，所述第一焊垫12也可以是在所述芯片固定区11的相反两侧分别排成两列。
此外，所述基板1也可以于其下表面设有多个焊接球(图未标示)，并且所述感测器封装结构100能通过所述焊接球而焊接固定于一电子构件上，据以使所述感测器封装结构100能电性连接所述电子构件。
所述感测芯片2于本实施例中是以一影像感测芯片来说明，但不以此为限。其中，所述感测芯片2是固定于所述基板1的芯片固定区11，也就是说，所述感测芯片2是位于所述第一焊垫12的内侧。再者，所述感测芯片2的一顶面20包含有一感测区21、围绕于所述感测区21(且呈环形)的一承载区22、及位于所述承载区22外侧的多个第二焊垫23。
其中，所述感测芯片2的所述第二焊垫23的数量及位置于本实施例中是分别对应于所述基板1的所述第一焊垫12的数量及位置。再者，所述金属线3的一端分别连接于所述第一焊垫12，并且所述金属线3的另一端分别连接于所述第二焊垫23，据以使所述基板1能通过所述金属线3而电性耦接于所述感测芯片2。
所述光固化层4呈环形且设置于所述感测芯片2的所述承载区22上；也就是说，所述光固化层4于本实施例中是设置于所述感测区21的外侧、并位于所述第二焊垫23的内侧，据以使所述光固化层4的高度可以无需受限于所述金属线3的高度，但本发明不受限于此。举例来说，在本发明未绘示的其他实施例中，所述光固化层4也可以是设置在所述承载区22上、并包覆所述第二焊垫23与每条金属线3的局部。
其中，所述光固化层4意指是通过光线(如：紫外光线)照射而固化的结构，所以并非通过光线固化的任何胶层则不同于本实施例所指的光固化层4。其中，所述光固化层4包含有分别位于相反两侧的一内侧缘41与一外侧缘42，并且所述内侧缘41与所述外侧缘42于平行所述感测芯片2的所述顶面20的一横向方向D上相隔有一第一距离D1。
所述透光层5于本实施例中是以呈透明状的一平板玻璃来说明，但本发明不受限于此。所述透光层5设置于所述光固化层4上，也就是说，所述光固化层4夹持于所述透光层5与所述感测芯片2之间。其中，所述透光层5、所述光固化层4、及所述感测芯片2共同包围形成有一封闭空间E，而所述感测区21位于所述封闭空间E内且面向所述透光层5。
再者，所述透光层5于本实施例中包含有一第一表面51、位于所述第一表面51相反侧的一第二表面52、及相连于所述第一表面51与所述第二表面52的一外侧面53。其中，所述第二表面52是面向所述感测区21，所述光固化层4的所述外侧缘42自所述透光层5的所述外侧面53内缩一距离，但本发明不受限于此。举例来说，如图3所示，所述透光层5的所述外侧面53也可以是切齐于所述光固化层4的所述外侧缘42。
所述遮蔽层6于本实施例中呈环形且不透光，并且所述遮蔽层6设置于所述透光层5的所述第二表面52上，而所述遮蔽层6的至少局部埋置于所述光固化层4内。其中，所述遮蔽层6朝向所述感测芯片2的所述顶面20正投影所形成的一投影区域，其位在所述感测区21的外侧，据以避免因为所述遮蔽层6的设置而影响到所述感测区21的感测精准度。
再者，所述遮蔽层6具有埋置于所述光固化层4内的一外边缘61；而于平行所述感测芯片2的所述顶面20的所述横向方向D上，所述光固化层4的所述外侧缘42与所述遮蔽层6的所述外边缘61之间相隔有一第二距离D2，并且所述第二距离D2介于所述第一距离D1的1/2～1/3。
据此，所述遮蔽层6的设置能够有效地降低因为所述光固化层4反光而产生的眩光现象，并且同时使所述遮蔽层6下方的所述光固化层4部位能照射到足够的固化光线(如：紫外光线)，进而能够使光固化层4被完全固化。也就是说，本实施例的感测器封装结构100能通过在特定位置形成遮蔽层6，以降低眩光现象并有效地固化光固化层4。
以上说明是以所述光固化层4的所述外侧缘42与所述遮蔽层6的所述外边缘61来共同定义所述遮蔽层6所在的特定位置(也就是，所述第二距离D2)，但本实施例不排除以其他方式定义所述遮蔽层6所在的特定位置。举例来说，于平行所述感测芯片2的所述横向方向D上，所述透光层5的所述外侧面53与所述遮蔽层6的所述外边缘61之间相隔有一第二距离D2a，并且所述第二距离D2a也大致是介于所述第一距离D1的1/2～1/3。
或者换个角度来看，于平行所述感测芯片2的所述横向方向D上，所述光固化层4的所述内侧缘41与所述遮蔽层6的所述外边缘61之间相隔有一重叠距离Do，并且所述重叠距离Do介于所述第一距离D1的1/2～2/3。进一步地说，所述遮蔽层6包含有埋置所述光固化层4内的一内埋部62以及相连于所述内埋部62且位于所述封闭空间E内的一裸露部63。
其中，所述遮蔽层6的所述外边缘61也就是远离所述裸露部63的所述内埋部62的边缘，并且所述内埋部62于所述横向方向D上具有一宽度W61(相当于所述重叠距离Do)，而所述宽度W61为所述第一距离D1的1/2～2/3。所述裸露部63朝向所述感测芯片2的所述顶面20正投影所形成的一投影区域，其位在所述感测区21与所述光固化层4之间，据以在不影响到所述感测区21的感测精准度的前提下，尽可能地降低眩光现象。
所述封装体7设置于所述基板1上并包覆所述感测芯片2的外侧缘、所述光固化层4的所述外侧缘42、及所述透光层5的外侧面53，而所述透光层5的局部外表面裸露于所述封装体7外；也就是说，所述感测模块埋置于所述封装体7内，并且所述透光层5的所述第一表面51裸露于所述封装体7外。再者，所述第一焊垫12、所述第二焊垫23、及所述金属线3皆完全埋置于所述封装体7内，但本发明不受限于此。
进一步地说，所述封装体7于本实施例中是以一液态封胶(liquid compound)来说明，但本发明不受限于此。举例来说，在本发明未绘示的其他实施例中，所述封装体7的液态封胶的顶面上进一步形成有一模制封胶(molding compound)；或者，所述封装体7也可以仅为一模制封胶。
[实施例二]
请参阅图4和图5所示，其为本发明的实施例二，由于本实施例类似于上述的实施例一，所以两个实施例的相同处则不再加以赘述(如：基板1、感测芯片2、金属线3、光固化层4、透光层5、及封装体7)，而本实施例相较于实施例一的差异大致说明如下：
于本实施例中，所述遮蔽层6a未埋置于所述光固化层4内，并且所述遮蔽层6a是设置于所述透光层5的所述第一表面51上。其中，所述遮蔽层6a朝向所述感测芯片2的所述顶面20正投影所形成的一投影区域，其较佳是位在所述感测区21的外侧。
再者，所述遮蔽层6a具有邻近所述透光层5外侧面53的一外边缘61；而于平行所述感测芯片2的所述顶面20的一横向方向D上，所述光固化层4的所述外侧缘42与所述遮蔽层6a的所述外边缘61之间相隔有一第二距离D2，并且所述第二距离D2介于所述第一距离D1的1/2～1/3。
据此，所述遮蔽层6a的设置能够有效地降低因为所述光固化层4而反光产生的眩光现象，并且同时使遮蔽层6a于方向H(如：高度方向)而遮蔽的所述光固化层4部位能照射到足够的固化光线(如：紫外光线)，进而能够使光固化层4被完全固化。
以上说明是以所述光固化层4的所述外侧缘42与所述遮蔽层6a的所述外边缘61来共同定义所述遮蔽层6a的特定位置(也就是，所述第二距离D2)，但本实施例不排除以其他方式定义所述遮蔽层6a所在的特定位置。举例来说，于平行所述感测芯片2的所述横向方向D上，所述透光层5的所述外侧面53与所述遮蔽层6a的所述外边缘61之间相隔有一第二距离D2a，并且所述第二距离D2a也大致是介于所述第一距离D1的1/2～1/3。
[本发明实施例的技术效果]
综上所述，本发明实施例所公开的感测器封装结构及其感测模块，通过在特定位置(如：第二距离或重叠距离)形成遮蔽层，据以能够有效地降低因为所述光固化层反光而产生的眩光现象，并且同时使所述遮蔽层下方的所述光固化层部位能照射到足够的的固化光线(如：紫外光线)，进而能够使光固化层被完全固化。
此外，本发明实施例所公开的感测器封装结构及其感测模块，还能通过其他结构上的限制，据以进一步地降低因为所述光固化层而产生的眩光现象。例如：所述裸露部朝向所述感测芯片的所述顶面正投影所形成的一投影区域，其位在所述感测区与所述光固化层之间。
以上所公开的内容仅为本发明的优选可行实施例，并非因此局限本发明的专利范围，所以凡是运用本发明说明书及图式内容所做的等效技术变化，均包含于本发明的专利范围内。

Claims (10)

1.一种感测器封装结构，其特征在于，所述感测器封装结构包括：
一基板；
一感测芯片，设置于所述基板上，并且所述感测芯片的一顶面包含有一感测区及围绕于所述感测区的一承载区；
一光固化层，呈环形且设置于所述承载区上，并且所述光固化层包含有分别位于相反两侧的一内侧缘与一外侧缘，所述内侧缘与所述外侧缘相隔有一第一距离；
一透光层，通过所述光固化层而设置于所述感测芯片的上方，以使所述透光层、所述光固化层、及所述感测芯片共同包围形成有一封闭空间；其中，所述感测区面向所述透光层；以及
一遮蔽层，设置于所述透光层的表面上，并且所述遮蔽层具有一外边缘；其中，于平行所述感测芯片的所述顶面的一横向方向上，所述光固化层的所述外侧缘与所述遮蔽层的所述外边缘之间相隔有一第二距离，并且所述第二距离介于所述第一距离的1/2～1/3。
2.依据权利要求1所述的感测器封装结构，其特征在于，所述透光层包含有分别位于相反两侧的一第一表面与一第二表面，并且所述第二表面是面向所述感测区；所述遮蔽层设置于所述第二表面并且至少局部埋置于所述光固化层内。
3.依据权利要求2所述的感测器封装结构，其特征在于，所述遮蔽层包含有：
一内埋部，埋置所述光固化层内，并且所述内埋部于所述横向方向上具有一宽度，而所述宽度为所述第一距离的1/2～2/3；及
一裸露部，位于所述封闭空间内，并且所述裸露部朝向所述感测芯片的所述顶面正投影所形成的一投影区域，其位在所述感测区与所述光固化层之间。
4.依据权利要求1所述的感测器封装结构，其特征在于，所述透光层包含有分别位于相反两侧的一第一表面与一第二表面，并且所述第二表面是面向所述感测区；所述遮蔽层设置于所述第一表面。
5.依据权利要求1所述的感测器封装结构，其特征在于，所述遮蔽层朝向所述感测芯片的所述顶面正投影所形成的一投影区域，其位在所述感测区的外侧。
6.依据权利要求1所述的感测器封装结构，其特征在于，所述透光层包含有一第一表面、位于所述第一表面相反侧的一第二表面、及相连于所述第一表面与所述第二表面的一外侧面，所述第二表面是面向所述感测区，而所述外侧面切齐于所述光固化层的所述外侧缘。
7.依据权利要求1所述的感测器封装结构，其特征在于，所述透光层包含有一第一表面、位于所述第一表面相反侧的一第二表面、及相连于所述第一表面与所述第二表面的一外侧面，所述第二表面是面向所述感测区，而所述光固化层的所述外侧缘自所述外侧面内缩一距离。
8.依据权利要求1所述的感测器封装结构，其特征在于，所述基板包含有位于所述感测芯片外侧的多个第一焊垫，所述感测芯片的所述顶面包含有位于所述承载区外侧的多个第二焊垫；所述感测器封装结构进一步包括：
多条金属线，其一端分别连接于所述第一焊垫，而另一端连接于所述第二焊垫；及
一封装体，位于所述基板上；其中，所述感测芯片、所述光固化层、所述透光层、及所述金属线埋置于所述封装体内，并且所述透光层的局部外表面裸露于所述封装体外。
9.一种感测器封装结构的感测模块，其特征在于，所述感测模块包括：
一感测芯片，其顶面包含有一感测区及围绕于所述感测区的一承载区；
一光固化层，呈环形且设置于所述承载区上，并且所述光固化层包含有分别位于相反两侧的一内侧缘与一外侧缘，所述内侧缘与所述外侧缘相隔有一第一距离；
一透光层，通过所述光固化层而设置于所述感测芯片的上方，以使所述透光层、所述光固化层、及所述感测芯片共同包围形成有一封闭空间；其中，所述感测区面向所述透光层；以及
一遮蔽层，设置于所述透光层的表面上，并且所述遮蔽层具有一外边缘；其中，于平行所述感测芯片的所述顶面的一横向方向上，所述光固化层的所述内侧缘与所述遮蔽层的所述外边缘之间相隔有一重叠距离，并且所述重叠距离介于所述第一距离的1/2～2/3。
10.一种感测器封装结构的感测模块，其特征在于，所述感测模块包括：
一感测芯片，其顶面包含有一感测区及围绕于所述感测区的一承载区；
一光固化层，呈环形且设置于所述承载区上，并且所述光固化层包含有分别位于相反两侧的一内侧缘与一外侧缘，所述内侧缘与所述外侧缘相隔有一第一距离；
一透光层，通过所述光固化层而设置于所述感测芯片的上方，以使所述透光层、所述光固化层、及所述感测芯片共同包围形成有一封闭空间；其中，所述透光层包含有一第一表面、位于所述第一表面相反侧的一第二表面、及相连于所述第一表面与所述第二表面的一外侧面，所述第二表面是面向所述感测区；以及
一遮蔽层，设置于所述透光层，并且所述遮蔽层具有一外边缘；其中，于平行所述感测芯片的一横向方向上，所述透光层的所述外侧面与所述遮蔽层的所述外边缘之间相隔有一第二距离，并且所述第二距离介于所述第一距离的1/2～1/3。
CN201910617401.4A 2019-04-30 2019-07-10 感测器封装结构及其感测模块 Active CN111863843B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201962840472P 2019-04-30 2019-04-30
US62/840,472 2019-04-30

Publications (2)

Publication Number Publication Date
CN111863843A true CN111863843A (zh) 2020-10-30
CN111863843B CN111863843B (zh) 2024-03-01

Family

ID=72602034

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910617401.4A Active CN111863843B (zh) 2019-04-30 2019-07-10 感测器封装结构及其感测模块

Country Status (3)

Country Link
US (1) US11133348B2 (zh)
CN (1) CN111863843B (zh)
TW (1) TWI697990B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI721815B (zh) * 2020-03-10 2021-03-11 勝麗國際股份有限公司 感測器封裝結構
KR20220060380A (ko) * 2020-11-04 2022-05-11 삼성전자주식회사 이미지 센서 패키지
TWI828192B (zh) * 2021-12-21 2024-01-01 同欣電子工業股份有限公司 感測器封裝結構
TWI807560B (zh) * 2021-12-28 2023-07-01 同欣電子工業股份有限公司 感測器封裝結構
TWI782857B (zh) * 2022-01-18 2022-11-01 勝麗國際股份有限公司 感測器封裝結構
TWI829446B (zh) * 2022-06-06 2024-01-11 同欣電子工業股份有限公司 感測器封裝結構及晶片級感測器封裝結構

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110156074A1 (en) * 2009-12-31 2011-06-30 Tsang-Yu Liu Chip package and method for fabricating the same
US20120211852A1 (en) * 2011-02-18 2012-08-23 Sony Corporation Solid-state imaging apparatus
US20180012919A1 (en) * 2016-07-06 2018-01-11 Kingpak Technology Inc. Sensor package structure
CN107591420A (zh) * 2016-07-06 2018-01-16 胜丽国际股份有限公司 感测器封装结构
US20180019274A1 (en) * 2016-07-12 2018-01-18 Kingpak Technology Inc. Sensor package structure

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101165527A (zh) * 2006-10-18 2008-04-23 鸿富锦精密工业（深圳）有限公司 便携式电子装置
TWI466278B (zh) * 2010-04-06 2014-12-21 Kingpak Tech Inc 晶圓級影像感測器構裝結構及其製造方法
JP5682185B2 (ja) * 2010-09-07 2015-03-11 ソニー株式会社 半導体パッケージおよび半導体パッケージの製造方法ならびに光学モジュール
US8500344B2 (en) * 2011-07-25 2013-08-06 Visera Technologies Co., Ltd. Compact camera module and method for fabricating the same
JP2013243340A (ja) * 2012-04-27 2013-12-05 Canon Inc 電子部品、実装部材、電子機器およびこれらの製造方法
US10109663B2 (en) * 2015-09-10 2018-10-23 Xintec Inc. Chip package and method for forming the same
WO2017117316A1 (en) * 2015-12-28 2017-07-06 Innosys, Inc. Personalized Lighting Systems
US10502935B2 (en) * 2017-03-03 2019-12-10 Ideal Industries Lighting Llc Image sensor modules and luminaires incorporating the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110156074A1 (en) * 2009-12-31 2011-06-30 Tsang-Yu Liu Chip package and method for fabricating the same
US20120211852A1 (en) * 2011-02-18 2012-08-23 Sony Corporation Solid-state imaging apparatus
US20180012919A1 (en) * 2016-07-06 2018-01-11 Kingpak Technology Inc. Sensor package structure
CN107591420A (zh) * 2016-07-06 2018-01-16 胜丽国际股份有限公司 感测器封装结构
CN107591374A (zh) * 2016-07-06 2018-01-16 胜丽国际股份有限公司 感测器封装结构
US20180019274A1 (en) * 2016-07-12 2018-01-18 Kingpak Technology Inc. Sensor package structure

Also Published As

Publication number Publication date
US20200350357A1 (en) 2020-11-05
TWI697990B (zh) 2020-07-01
US11133348B2 (en) 2021-09-28
CN111863843B (zh) 2024-03-01
TW202042354A (zh) 2020-11-16

Similar Documents

Publication Publication Date Title
CN111863843A (zh) 感测器封装结构及其感测模块
US7560744B2 (en) Package optical chip with conductive pillars
US9231017B2 (en) Manufacturing method of semiconductor device
JP6530479B2 (ja) センサパッケージ構造
EP1351319A2 (en) Package for optical semiconductor
US20060121184A1 (en) Photocurable-resin application method and bonding method
CN115514863B (zh) 无焊接式感测镜头
US20170082466A1 (en) Electronic Module, Method and Device for Manufacturing an Electronic Module
KR20170073796A (ko) 반도체 패키지 및 패키지 제조 방법
US10700111B2 (en) Optical sensor
TWI782830B (zh) 感測器封裝結構
KR101413596B1 (ko) 발광장치 및 이를 구비하는 백라이트 유닛
TWM628856U (zh) 光學感測器封裝組件
CN110957334B (zh) 感测器封装结构
US20240047491A1 (en) Sensor package structure
CN116504795A (zh) 感测器封装结构
KR20160056663A (ko) 광학 센서 패키지
US20230197744A1 (en) Sensor package structure
CN115514864B (zh) 无焊接式感测镜头
TWI808691B (zh) 光學感測器封裝組件
CN117199088A (zh) 感测镜头
JP3100560U (ja) 映像センサーのフリップチップパッケージ構造とその映像センサーモジュール
US20240234166A9 (en) Chip package structure and method for producing the same
CN110518027B (zh) 感测器封装结构
US20230395634A1 (en) Sensor package structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20230119

Address after: Taipei City, Taiwan Chinese Zhongzheng District Yanping Road No. 83 6 floor

Applicant after: TONG HSING ELECTRONIC INDUSTRIES, Ltd.

Address before: Hsinchu County

Applicant before: KINGPAK TECHNOLOGY Inc.

GR01 Patent grant
GR01 Patent grant
TG01 Patent term adjustment
TG01 Patent term adjustment