TWI653742B - 半導體裝置與其之製造方法 - Google Patents
半導體裝置與其之製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims description 40
- 239000010410 layer Substances 0.000 claims abstract description 207
- 239000011247 coating layer Substances 0.000 claims abstract description 72
- 230000004888 barrier function Effects 0.000 claims abstract description 61
- 125000006850 spacer group Chemical group 0.000 claims abstract description 60
- 239000000463 material Substances 0.000 claims abstract description 50
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000011248 coating agent Substances 0.000 claims abstract description 16
- 238000000576 coating method Methods 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims description 60
- 239000011241 protective layer Substances 0.000 claims description 35
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical group Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 15
- 229910002601 GaN Inorganic materials 0.000 claims description 12
- 230000003647 oxidation Effects 0.000 claims description 12
- 238000007254 oxidation reaction Methods 0.000 claims description 12
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical group [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims description 9
- 230000001590 oxidative effect Effects 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 5
- 230000000903 blocking effect Effects 0.000 claims 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 18
- 238000005229 chemical vapour deposition Methods 0.000 description 12
- 239000010931 gold Substances 0.000 description 12
- 239000010936 titanium Substances 0.000 description 12
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 230000005533 two-dimensional electron gas Effects 0.000 description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- 238000005566 electron beam evaporation Methods 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 229910052759 nickel Inorganic materials 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 5
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 238000001459 lithography Methods 0.000 description 4
- 238000004151 rapid thermal annealing Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000009844 basic oxygen steelmaking Methods 0.000 description 2
- 238000005253 cladding Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
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Abstract
一種半導體裝置包含基板、通道層、間隔層、阻障層與氧化披覆層。通道層置於基板上。間隔層置於通道層上。阻障層置於間隔層上。氧化披覆層置於阻障層上。氧化披覆層之材質為氮氧化物。
Description
本發明是有關於一種半導體裝置。
隨著半導體技術的不斷發展,矽基半導體的技術已非常成熟。然而隨著元件尺寸的不斷縮小,許多元件性能卻也面臨到一些來自材料本身所造成的瓶頸。許多下一世代的半導體元件技術也陸續提出,其中III-V 族半導體材料,尤其是氮基材料,例如氮化鎵,更因其具有特殊的自發極化效應、壓電極化效應與能形成二維電子氣(2DEG),具有高電子飽和速度與高崩潰電場,使得氮化鎵元件受到矚目,特別是常關型氮化鎵電晶體。
本發明之一實施方式提供一種半導體裝置,包含基板、通道層、間隔層、阻障層與氧化披覆層。通道層置於基板上。間隔層置於通道層上。阻障層置於間隔層上。氧化披覆層置於阻障層上。氧化披覆層之材質為氮氧化物。
在一或多個實施方式中,間隔層之厚度小於5奈米。
在一或多個實施方式中,間隔層之材質為氮化鋁。
在一或多個實施方式中,氧化披覆層之厚度小於5奈米。
在一或多個實施方式中,氧化披覆層之材質為氮氧化鋁。
在一或多個實施方式中,阻障層之材質為氮化鎵鋁(Alx
Ga(1-x)
N),且0.1≤x≤0.4。
在一或多個實施方式中,半導體裝置更包含源極、汲極與閘極。源極與汲極置於阻障層上。閘極至少置於氧化披覆層上與置於源極與汲極之間。
在一或多個實施方式中,半導體裝置更包含保護層,置於氧化披覆層上,且至少一部分之保護層置於氧化披覆層與閘極之間。
在一或多個實施方式中,間隔層具有氧化區域。氧化披覆層具有第一凹槽,且阻障層具有第二凹槽。第一凹槽與第二凹槽一併暴露至少一部分之氧化區域,且至少一部分之閘極置於第一凹槽與第二凹槽中。
在一或多個實施方式中,半導體裝置更包含保護層,共形地置於第一凹槽與第二凹槽中,且至少一部分之保護層置於閘極與間隔層之氧化區域之間。
本發明之另一實施方式提供一種半導體裝置之製造方法,包含形成通道層於基板上。形成間隔層於通道層上。形成阻障層於間隔層上。形成披覆層於阻障層上。氧化披覆層,以形成氧化披覆層於阻障層上。氧化披覆層之材質為氮氧化物。
在一或多個實施方式中,間隔層之材質為氮化鋁。
在一或多個實施方式中,氧化披覆層之材質為氮氧化鋁。
在一或多個實施方式中,阻障層之材質為氮化鎵鋁(Alx
Ga(1-x)
N),且0.1≤x≤0.4。
在一或多個實施方式中,披覆層使用一高溫氧化製程氧化,且該溫度高於700˚C。
在一或多個實施方式中,製造方法更包含形成源極與汲極於阻障層上。形成閘極於至少氧化披覆層上且於源極與汲極之間。
在一或多個實施方式中,製造方法更包含形成保護層於氧化披覆層上,且形成至少一部分之保護層於氧化披覆層與閘極之間。
在一或多個實施方式中,製造方法更包含形成第一凹槽於披覆層中以暴露出一部分之阻障層。藉由第一凹槽形成第二凹槽於阻障層中以暴露出一部分之間隔層。
在一或多個實施方式中,氧化披覆層包含一併氧化披覆層與部分之間隔層,以形成氧化披覆層與氧化區域於間隔層中。形成閘極包含更形成閘極於第一凹槽與第二凹槽中。
在一或多個實施方式中,製造方法更包含共形地形成保護層於第一凹槽與第二凹槽中,使得至少一部分之保護層置於閘極與間隔層之氧化區域之間。
本發明之再一實施方式提供一種半導體裝置之製造方法,包含形成通道層於基板上。形成間隔層於通道層上。形成阻障層於間隔層上。形成披覆層於阻障層上。藉由蝕刻披覆層以形成第一凹槽於披覆層中。藉由蝕刻阻障層以形成第二凹槽於阻障層中,以暴露一部分之間隔層。氧化披覆層與被暴露之間隔層,以形成氧化披覆層與氧化區域。氧化披覆層之材質為氮氧化物。
在一或多個實施方式中,間隔層之材質為氮化鋁。
在一或多個實施方式中,氧化披覆層之材質為氮氧化鋁。
在一或多個實施方式中,阻障層之材質為氮化鎵鋁(Alx
Ga(1-x)
N),且0.1≤x≤0.4。
在一或多個實施方式中,披覆層使用一高溫氧化製程氧化,且溫度高於700˚C。
在上述實施方式中,披覆層之缺陷可減少,因此披覆層之表面為平坦表面。更進一步地,氧化製程可將披覆層去極化,如此一來,氧化披覆層之缺陷可進一步地被減少。再加上,因氧化披覆層被去極化,因此其表面為平坦表面,成長於氧化披覆層上之其他層的品質也可被改善。
以下將以圖式揭露本發明的複數個實施方式,為明確說明起見,許多實務上的細節將在以下敘述中一併說明。然而,應瞭解到,這些實務上的細節不應用以限制本發明。也就是說,在本發明部分實施方式中,這些實務上的細節是非必要的。此外,為簡化圖式起見,一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。
第1A圖至第1E圖為本發明第一實施方式之半導體裝置於不同階段的製造流程剖面圖。如第1A圖所示,首先提供一基板110。接著,可選擇性地形成一緩衝層210於基板110上。在本實施方式中,基板110之材質可為藍寶石(Sapphire)、矽(Si)或碳化矽(SiC),而緩衝層210之材質可為氮化鋁(AlN)或其他合適之材質。之後,形成一通道層120於基板110上或上方。舉例而言,在第1A圖中,通道層120形成於基板110上方且形成於緩衝層210上。在本實施方式中,通道層120之材質可為氮化鎵(GaN),而形成通道層120之方法可為化學氣相沉積(chemical vapor deposition, CVD)法。
接著請參照第1B圖。形成一間隔層130於通道層120上。在本實施方式中,間隔層130之材質可為氮化鋁(AlN),間隔層130之厚度T1可小於5奈米,而形成間隔層130的方法可為金屬有機化學氣相沉積(metal organic chemical vapor deposition, MOCVD)法。
接著請參照第1C圖。之後,形成一阻障層140於間隔層130上。在本實施方式中,阻障層140之材質為氮化鎵鋁(Alx
Ga(1-x)
N),且0.1≤x≤0.4。阻障層140之厚度T2可小於40奈米,而形成阻障層140的方法可為金屬有機化學氣相沉積(metal organic chemical vapor deposition, MOCVD)法。
請參照第1D圖。形成一披覆層150於阻障層140上。在本實施方式中,披覆層150之材質可為氮化鋁(AlN),披覆層150之厚度T3可小於5奈米,而形成披覆層150之方法可為金屬有機化學氣相沉積(MOCVD)法。更進一步地,金屬有機化學氣相沉積法可為一高溫磊晶製程,以減少披覆層150之缺陷,改善披覆層150之品質。
接著,形成一犧牲層250於披覆層150上。在本實施方式中,犧牲層250之材質可為氮化鎵(GaN)。形成犧牲層250之方法可為化學氣相沉積(CVD)法。犧牲層250可避免形成原生氧化物。在其他的實施方式中,犧牲層250可被省略。
請參照第1E圖。之後,氧化第1D圖之披覆層150以形成一氧化披覆層155於阻障層140上,而第1D圖之犧牲層250可一併被氧化而成為氧化犧牲層(未繪示)。在本實施方式中,氧化披覆層155之材質可為氮氧化鋁(AlON),且氧化該披覆層150的方法可為高溫氧化製程,例如高溫氧氣轉爐製程或快速熱退火(RTA)製程,且該溫度高於700˚C。在其他的實施方式中,氧化該披覆層150的方法可為氧基電漿(oxygen-based plasma)製程或使用化學溶液(例如雙氧水(H2
O2
))。氧化犧牲層可藉由浸泡於稀釋的鹽酸中而去除。
從結構上來看,半導體裝置包含基板110、通道層120、間隔層130、阻障層140與氧化披覆層155。通道層120置於基板110上。間隔層130置於通道層120上。阻障層140置於間隔層130上。氧化披覆層155置於阻障層140上。氧化披覆層155之材質為氮氧化物,例如為氮氧化鋁。二維電子氣(two-dimensional electron gas, 2DEG)通道122存在於通道層120中並靠近間隔層130。在一或多個實施方式中,半導體裝置可更包含緩衝層210,置於基板110與通道層120之間。因披覆層150以高溫磊晶製程形成,因此披覆層150與形成於其上之界面的品質可被改善。
第2A圖與第2B圖為本發明第二實施方式之半導體裝置於不同階段的製造流程剖面圖。第二實施方式與第一實施方式的不同處在於源極160、汲極170與閘極180。請參照第2A圖。可先執行第1A圖至第1E圖之製造流程。因相關之製造細節與第一實施方式中相同,因此便不再贅述。接著,可形成一源極160與一汲極170於阻障層140上。舉例而言,可形成一第一導電層以覆蓋氧化披覆層155與被暴露之阻障層140。接著,可圖案化第一導電層以形成源極160與汲極170。在一或多個實施方式中,可在形成源極160與汲極170後執行退火製程。
在本實施方式中,源極160與汲極170之材質可為鈦(Ti)、鋁(Al)、鎳(Ni)、金(Au)或其任意組合。形成第一導電層的方法可為物理氣相沉積法(如濺鍍法)或電子束蒸鍍法,而第一導電層可以微影蝕刻法圖案化。退火製程的溫度可大約為800˚C,然而本發明不以此為限。
請參照第2B圖。形成一閘極180於氧化披覆層155上並置於源極160與汲極170之間。舉例而言,可形成一第二導電層以至少覆蓋氧化披覆層155。接著,圖案化第二導電層以形成閘極180。閘極180之材質可為鈦(Ti)、鋁(Al)、鎳(Ni)、金(Au)或其任意組合。第二導電層可以物理氣相沉積法(如濺鍍法)、或電子束蒸鍍法製成,而第二導電層可以微影蝕刻法圖案化。
從結構上來看,第二實施方式與第一實施方式的不同處在於源極160、汲極170與閘極180。源極160與汲極170分開置於阻障層140上。閘極180至少置於氧化披覆層155上且置於源極160與汲極170之間。
二維電子氣通道122存在於通道層120中並靠近間隔層130。源極160可藉由二維電子氣通道122而與汲極170電性連接。也就是說,本實施方式之半導體裝置為空乏型電晶體。至於第二實施方式之相關結構細節因與第一實施方式相同,因此便不再贅述。
第3A圖與第3B圖為本發明第三實施方式之半導體裝置於不同階段的製造流程剖面圖。第三實施方式與第二實施方式的不同處在於保護層190。請先參照第3A圖。可先執行第1A圖至第1E圖以及第2A圖之製造流程。因相關之製造細節與第二實施方式中相同,因此便不再贅述。接著,可形成保護層190於氧化披覆層155上。在本實施方式中,保護層190之材質可為氧化鋁(aluminum oxide, Al2
O3
)、氮化鋁(aluminum nitride, AlN)、氮化矽(silicon nitride, Si3
N4
)、二氧化矽(silicon oxide, SiO2
)、二氧化鉿(hafnium oxide, HfO2
)、或其任意組合。形成保護層190的方法可為化學氣相沉積法。
請參照第3B圖。形成一閘極180於氧化披覆層155上、於保護層190上與於源極160以及汲極170之間。舉例而言,可形成一第二導電層以至少覆蓋保護層190。接著,圖案化第二導電層以形成閘極180。閘極180之材質可為鈦(Ti)、鋁(Al)、鎳(Ni)、金(Au)或其任意組合。形成第二導電層的方法可為物理氣相沉積法(如濺鍍法)或電子束蒸鍍法,而第二導電層可以微影蝕刻法圖案化。
從結構上來看,第三實施方式與第二實施方式的不同處在於保護層190。在本實施方式中,保護層190置於氧化披覆層155上,且至少部分之保護層190置於氧化披覆層155與閘極180之間。保護層190保護其下之疊層。至於第三實施方式之相關結構細節因與第二實施方式相同,因此便不再贅述。
第4A圖與第4D圖為本發明第四實施方式之半導體裝置於不同階段的製造流程剖面圖。第四實施方式與第一實施方式的不同處在於源極160、汲極170、閘極180、第一凹槽156與第二凹槽142。請先參照第4A圖。先執行第1A圖至第1D圖之製造流程。因相關之製造細節與第一實施方式中相同,因此便不再贅述。接著,形成第一凹槽156於披覆層150中以暴露出一部分之阻障層140。形成第一凹槽156之方法可為微影與蝕刻法。在本實施方式中,因披覆層150之材質(例如氮化鋁)與阻障層140之材質(例如氮化鎵鋁(Alx
Ga(1-x)
N),且0.1≤x≤0.4)不同,因此阻障層140可作為蝕刻披覆層150時的蝕刻停止層。
接著,形成一第二凹槽142於阻障層140中以暴露一部分之間隔層130。可利用披覆層150作為遮罩以蝕刻第二凹槽142。在本實施方式中,因阻障層140之材質(例如氮化鎵鋁(Alx
Ga(1-x)
N),且0.1≤x≤0.4)與間隔層130之材質(例如氮化鋁)不同,因此間隔層130可作為蝕刻阻障層140時的蝕刻停止層。如此一來,間隔層130可防止通道層120被蝕刻,且通道層120的表面可避免蝕刻破壞,因此二維電子氣通道具有良好品質。
請參照第4B圖。一併氧化第4A圖之披覆層150以及部分之間隔層130以形成氧化披覆層155以及在間隔層130中之氧化部分132。換句話說,氧化披覆層155與氧化部分132之材質皆為氮氧化鋁(aluminum oxynitride, AlON)。氧化該披覆層150與部分之間隔層130的方法可為高溫氧化製程,例如高溫氧氣轉爐製程或快速熱退火(RTA)製程,且該溫度高於700˚C。在其他的實施方式中,氧化該披覆層150的方法可為氧基電漿(oxygen-based plasma)製程或化學溶液(例如雙氧水(H2
O2
))。
請參照第4C圖。形成一源極160與一汲極170於阻障層140上。在一或多個實施方式中,可於形成源極160與汲極170後執行一退火製程以於源極160與阻障層140之間以及汲極170與阻障層140之間形成歐姆接觸。
在本實施方式中,源極160與汲極170的材質可為鈦(Ti)、鋁(Al)、鎳(Ni)、金(Au)或其任意組合。形成源極160與汲極170的方法可為物理氣相沉積法(如濺鍍法)或電子束蒸鍍法,而源極160與汲極170可以微影蝕刻法圖案化。退火製程的溫度可大約為800˚C,然而本發明不以此為限。
請參照第4D圖。形成一閘極180於第一凹槽156與第二凹槽142且於氧化披覆層155上。舉例而言,可形成一導電層以填滿第一凹槽156與第二凹槽142且覆蓋氧化披覆層155。接著,圖案化導電層以形成閘極180。閘極180的材質可為鈦(Ti)、鋁(Al)、鎳(Ni)、金(Au)或其任意組合。形成導電層的方法可為物理氣相沉積法(如濺鍍法)或電子束蒸鍍法。
從結構上來看,第四實施方式與第一實施方式的不同處在於源極160、汲極170、閘極180、第一凹槽156與第二凹槽142。源極160與汲極170置於阻障層140上。氧化披覆層155具有第一凹槽156,且阻障層140具有第二凹槽142。間隔層130具有氧化部分132。第一凹槽156與第二凹槽142共同暴露出至少一部分之氧化部分132。閘極180至少置於氧化披覆層155上、於第一凹槽156與第二凹槽142中,且於源極160與汲極170之間。
二維電子氣通道122存在於通道層120中並靠近間隔層130。第一凹槽156與第二凹槽142下之二維電子氣通道122被切斷。也就是說,本實施方式之半導體裝置為增強型電晶體。至於第四實施方式之相關結構細節因與第一實施方式相同,因此便不再贅述。
第5A圖與第5B圖為本發明第五實施方式之半導體裝置於不同階段的製造流程剖面圖。第五實施方式與第四實施方式的不同處在於保護層190。請先參照第5A圖。先執行第1A圖至第1D圖以及第4A圖至第4C圖之製造流程。因相關之製造細節與第四實施方式中相同,因此便不再贅述。接著,共形地(conformally)形成保護層190於第一凹槽156與第二凹槽142中。在本實施方式中,保護層190之材質可為氧化鋁(aluminum oxide, Al2
O3
)、氮化鋁(aluminum nitride, AlN)、氮化矽(silicon nitride, Si3
N4
)、二氧化矽(silicon oxide, SiO2
)、二氧化鉿(hafnium oxide, HfO2
)、或其任意組合。形成保護層190的方法可為化學氣相沉積法。
請參照第5B圖。形成一閘極180於氧化披覆層155上、於保護層190上與於第一凹槽156與第二凹槽142中。舉例而言,可形成一導電層以至少覆蓋保護層190。接著,圖案化導電層以形成閘極180。閘極180之材質可為鈦(Ti)、鋁(Al)、鎳(Ni)、金(Au)或其任意組合。形成導電層的方法可為物理氣相沉積法(如濺鍍法)或電子束蒸鍍法。
從結構上來看,第五實施方式與第四實施方式的不同處在於保護層190。在本實施方式中,保護層190共形地置於第一凹槽156與第二凹槽142中,且至少部分之保護層190置於閘極180與間隔層130之氧化部分132之間。保護層190保護其下之疊層。至於第五實施方式之相關結構細節因與第四實施方式相同,因此便不再贅述。
雖然本發明已以實施方式揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
110‧‧‧基板
120‧‧‧通道層
122‧‧‧二維電子氣通道
130‧‧‧間隔層
132‧‧‧氧化部分
140‧‧‧阻障層
142‧‧‧第二凹槽
150‧‧‧披覆層
155‧‧‧氧化披覆層
156‧‧‧第一凹槽
160‧‧‧源極
170‧‧‧汲極
180‧‧‧閘極
190‧‧‧保護層
210‧‧‧緩衝層
250‧‧‧犧牲層
T1、T2、T3‧‧‧厚度
第1A圖至第1E圖為本發明第一實施方式之半導體裝置於不同階段的製造流程剖面圖。 第2A圖與第2B圖為本發明第二實施方式之半導體裝置於不同階段的製造流程剖面圖。 第3A圖與第3B圖為本發明第三實施方式之半導體裝置於不同階段的製造流程剖面圖。 第4A圖與第4D圖為本發明第四實施方式之半導體裝置於不同階段的製造流程剖面圖。 第5A圖與第5B圖為本發明第五實施方式之半導體裝置於不同階段的製造流程剖面圖。
Claims (22)
- 一種半導體裝置,包含:一基板;一通道層,置於該基板上;一間隔層,置於該通道層上;一阻障層,置於該間隔層上;一氧化披覆層,置於該阻障層上,其中該氧化披覆層之材質為氮氧化物;一源極與一汲極,置於該阻障層上;以及一閘極,至少置於該氧化披覆層上與置於該源極與該汲極之間,其中該間隔層具有一氧化區域,該氧化披覆層具有一第一凹槽,且該阻障層具有一第二凹槽,該第一凹槽與該第二凹槽一併暴露至少一部分之該氧化區域,且至少一部分之該閘極置於該第一凹槽與該第二凹槽中。
- 如請求項1所述之半導體裝置,其中該間隔層之厚度小於5奈米。
- 如請求項1所述之半導體裝置,其中該間隔層之材質為氮化鋁。
- 如請求項1所述之半導體裝置,其中該氧化披覆層之厚度小於5奈米。
- 如請求項1所述之半導體裝置,其中該氧化披覆層之材質為氮氧化鋁。
- 如請求項1所述之半導體裝置,其中該阻障層之材質為氮化鎵鋁(AlxGa(1-x)N),且0.1x0.4。
- 如請求項1所述之半導體裝置,更包含:一保護層,共形地置於該第一凹槽與該第二凹槽中,且至少一部分之該保護層置於該閘極與該間隔層之該氧化區域之間。
- 一種半導體裝置之製造方法,包含:形成一通道層於一基板上;形成一間隔層於該通道層上;形成一阻障層於該間隔層上;形成一披覆層於該阻障層上;以及氧化該披覆層,以形成一氧化披覆層於該阻障層上,其中該氧化披覆層之材質為氮氧化物。
- 如請求項8所述之製造方法,其中該間隔層之材質為氮化鋁。
- 如請求項8所述之製造方法,其中該氧化披覆層之材質為氮氧化鋁。
- 如請求項8所述之製造方法,其中該阻障層之材質為氮化鎵鋁(AlxGa(1-x)N),且0.1x0.4。
- 如請求項8所述之製造方法,其中該披覆層使用一高溫氧化製程氧化,且該溫度高於700℃。
- 如請求項8所述之製造方法,更包含:形成一源極與一汲極於該阻障層上;以及形成一閘極於至少該氧化披覆層上且於該源極與該汲極之間。
- 如請求項13所述之製造方法,更包含:形成一保護層於該氧化披覆層上,且形成至少一部分之該保護層於該氧化披覆層與該閘極之間。
- 如請求項13所述之製造方法,更包含:形成一第一凹槽於該披覆層中以暴露出一部分之該阻障層;以及藉由該第一凹槽形成一第二凹槽於該阻障層中以暴露出一部分之該間隔層。
- 如請求項15所述之製造方法,其中氧化該披覆層包含:一併氧化該披覆層與該部分之該間隔層,以形成該氧化披覆層與一氧化區域於該間隔層中;以及其中形成該閘極包含:更形成該閘極於該第一凹槽與該第二凹槽中。
- 如請求項13所述之製造方法,更包含:共形地形成一保護層於該第一凹槽與該第二凹槽中,使得至少一部分之該保護層置於該閘極與該間隔層之該氧化區域之間。
- 一種半導體裝置之製造方法,包含:形成一通道層於一基板上;形成一間隔層於該通道層上;形成一阻障層於該間隔層上;形成一披覆層於該阻障層上;藉由蝕刻該披覆層以形成一第一凹槽於該披覆層中;藉由蝕刻該阻障層以形成一第二凹槽於該阻障層中,以暴露一部分之該間隔層;以及氧化該披覆層與被暴露之該間隔層,以形成一氧化披覆層與一氧化區域,其中該氧化披覆層之材質為氮氧化物。
- 如請求項18所述之製造方法,其中該間隔層之材質為氮化鋁。
- 如請求項18所述之製造方法,其中該氧化披覆層之材質為氮氧化鋁。
- 如請求項18所述之製造方法,其中該阻障層之材質為氮化鎵鋁(AlxGa(1-x)N),且0.1x0.4。
- 如請求項18所述之製造方法,其中該披覆層使用一高溫氧化製程氧化,且該溫度高於700℃。
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