TW202115909A - 高電子遷移率電晶體及其製作方法 - Google Patents

高電子遷移率電晶體及其製作方法 Download PDF

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TW202115909A
TW202115909A TW108135419A TW108135419A TW202115909A TW 202115909 A TW202115909 A TW 202115909A TW 108135419 A TW108135419 A TW 108135419A TW 108135419 A TW108135419 A TW 108135419A TW 202115909 A TW202115909 A TW 202115909A
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barrier layer
layer
hard mask
type semiconductor
mobility transistor
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TWI801671B (zh
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張峻銘
黃哲弘
廖文榮
侯俊良
葉治東
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聯華電子股份有限公司
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Abstract

本發明揭露一種製作高電子遷移率電晶體(high electron mobility transistor, HEMT)的方法，其主要先形成一緩衝層於一基底上，形成一第一阻障層於該緩衝層上，形成一第二阻障層於該第一阻障層上，形成一第一硬遮罩於該第二阻障層上，去除該第一硬遮罩以及該第二阻障層以形成一凹槽，再形成一P型半導體層於該凹槽內。

Description

高電子遷移率電晶體及其製作方法
本發明是關於一種高電子遷移率電晶體及其製作方法。
以氮化鎵基材料(GaN-based materials)為基礎的高電子遷移率電晶體具有於電子、機械以及化學等特性上之眾多優點，例如寬能隙、高崩潰電壓、高電子遷移率、大彈性模數(elastic modulus)、高壓電與壓阻係數(high piezoelectric and piezoresistive coefficients)等與化學鈍性。上述優點使氮化鎵基材料可用於如高亮度發光二極體、功率開關元件、調節器、電池保護器、面板顯示驅動器、通訊元件等應用之元件的製作。
本發明一實施例揭露一種製作高電子遷移率電晶體(high electron mobility transistor, HEMT)的方法，其主要先形成一緩衝層於一基底上，形成一第一阻障層於該緩衝層上，形成一第二阻障層於該第一阻障層上，形成一第一硬遮罩於該第二阻障層上，去除該第一硬遮罩以及該第二阻障層以形成一凹槽，再形成一P型半導體層於該凹槽內。
本發明另一實施例揭露一種高電子遷移率電晶體(high electron mobility transistor, HEMT)，其主要包含一緩衝層設於一基底上；一第一阻障層設於該緩衝層上；一P型半導體層設於該第一阻障層上；一第二阻障層設於該P型半導體層兩側之該第一阻障層上；一閘極電極設於該P型半導體層上；以及一源極電極以及一汲極電極設於該閘極電極兩側之該阻障層上。
請參照第1圖至第5圖，第1圖至第5圖為本發明一實施例製作一高電子遷移率電晶體之方法示意圖。如第1圖所示，首先提供一基底12，例如一由矽、碳化矽或氧化鋁(或可稱藍寶石)所構成的基底，其中基底12可為單層基底、多層基底、梯度基底或上述之組合。依據本發明其他實施例基底12又可包含一矽覆絕緣(silicon-on-insulator, SOI)基底。
然後於基底12表面形成一緩衝層14。在一實施利中，緩衝層14包含III-V族半導體例如氮化鎵，其厚度可藉於0.5微米至10微米之間。在一實施利中，可利用分子束磊晶製程(molecular-beam epitaxy, MBE)、有機金屬氣相沉積(metal organic chemical vapor deposition, MOCVD)製程、化學氣相沉積(chemical vapor deposition, CVD)製程、氫化物氣相磊晶(hydride vapor phase epitaxy, HVPE)製程或上述組合於基底12上形成緩衝層14。
隨後可選擇性形成一金屬氮化層16於緩衝層14表面作為閘極介電層。在一實施例中，金屬氮化層16可包含例如但不侷限於氮化鋁，其中形成金屬氮化層16的方法可包含有機金屬氣相沉積(metal organic chemical vapor deposition, MOCVD)製程、化學氣相沉積(chemical vapor deposition, CVD)製程、氫化物氣相磊晶(hydride vapor phase epitaxy, HVPE)製程或上述組合。
接著依序形成一第一阻障層18與第二阻障層20於金屬氮化層16表面。在本實施例中第一阻障層18與第二阻障層20均較佳包含III-V族半導體例如氮化鋁鎵(Alx Ga1-x N)且兩者均較佳包含由磊晶成長製程所形成之磊晶層。在本實施例中，第一阻障層18與第二阻障層20較佳包含不同厚度，例如第一阻障層18厚度較佳小於第二阻障層20厚度。另外第一阻障層18與第二阻障層20較佳包含不同鋁濃度或更具體而言第一阻障層18之鋁濃度較佳小於第二阻障層20之鋁濃度。舉例來說，若第一阻障層18包含III-V族半導體例如氮化鋁鎵(Alx Ga1-x N)，其中0>x>1，x較佳介於5-15%。第二阻障層20若同樣包含III-V族半導體例如氮化鋁鎵(Alx Ga1-x N)，其中0>x>1，x較佳介於15-50%。
如同上述形成緩衝層14的方式，可利用分子束磊晶製程(molecular-beam epitaxy, MBE)、有機金屬氣相沉積(metal organic chemical vapor deposition, MOCVD)製程、化學氣相沉積(chemical vapor deposition, CVD)製程、氫化物氣相磊晶(hydride vapor phase epitaxy, HVPE)製程或上述組合於金屬氮化層16上形成第一阻障層18及第二阻障層20。
隨後依序形成一第一硬遮罩22以及一第二硬遮罩24於第二阻障層20表面。在本實施例中，第一硬遮罩22與第二硬遮罩24較佳包含不同材料，其中第一硬遮罩22較佳包含氮化矽且其厚度較佳小於5奈米，第二硬遮罩24則較佳包含氧化矽，但均不侷限於此。
如第2圖所示，接著進行一平台隔離(MESA isolation)製程定義出MESA區域26與主動區域，使元件之間可獨立運作而不致受到彼此交互影響。在本實施例中，平台隔離製程可利用一微影暨蝕刻製程圖案化或以蝕刻去除部分第二硬遮罩24、部分第一硬遮罩22、部分第二阻障層20、部分第一阻障層18、部份金屬氮化層16以及部分緩衝層14，其中被圖案化的第二硬遮罩24、第一硬遮罩22、第二阻障層20、第一阻障層18、金屬氮化層16以及緩衝層14較佳具有相同寬度且被圖案化的材料層之間的邊緣較佳相互切齊，而剩餘且未被圖案化的部分緩衝層14則與基底12包含相同寬度。
隨後形成一第三硬遮罩28於第二硬遮罩24上並覆蓋圖案化的第二硬遮罩24側壁、第一硬遮罩22側壁、第二阻障層20側壁、第一阻障層18側壁、金屬氮化層16側壁、緩衝層14側壁以及設於MESA區域26兩側的緩衝層14表面。在本實施例中，第二硬遮罩24與第三硬遮罩28較佳包含相同材料例如兩者均由氧化矽所構成，但不侷限於此。
然後如第3圖所示，進行一微影暨蝕刻製程，例如可利用一圖案化遮罩(圖未示)為遮罩去除部分第三硬遮罩28、部分第二硬遮罩24、部分第一硬遮罩22以及部分第二阻障層20以形成一凹槽30並同時暴露出第一阻障層18表面。需注意的是，本實施例於進行上述微影曁蝕刻製程形成凹槽30時雖較佳不去除任何第一阻障層18或凹槽30正下方的第一阻障層18上表面較佳切齊凹槽30兩側的第一阻障層18上表面，但不侷限於此，依據本發明其他實施例又可於去除部分第二阻障層20後再繼續去除部分第一阻障層18形成凹槽30，使凹槽30正下方的第一阻障層18上表面略低於凹槽30兩側的第一阻障層18上表面，此變化型也屬本發明所涵蓋的範圍。
如第4圖所示，接著形成一形成一P型半導體層32於凹槽30正下方的第一阻障層18上，再去除第三硬遮罩28與第二硬遮罩24暴露出下方的第一硬遮罩22。在一實施利中，P型半導體層32較佳包含P型氮化鎵，且可利用分子束磊晶製程(molecular-beam epitaxy, MBE)、有機金屬氣相沉積(metal organic chemical vapor deposition, MOCVD)製程、化學氣相沉積(chemical vapor deposition, CVD)製程、氫化物氣相磊晶(hydride vapor phase epitaxy, HVPE)製程或上述組合於凹槽30內的第一阻障層18表面形成P型半導體層32且P型半導體層32上表面較佳高於兩側的第一硬遮罩22上表面。
隨後如第5圖所示，先形成一保護層34於第一硬遮罩22、P型半導體層32以及MESA區域26兩側的緩衝層14表面，再形成一閘極電極36於P型半導體層32上以及源極電極38與汲極電極40於閘極電極36兩側。在本實施例中，可先進行一微影暨蝕刻製程去除P型半導體層32正上方的部分保護層34形成凹槽(圖未示)，形成一閘極電極36於凹槽內，去除閘極電極36兩側的部分保護層34及部分第一硬遮罩22形成二凹槽，再分別形成源極電極38與汲極電極40於閘極電極36兩側。
在本實施例中，閘極電極36、源極電極38以及汲極電極40較佳由金屬所構成，其中閘極電極36較佳由蕭特基金屬所構成而源極電極38與汲極電極40較佳由歐姆接觸金屬所構成。依據本發明一實施例，閘極電極36、源極電極38及汲極電極40可各自包含金、銀、鉑、鈦、鋁、鎢、鈀或其組合。在一些實施例中，可利用電鍍製程、濺鍍製程、電阻加熱蒸鍍製程、電子束蒸鍍製程、物理氣相沉積(physical vapor deposition, PVD)製程、化學氣相沉積製程(chemical vapor deposition, CVD)製程、或上述組合於上述凹槽內形成導電材料，然後再利用單次或多次蝕刻將電極材料圖案化以形成閘極電極36、源極電極38以及汲極電極40。至此即完成本發明一實施例之一高電子遷移率電晶體的製作。
請再參照第5圖，第5圖另揭露本發明一實施例之一高電子遷移率電晶體之結構示意圖。如第5圖所示，高電子遷移率電晶體主要包含緩衝層14設於基底12上，P型半導體層32設於緩衝層14上，第一阻障層18設於緩衝層14及P型半導體層32之間，第二阻障層20設於P型半導體層32兩側的第一阻障層18上，閘極電極36設於P型半導體層32上以及源極電極38以及汲極電極40設於閘極電極36兩側的第二阻障層20上，其中P型半導體層32側壁較佳切齊閘極電極36側壁。
在本實施例中，第一阻障層18與第二阻障層20較佳包含不同厚度，例如第一阻障層18厚度較佳小於第二阻障層20厚度。另外第一阻障層18與第二阻障層20較佳包含不同鋁濃度或更具體而言第一阻障層18之鋁濃度較佳小於第二阻障層20之鋁濃度。舉例來說，若第一阻障層18包含III-V族半導體例如氮化鋁鎵(Alx Ga1-x N)，其中0>x>1，x較佳介於5-15%。第二阻障層20若同樣包含III-V族半導體例如氮化鋁鎵(Alx Ga1-x N)，其中0>x>1，x較佳介於15-50%。P型半導體層32則較佳包含P型氮化鎵。
綜上所述，本發明主要先形成多層由例如氮化矽以及/或氧化矽所構成的硬遮罩於AlGaN阻障層表面，去除部分硬遮罩與阻障層形成凹槽，再形成P型半導體層及閘極電極於凹槽內。依據本發明之較佳實施例，覆蓋於AlGaN阻障層表面的硬遮罩可於凹槽形成時用來保護AlGaN阻障層，避免阻障層受到蝕刻劑傷害並改善後續形成保護層後可能產生的應力損害(stress degradation)。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
12:基底 14:緩衝層 16:金屬氮化層 18:第一阻障層 20:第二阻障層 22:第一硬遮罩 24:第二硬遮罩 26:MESA區域 28:第三硬遮罩 30:凹槽 32:P型半導體層 34:保護層 36:閘極電極 38:源極電極 40:汲極電極
第1圖至第5圖為本發明一實施例製作一高電子遷移率電晶體之方法示意圖。
12:基底
14:緩衝層
16:金屬氮化層
18:第一阻障層
20:第二阻障層
22:第一硬遮罩
26:MESA區域
32:P型半導體層
34:保護層
36:閘極電極
38:源極電極
40:汲極電極

Claims (20)

  1. 一種製作高電子遷移率電晶體(high electron mobility transistor, HEMT)的方法，其特徵在於，包含： 形成一緩衝層於一基底上； 形成一第一阻障層於該緩衝層上； 形成一第二阻障層於該第一阻障層上； 形成一第一硬遮罩於該第二阻障層上； 去除該第一硬遮罩以及該第二阻障層以形成一凹槽；以及 形成一P型半導體層於該凹槽內。
  2. 如申請專利範圍第1項所述之方法，另包含： 形成一第二硬遮罩於該第一硬遮罩上； 圖案化該第二硬遮罩、該第一硬遮罩、該第二阻障層、該第一阻障層以及該緩衝層； 形成一第三硬遮罩於該第二硬遮罩上； 去除該第三硬遮罩、該第二硬遮罩、該第一硬遮罩以及該第二阻障層以形成該凹槽； 形成該P型半導體層於該凹槽內； 去除該第三硬遮罩以及該第二硬遮罩； 形成一保護層於該第一硬遮罩上； 形成一閘極電極於該P型半導體層上；以及 形成一源極電極以及一汲極電極於該閘極電極兩側。
  3. 如申請專利範圍第2項所述之方法，其中該第二硬遮罩以及該第三硬遮罩包含相同材料。
  4. 如申請專利範圍第1項所述之方法，其中該第一硬遮罩以及該第二硬遮罩包含不同材料。
  5. 如申請專利範圍第1項所述之方法，其中該第一阻障層以及該第二阻障層包含氮化鋁鎵(Alx Ga1-x N)。
  6. 如申請專利範圍第5項所述之方法，其中該第一阻障層以及該第二阻障層包含不同鋁濃度。
  7. 如申請專利範圍第5項所述之方法，其中該第一阻障層之鋁濃度小於該第二阻障層之鋁濃度。
  8. 如申請專利範圍第1項所述之方法，其中該第一阻障層厚度小於該第二阻障層厚度。
  9. 如申請專利範圍第1項所述之方法，另包含於形成該第一阻障層之前形成一金屬氮化層於該緩衝層上。
  10. 如申請專利範圍第1項所述之方法，其中該P型半導體層包含P型氮化鎵。
  11. 一種高電子遷移率電晶體(high electron mobility transistor, HEMT)，其特徵在於，包含： 一緩衝層設於一基底上； 一第一阻障層設於該緩衝層上； 一P型半導體層設於該第一阻障層上； 一第二阻障層設於該P型半導體層兩側之該第一阻障層上； 一閘極電極設於該P型半導體層上；以及 一源極電極以及一汲極電極設於該閘極電極兩側之該第二阻障層上。
  12. 如申請專利範圍第11項所述之高電子遷移率電晶體，另包含一硬遮罩設於該第二阻障層以及該P型半導體層上。
  13. 如申請專利範圍第12項所述之高電子遷移率電晶體，其中該硬遮罩上表面低於該P型半導體層上表面。
  14. 如申請專利範圍第12項所述之高電子遷移率電晶體，另包含一保護層設於該硬遮罩上、該第二阻障層側壁、該第一阻障層側壁以及該緩衝層側壁。
  15. 如申請專利範圍第11項所述之高電子遷移率電晶體，其中該第一阻障層以及該第二阻障層包含氮化鋁鎵(Alx Ga1-x N)。
  16. 如申請專利範圍第15項所述之高電子遷移率電晶體，其中該第一阻障層以及該第二阻障層包含不同鋁濃度。
  17. 如申請專利範圍第15項所述之高電子遷移率電晶體，其中該第一阻障層之鋁濃度小於該第二阻障層之鋁濃度。
  18. 如申請專利範圍第11項所述之高電子遷移率電晶體，其中該第一阻障層厚度小於該第二阻障層厚度。
  19. 如申請專利範圍第11項所述之高電子遷移率電晶體，另包含一金屬氮化層設於該緩衝層及該第一阻障層之間。
  20. 如申請專利範圍第11項所述之高電子遷移率電晶體，其中該P型半導體層包含P型氮化鎵。
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