TWI622173B - Field effect tube and manufacturing method thereof - Google Patents

Field effect tube and manufacturing method thereof Download PDF

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TWI622173B
TWI622173B TW106102942A TW106102942A TWI622173B TW I622173 B TWI622173 B TW I622173B TW 106102942 A TW106102942 A TW 106102942A TW 106102942 A TW106102942 A TW 106102942A TW I622173 B TWI622173 B TW I622173B
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layer
insulating layer
gate insulating
gate
gate structure
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TW201737488A (zh
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xu-dong Qin
hui-long Xu
Chen-Xiong Zhang
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Huawei Tech Co Ltd
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Abstract

本發明公開了一種場效應管及其製造方法,屬於電子技術領域。本發明提供的場效應管包括兩個頂柵電極和兩個底柵電極,該頂柵電極和底柵電極兩兩相對,使得該場效應管增加了由控制電壓感生的載流子數量,進而增大場效應管的輸出電流,提高了在高頻使用時的功率增益極限頻率,並且使得所述頂柵電極和所述底柵電極之間的電場更加充分的覆蓋所述源極和所述漏極之間的所述溝道層,進而減小了在高頻下的寄生效應,進一步提高了場效應管的頻率特性。

Description

場效應管及其製造方法
本發明涉及電子技術領域,特別涉及一種場效應管及其製造方法。
隨著電子技術的發展,矽積體電路中電子元件的頻率特性,例如功率增益極限頻率等,逐漸逼近物理規律的極限,進而如何使得電子元件的頻率特性進一步提高成為了本技術領域重要的技術問題。
場效應管是一種常見的電子元件,習知技術中一般採用矽基半導體材料來製備場效應管,為了提供更好的頻率特性,可以採用石墨烯等二維材料代替矽基半導體材料,從而製備基於石墨烯材料的場效應管。由於石墨烯材料具有二維特性、高遷移率、高飽和速度等優勢,進而使得上述基於石墨烯材料的場效應管相比於傳統矽基場效應管能夠具有更好的頻率特性,例如,具有更高的截止頻率。
然而,由於上述基於石墨烯材料的場效應管仍採用傳統的絕緣柵場效應管結構,進而容易造成輸出電流低、對載流子散射效應較大、寄生效應明顯等問題,使得該基於石墨烯材料的場效應管未實現理想的頻率特性。
為了克服本領域記憶體在的技術問題,本發明實施例提供了一種場效應管及其製造方法。該技術方案如下。
第一方面,提供了一種場效應管,所述場效應管包括:襯底層,所述襯底層的上表面凹槽中設置有第一柵結構和第二柵結構;覆蓋於所述襯底層上表面的底柵絕緣層;覆蓋於所述底柵絕緣層上表面的溝道層;覆蓋於所述溝道層上表面的頂柵絕緣層,所述頂柵絕緣層的下表面上設置有:所述第一源極、第二源極以及設置於所述第一源極和第二源極之間的漏極,所述頂柵絕緣層的上表面凹槽中設置有第三柵結構和第四柵結構;所述第三柵結構設置於所述第一柵結構在所述頂柵絕緣層上的第一投影區域內,所述第一投影區域位於所述第一源極與所述漏極之間;所述第四柵結構設置於所述第二柵結構在所述頂柵絕緣層上的第二投影區域內,所述第二投影區域位於所述第二源極與所述漏極之間。
在第一方面的一種可能設計中,所述第一投影區域的兩個邊緣分別與所述第一源極的邊緣及所述漏極的邊緣相重合,所述第二投影區域的兩個邊緣分別與所述第二源極的邊緣及所述漏極的邊緣相重合。
在第一方面的一種可能設計中,所述第三柵結構的面積小於或等於所述第一投影區域的面積;所述第四柵結構的面積小於或等於所述第二投影區域的面積。
在第一方面的一種可能設計中,所述第三柵結構和所述第四柵結構相互平行;或,所述第三柵結構和所述第四柵結構為一個門框形的連通結構。
在第一方面的一種可能設計中,所述第一柵結構與所述第三柵結構通過接觸孔相連接,所述第二柵結構與所述第四柵結構通過接觸孔相連接。
在第一方面的一種可能設計中,所述溝道層採用石墨烯、二硫化鉬、或黑磷或其他二維材料中的一種。
第二方面,提供了一種場效應管,所述場效應管包括:襯底層,所述襯底層的上表面的第一凹槽中設置有第一柵結構以及覆蓋於第一柵結構上的第一底柵絕緣層,所述襯底層的上表面的第二凹槽中第二柵結構以及覆蓋於所述第二底柵絕緣層;覆蓋於所述第一底柵絕緣層上,且呈凹槽形狀的第一溝道層;覆蓋於所述第二底柵絕緣層上,且呈凹槽形狀的第二溝道層;所述第一溝道層所形成的凹槽的底表面上設置有第一頂柵絕緣層以及覆蓋在所述第一頂柵絕緣層上的第三柵結構;所述第二溝道層所形成的凹槽的底表面上設置有第二頂柵絕緣層以及覆蓋在所述第二頂柵絕緣層上的第四柵結構;設置於由所述襯底層、所述第一溝道層的第一外表面以及所述第二溝道層的第一外表面所形成的凹槽結構內的漏極;覆蓋於所述襯底層上、並與所述第一溝道層的第二外表面相接觸的第一源極;覆蓋於所述襯底層上、並與所述第二溝道層的第二外表面相接觸的第二源極。
在第二方面的一種可能設計中,所述溝道層採用石墨烯、二硫化鉬、或黑磷或其他二維材料中的一種。
協力廠商面,提供了一種場效應管的製造方法,所述方法包括:提供一襯底層;在所述襯底層上形成底柵電極,所述底柵電極包括第一柵結構和第二柵結構;在所述底柵電極之上形成底柵絕緣層;在所述底柵絕緣層之上附著溝道層;在所述溝道層之上形成源極及漏極,所述源極包括第一源極和第二源極;在所述溝道層及所述源極及漏極之上形成頂柵絕緣層;在所述頂柵絕緣層之上形成頂柵電極,所述頂柵電極包括第三柵結構和第四柵結構。
在協力廠商面的一種可能設計中,所述在所述襯底層上形成底柵電極包括:採用光刻及刻蝕工藝,在所述襯底層上形成兩個凹槽結構;在所述 兩個凹槽結構內分別形成所述底柵電極的第一柵結構和所述底柵電極的第二柵結構。
在協力廠商面的一種可能設計中,在所述形成底柵絕緣層之前,所述方法還包括:採用化學機械拋光方法,對形成底柵電極的襯底層表面進行處理。
在協力廠商面的一種可能設計中,所述在所述頂柵絕緣層之上形成頂柵電極包括:在所述頂柵電極與所述底柵電極之間製作垂直接觸孔,使得所述頂柵電極與所述底柵電極相連接。
第四方面,提供了一種場效應管的製造方法,所述方法包括:提供一襯底層;在所述襯底層上製備形成源極及漏極所需的薄膜結構;在所述薄膜結構上形成犧牲層,所述犧牲層可溶解於特定的溶液;在所述襯底層及所述薄膜結構及所述犧牲層上形成第一凹槽結構與第二凹槽結構;在所述第一凹槽結構及第二凹槽結構內分別形成底柵電極的第一柵結構和底柵電極的第二柵結構;在所述第一凹槽結構及第二凹槽結構內分別形成第一底柵絕緣層和第二底柵絕緣層;附著溝道層;在所述溝道層上形成第一頂柵絕緣層及第二頂柵絕緣層;在所述第一頂柵絕緣層及所述第二頂柵絕緣層之上分別形成頂柵電極的第三柵結構和頂柵電極的第四柵結構;腐蝕掉所述犧牲層。
在第四方面的一種可能設計中,在形成第一底柵絕緣層和第二底柵絕緣層之後,所述附著溝道層包括:原位沉積所述溝道層,使得所述溝道層折疊貼服在第一底柵絕緣層和第二底柵絕緣層之上的第一凹槽結構及第二凹槽結構內。
在第四方面的一種可能設計中,所述形成頂柵電極的第三柵結構和頂柵電極的第四柵結構包括:在所述頂柵電極與所述底柵電極之間製作垂直接觸孔,使得所述頂柵電極與所述底柵電極相連接。
本發明實施例提供的技術方案的有益效果是:本發明提供的場效應管包括兩個頂柵電極和兩個底柵電極,該頂柵電極和底柵電極兩兩相對,使得該場效應管增加了由控制電壓感生的載流子數量,進而增大場效應管的輸出電流,提高了在高頻使用時的功率增益極限頻率,並且使得該頂柵電極和該底柵電極之間的電場更加充分的覆蓋該源極和該漏極之間的該溝道層,進而減小了在高頻下的寄生效應,進一步提高了場效應管的頻率特性。
101、401‧‧‧襯底層
102‧‧‧柵極絕緣層
1021‧‧‧頂柵絕緣層
1022‧‧‧底柵絕緣層
103‧‧‧柵電極
1031‧‧‧頂柵電極
1031C、4031C‧‧‧第三柵結構
1031D、4031D‧‧‧第四柵結構
1032‧‧‧底柵電極
1032A、4032A‧‧‧第一柵結構
1032B、4032B‧‧‧第二柵結構
104‧‧‧源極
1041、4041‧‧‧第一源極
1042、4042‧‧‧第二源極
105‧‧‧漏極
106‧‧‧溝道層
201‧‧‧第一投影區域
2011‧‧‧第一投影區域的邊緣
202‧‧‧第二投影區域
2021‧‧‧第二投影區域的邊緣
4021C‧‧‧第一頂柵絕緣層
4021D‧‧‧第二頂柵絕緣層
4022A‧‧‧第一底柵絕緣層
4022B‧‧‧第二底柵絕緣層
4061‧‧‧第一溝道層
4062‧‧‧第二溝道層
405‧‧‧漏極
501~507‧‧‧步驟
701~710‧‧‧步驟
為了更清楚地說明本發明實施例中的技術方案,下面將對實施例描述中所需要使用的附圖作簡單地介紹,顯而易見地,下面描述中的附圖僅僅是本發明的一些實施例,對於本領域的通常知識者來講,在不付出進步性勞動的前提下,還可以根據這些附圖獲得其他的附圖。
圖1是本發明實施例1提供的一種場效應管的垂直切面結構示意圖;圖2是本發明實施例1提供的一種場效應管的垂直切面結構中關於投影區域的示意圖;圖3是發明實施例1提供的一種場效應管沿圖2中AA’方向的剖視圖; 圖4是本發明實施例2提供的一種場效應管的垂直切面結構示意圖;圖5是本發明實施例3提供的一種場效應管製造方法的流程圖;圖6是本發明實施例3提供的一種場效應管製造方法中每個步驟完成時,待製造的場效應管結構示意圖;圖7是本發明實施例4提供的一種場效應管製造方法的流程圖;圖8是本發明實施例4提供的一種場效應管製造方法中每個步驟完成時,待製造的場效應管結構示意圖。
為使本發明的目的、技術方案和優點更加清楚,下面將結合附圖對本發明實施方式作進一步地詳細描述。
實施例1
圖1是本發明實施例1提供的一種場效應管的垂直切面結構示意圖,如圖所示,該場效應管包括:襯底層101,所述襯底層101的上表面凹槽中設置有第一柵結構1032A和第二柵結構1032B;覆蓋於所述襯底層101上表面的底柵絕緣層1022,該底柵絕緣層1022用於使得作為底柵電極的第一柵結構1032A和第二柵結構1032B與該溝道層106之間為斷開狀態。
覆蓋於所述底柵絕緣層1022上表面的溝道層106;覆蓋於所述溝道層106上表面的頂柵絕緣層1021,所述頂柵絕緣層1021的下表面上設置有:所述第一源極1041、第二源極1042以及設置於所述第一源極1041和第二源極1042之間的漏極105,通過上述結構,溝道層106與該第一源極1041、第二源極1042及該漏極105相接觸,使得通過柵電極103施加控制電壓時,基於該溝道層106, 在該源極104和該漏極105之間形成導電溝道。所述頂柵絕緣層1021的上表面凹槽中設置有第三柵結構1031C和第四柵結構1031D,該頂柵絕緣層1021用於使得該第三柵結構1031C和第四柵結構1031D與該溝道層106之間為斷開狀態;所述第三柵結構1031C設置於所述第一柵結構1032A在所述頂柵絕緣層1021上的第一投影區域內,所述第一投影區域位於所述第一源極1041與所述漏極105之間;所述第四柵結構1031D設置於所述第二柵結構1032B在所述頂柵絕緣層1021上的第二投影區域內,所述第二投影區域位於所述第二源極1042與所述漏極105之間。
為了在該溝道層106的上下兩個方向共同施加控制電壓,以增加由該控制電壓感生的載流子數量,進而增大場效應管的輸出電流,提高在高頻使用時的功率增益極限頻率,本發明實施例所提供的結構包括作為頂柵電極的第三柵結構1031C和第四柵結構1031D和底柵電極的第一柵結構1032A和第二柵結構1032B。
該漏極105設置於該第一源極1041和第二源極1042之間,進而使得在該第一源極1041與該漏極105之間及該第二源極1042與該漏極105分別形成導電溝道,從而提供了一種雙導電溝道結構,進一步提高場效應管的輸出電流,提高另外在高頻使用時的功率增益極限頻率。
該第一柵結構1032A和第三柵結構1031C對應,用於向一導電溝道施加控制電壓,該第二柵結構1032B和第四柵結構1031D對應,用於向另一導電溝道施加控制電壓。需要說明的是,在實際應用中,分別用於形成該兩個導電溝道的柵電極、柵極絕緣層及源極可以具有相同的形狀和尺寸,也可以根據需要具有不同的形狀和尺寸,本發明對上述任一結構的具體形狀和尺寸不作限定。還需要說明的是,在實際應用中,作為源極的第一源極1041和第二源極1042 和漏極105接入的電壓可以互換,進而第一源極1041和第二源極1042可以被設置為漏極,而漏極105可以被設置為源極,本發明對源極和漏極是否互換不作具體限定。
為了在施加控制電壓時,能夠使得頂柵電極1031和底柵電極1032之間的電場充分覆蓋該第一源極1041、第二源極1042和該漏極105之間的溝道層106,進而減小場效應管在高頻下的寄生效應,如寄生電阻、寄生電容等,進而提升場效應管的頻率特性,本發明實施例中,如圖2所示,該第三柵結構1031C設置於該第一柵結構1032A在該頂柵絕緣層1021上的第一投影區域201內,該第一投影區域201位於該第一源極1041與該漏極105之間,該第三柵結構1031C與第一柵結構1032A之間依次設置為頂柵絕緣層1021、該溝道層106、該底柵絕緣層1022。頂柵絕緣層1021以及底柵絕緣層1022統稱為柵極絕緣層102,頂柵電極1031和底柵電極1032統稱為柵電極103。
相應地,該第四柵結構1031D設置於該第二柵結構1032B在該頂柵絕緣層1021上的第二投影區域202內,該第二投影區域202位於該第二源極1042與漏極105之間,該第四柵結構1031D與該第二柵結構1032B及之間依次設置為頂柵絕緣層1021、該溝道層106、該底柵絕緣層1022。
為了在施加控制電壓時,能夠使得頂柵電極和底柵電極之間的電場更加充分覆蓋該第一源極1041、第二源極1042和該漏極105之間的溝道層106,進而進一步減小高頻下的寄生效應,在本發明實施例中,如圖2所示,該第一投影區域201的兩個邊緣2011分別與該第一源極1041的邊緣及該漏極105的邊緣相重合,該第二投影區域202的兩個邊緣2021分別與該第二源極1042的邊緣及該漏極105的邊緣相重合。
為了在施加控制電壓時,能夠使得頂柵電極1031和底柵電極1032之間的電場更加充分覆蓋該源極104和該漏極105之間的溝道層106,進而進一步減小高頻下的寄生效應,在本發明實施例中,該第三柵結構1031C的面積小於等於該第一投影區域201面積,該第四柵結構1031D的面積小於等於該第二投影區域202面積。圖3是圖2中沿AA’方向的剖視圖,如圖3所示,該第一投影區域201及該第一投影區域202的面積是指該任一投影區域在與襯底層101平行的平面上所占面積。
為了進一步提高場效應管的輸出電流,進而進一步提高在高頻使用時的功率增益極限頻率,在本發明實施例中,該第三柵結構1031C和該第四柵結構1031D相互平行。具體地,如圖3所示,所述第三柵結構1031C和所述第四柵結構1031D為一個門框形的連通結構,也即是,頂柵電極包括相互平行的兩部分以及用於連接該兩部分之間的連通部分。該相互平行的部分可以分別為矩形結構。需要說明的是,上述任一個柵結構的形狀可以根據實際應用情況進行設置,本發明對此不做限定。
為了方便製造,該襯底層101具有凹槽結構,該底柵電極1032設置於該凹槽結構之中。具體地,該襯底層101具有兩個相互平行的凹槽結構,該底柵電極1032的第一柵結構1032A和第二柵結構1032B分別設置於該兩個相互平行的凹槽結構。
為了可以在頂柵電極1031和底柵電極1032施加相同的控制電壓,該頂柵電極和底柵電極通過接觸孔相連接,也即是,所述第一柵結構1032A與所述第三柵結構1031C通過接觸孔相連接,所述第二柵結構1032B與所述第四 柵結構1031D通過接觸孔相連接。該接觸孔設置的具體位置可以根據電路佈線的實際情況進行選擇,本發明對此不作限定。
實施例2
圖4是本發明實施例2提供的一種場效應管的垂直切面結構示意圖,如圖4所示,該場效應管包括:襯底層401,所述襯底層401的上表面的第一凹槽中設置有第一柵結構4032A以及覆蓋於第一柵結構4032A上的第一底柵絕緣層4022A,所述襯底層401的上表面的第二凹槽中第二柵結構4032B以及覆蓋於所述第二底柵絕緣層4022B,以方便製造。
覆蓋於所述第一底柵絕緣層4022A上,且呈凹槽形狀的第一溝道層4061;覆蓋於所述第二底柵絕緣層4022B上,且呈凹槽形狀的第二溝道層4062;所述第一溝道層4061所形成的凹槽的底表面上設置有第一頂柵絕緣層4021C以及覆蓋在所述第一頂柵絕緣層4021C上的第三柵結構4031C;所述第二溝道層4062所形成的凹槽的底表面上設置有第二頂柵絕緣層4021D以及覆蓋在所述第二頂柵絕緣層4021D上的第四柵結構4031D,這種結構,是為了基於石墨烯柔軟的機械性能,方便製造。
設置於由所述襯底層401、所述第一溝道層4061的第一外表面以及所述第二溝道層4062的第一外表面所形成的凹槽結構內的漏極405;覆蓋於所述襯底層401上、並與所述第一溝道層4061的第二外表面相接觸的第一源極4041;覆蓋於所述襯底層401上、並與所述第二溝道層4062的第二外表面相接觸的第二源極4042。
該第一溝道層4061與該第一源極4041及該漏極405相接觸,用於形成該第一源極4041及該漏極405之間的導電溝道,該第二溝道層4062與該第二 源極4042及該漏極405相接觸,用於形成該第二源極4042和該漏極405之間的導電溝道,從而在施加控制電壓時,能夠使得頂柵電極和底柵電極之間的電場完全覆蓋該源極和該漏極之間的溝道層,進而進一步減小高頻下的寄生效應。
需要說明的是,在實際應用中,該第一頂柵絕緣層4021C和第二頂柵絕緣層4021D可以連接,也可以不連接,該第一底柵絕緣層4022A和第二底柵絕緣層4022B可以連接,也可以不連接,本發明對此不作具體限定。
實施例3
圖5是本發明實施例3提供的一種場效應管製造方法的流程圖,該方法用於製造實施例1提供的場效應管,並以溝道材料為石墨烯為例進行說明,包括以下步驟。
501、如圖6中a圖所示,提供一襯底層。在實際應用中,該襯底層的材料可以是的二氧化矽(SiO2)、碳化矽(SiC)、氮化硼(BN)、氮化矽(Si3N4)、聚對苯二甲酸乙二酯(PET)、藍寶石等絕緣材料,本發明對襯底層的材料不作具體限定。
502、如圖6中b圖所示,在該襯底層上形成底柵電極,該底柵電極包括第一柵結構和第二柵結構。具體地,採用光刻及刻蝕及鍍膜工藝,在該襯底層上形成兩個凹槽結構,在該兩個凹槽結構內分別形成該底柵電極的第一柵結構和該底柵電極的第二柵結構。在實際應用中,該底柵電極的材料可以是銅、鉑、金等金屬材料,本發明對該底柵電極的材料不作限定。在實際應用中,根據待製造場效應管的尺寸特徵,該光刻工藝可以選擇為普通光刻工藝,或電子束曝光光刻工藝,本發明對此不作限定。在實際應用中,該刻蝕工藝包括等 離子體刻蝕等,該鍍膜工藝包括濺射鍍膜工藝、蒸發鍍膜工藝等,本發明對形成該底柵電極的具體工藝不作限定。
503、如圖6中c圖所示,在該底柵電極之上形成底柵絕緣層。本發明實施例中,在本步驟之前採用化學機械拋光方法,對形成底柵電極的襯底層表面進行處理,使得該表面保持平整。該底柵絕緣層材料可以是SiO2,Al2O3等,本發明對此不作限定。形成該底柵絕緣層的具體工藝可以為化學氣相沉積、原子層沉積等,本發明對此不作限定。
504、如圖6中d圖所示,在該底柵絕緣層之上附著溝道層(石墨烯層)。
505、如圖6中e圖所示,在該溝道層之上形成源極及漏極,該源極包括第一源極和第二源極,該漏極設置於該第一源極和該第二源極之間。具體形成過程包括:在該石墨烯層上通過光刻工藝定義源極及漏極區域,然後通過鍍膜工藝形成源極及漏極。該源極及漏極材料可以是銅、鉑、金等金屬。
506、如圖6中f圖所示,在該溝道層及該源極及漏極之上形成頂柵絕緣層。該頂柵絕緣層材料可以是二氧化矽(SiO2)、三氧化二鋁(Al2O3)等,本發明對此不作限定。形成該頂柵絕緣層的具體工藝可以為化學氣相沉積、原子層沉積等,本發明對此不作限定。
507、如圖6中g圖所示,在該頂柵絕緣層之上形成頂柵電極,該頂柵電極包括第三柵結構和第四柵結構。具體地,在形成該頂柵電極包括在該頂柵電極與該底柵電極之間製作垂直接觸孔,使得該頂柵電極與該底柵電極相連接。
實施例4
圖7是本發明實施例4提供的一種場效應管製造方法的流程圖,該方法用於製造實施例2提供的場效應管,並以溝道材料為石墨烯為例進行說明,包括以下步驟。
701、如圖8中a圖所示,提供一襯底層,該步驟與實施例3中步驟501同理,在此不再贅述。
702、如圖8中b圖所示,在該襯底層上製備形成源極及漏極所需的薄膜結構。該薄膜結構可以通過鍍膜工藝形成。該鍍膜工藝包括濺射鍍膜工藝、蒸發鍍膜工藝等,本發明對形成該薄膜結構的具體工藝不作限定。在實際應用中,該的材料可以是銅、鉑、金等金屬材料,本發明對該薄膜結構的材料不作限定。
703、如圖8中c圖所示,在該薄膜結構上形成犧牲層,該犧牲層可溶解於特定的溶液。該犧牲層材料可以是氧化矽、多晶矽、氮化矽、光刻膠等,本發明對此不作具體限定。
704、如圖8中d圖所示,在該襯底層及該薄膜結構及該犧牲層上形成第一凹槽結構與第二凹槽結構。採用光刻及刻蝕工藝形成該第一凹槽結構及第二凹槽結構。在實際應用中,根據待製造場效應管的尺寸特徵,該光刻工藝可以選擇為普通光刻工藝,或電子束曝光光刻工藝,本發明對此不作限定。該刻蝕工藝包括離子束刻蝕等,本發明對形成該第一凹槽結構與第二凹槽結構的具體工藝不作限定。
705、如圖8中e圖所示,在該第一凹槽結構及第二凹槽結構內分別形成底柵電極的第一柵結構和底柵電極的第二柵結構。採用電子束蒸發鍍膜的工藝形成該底柵電極的第一柵結構和底柵電極的第二柵結構。在實際應用 中,也可以採用其他工藝形成該第一柵結構和該第二柵結構,本發明對此不作限定。
706、如圖8中f圖所示,在該第一凹槽結構及第二凹槽結構內分別形成第一底柵絕緣層和第二底柵絕緣層。採用電子束蒸發鍍膜的工藝形成該第一底柵絕緣層和第二底柵絕緣層。在實際應用中,也可以採用其他工藝形成該第一底柵絕緣層和該第二底柵絕緣層,本發明對此不作限定。
707、如圖8中g圖所示,附著溝道層(石墨烯層)。原位沉積該石墨烯層,使得該石墨烯層折疊貼服在第一底柵絕緣層和第二底柵絕緣層之上的第一凹槽結構及第二凹槽結構內。在本發明實施例中,石墨烯均勻連續附著在該結構表面,與該結構中的金屬形成歐姆接觸。
708、如圖8中h圖所示,在該溝道層上形成第一頂柵絕緣層及第二頂柵絕緣層。採用電子束蒸發鍍膜的工藝形成該第一頂柵絕緣層及第二頂柵絕緣層。在實際應用中,也可以採用其他工藝形成該第一頂柵絕緣層及該第二頂柵絕緣層,本發明對此不作限定。
709、如圖8中i圖所示,在該第一頂柵絕緣層及該第二頂柵絕緣層之上分別形成頂柵電極的第三柵結構和頂柵電極的第四柵結構。具體形成過程還包括:在該頂柵電極與該底柵電極之間製作垂直接觸孔,使得該頂柵電極與該底柵電極相連接。
710、如圖8中j圖所示,腐蝕掉該犧牲層。通過腐蝕掉該犧牲層,使得該犧牲層之上的結構脫落,進而獲得需要製造的場效應管。
本領域的通常知識者可以理解實現上述實施例的全部或部分步驟可以通過硬體來完成,也可以通過程式來指令相關的硬體完成,該的程式可 以存儲於一種電腦可讀存儲介質中,上述提到的存儲介質可以是唯讀記憶體,磁片或光碟等。
以上僅為本發明的較佳實施例,並不用以限制本發明,凡在本發明的精神和原則之內,所作的任何修改、等同替換、改進等,均應包含在本發明的保護範圍之內。

Claims (13)

  1. 一種場效應管,其中,該場效應管包括:一襯底層(101),該襯底層(101)的上表面凹槽中設置有一第一柵結構(1032A)和一第二柵結構(1032B);覆蓋於該襯底層(101)上表面的一底柵絕緣層(1022);覆蓋於該底柵絕緣層(1022)上表面的一溝道層(106);覆蓋於該溝道層(106)上表面的一頂柵絕緣層(1021),該頂柵絕緣層(1021)的下表面上設置有:一第一源極(1041)、一第二源極(1042)以及設置於該第一源極(1041)和該第二源極(1042)之間的一漏極(105),該頂柵絕緣層(1021)的上表面凹槽中設置有一第三柵結構(1031C)和一第四柵結構(1031D);該第三柵結構(1031C)設置於該第一柵結構(1032A)在該頂柵絕緣層(1021)上的一第一投影區域內,該第一投影區域位於該第一源極(1041)與該漏極(105)之間;該第四柵結構(1031D)設置於該第二柵結構(1032B)在該頂柵絕緣層(1021)上的一第二投影區域內,該第二投影區域位於該第二源極(1042)與該漏極(105)之間。
  2. 根據申請專利範圍第1項所述的場效應管,其中,該第一投影區域的兩個邊緣分別與該第一源極(1041)的邊緣及該漏極(105)的邊緣相重合,該第二投影區域的兩個邊緣分別與該第二源極(1042)的邊緣及該漏極(105)的邊緣相重合。
  3. 根據申請專利範圍第1項所述的場效應管,其中,該第三柵結構(1031C)的面積小於或等於該第一投影區域的面積;該第四柵結構(1031D)的面積小於或等於該第二投影區域的面積。
  4. 根據申請專利範圍第1項所述的場效應管,其中,該第三柵結構(1031C)和該第四柵結構(1031D)相互平行;或,該第三柵結構(1031C)和該第四柵結構(1031D)為一個門框形的連通結構。
  5. 根據申請專利範圍第1項所述的場效應管,其中,該第一柵結構(1032A)與該第三柵結構(1031C)通過接觸孔相連接,該第二柵結構(1032B)與該第四柵結構(1031D)通過接觸孔相連接。
  6. 根據申請專利範圍第1項所述的場效應管,該溝道層採用石墨烯、二硫化鉬、或黑磷或其他二維材料中的一種。
  7. 一種場效應管,其中,該場效應管包括:一襯底層(401),該襯底層(401)的上表面的第一凹槽中設置有一第一柵結構(4032A)以及覆蓋於該第一柵結構(4032A)上的一第一底柵絕緣層(4022A),該襯底層(401)的上表面的第二凹槽中一第二柵結構(4032B)以及覆蓋於該第二底柵絕緣層(4022B);覆蓋於該第一底柵絕緣層(4022A)上,且呈凹槽形狀的一第一溝道層(4061);覆蓋於該第二底柵絕緣層(4022B)上,且呈凹槽形狀的一第二溝道層(4062);該第一溝道層(4061)所形成的凹槽的底表面上設置有一第一頂柵絕緣層(4021C)以及覆蓋在該第一頂柵絕緣層(4021C)上的一第三柵結構(4031C);該第二溝道層(4062)所形成的凹槽的底表面上設置有一第二頂柵絕緣層(4021D)以及覆蓋在該第二頂柵絕緣層(4021D)上的一第四柵結構(4031D);設置於由該襯底層(401)、該第一溝道層(4061)的第一外表面以及該第二溝道層(4062)的第一外表面所形成的凹槽結構內的一漏極(405);覆蓋於該襯底層(401)上、並與該第一溝道層(4061)的第二外表面相接觸的一第一源極(4041);覆蓋於該襯底層(401)上、並與該第二溝道層(4062)的第二外表面相接觸的一第二源極(4042)。
  8. 根據申請專利範圍第7項所述的場效應管,該溝道層採用石墨烯、二硫化鉬、或黑磷或其他二維材料中的一種。
  9. 一種場效應管的製造方法,其中,該製造方法包括下列步驟:提供一襯底層;在該襯底層上形成一底柵電極,該底柵電極包括一第一柵結構和一第二柵結構;在該底柵電極之上形成一底柵絕緣層;在該底柵絕緣層之上附著一溝道層;在該溝道層之上形成源極及漏極,該源極包括一第一源極和一第二源極,該漏極位於該第一源極和該第二源極之間;在該溝道層及該源極及漏極之上形成一頂柵絕緣層;在該頂柵絕緣層之上形成一頂柵電極,該頂柵電極包括一第三柵結構和一第四柵結構,該第三柵結構位於該第一柵結構在該頂柵絕緣層上的一第一投影區域內,該第一投影區域位於該第一源極與該漏極之間,該第四柵結構位於該第二柵結構在該頂柵絕緣層上的一第二投影區域內,該第二投影區域位於該第二源極與該漏極之間。
  10. 根據申請專利範圍第9項所述的製造方法,其中,所述在該襯底層上形成該底柵電極包括:採用光刻及刻蝕工藝,在該襯底層上形成兩個凹槽結構;在兩個凹槽結構內分別形成該底柵電極的該第一柵結構和該底柵電極的該第二柵結構。
  11. 根據申請專利範圍第9項所述的製造方法,其中,在所述形成該底柵絕緣層之前,該製造方法還包括:採用化學機械拋光方法,對形成該底柵電極的該襯底層表面進行處理。
  12. 一種場效應管的製造方法,其中,該製造方法包括:提供一襯底層;在該襯底層上製備形成源極及漏極所需的一薄膜結構;在該薄膜結構上形成一犧牲層,該犧牲層可溶解於特定的溶液;在該襯底層及該薄膜結構及該犧牲層上形成第一凹槽結構與第二凹槽結構;在第一凹槽結構及第二凹槽結構內分別形成一底柵電極的一第一柵結構和該底柵電極的一第二柵結構;在第一凹槽結構及第二凹槽結構內分別形成一第一底柵絕緣層和一第二底柵絕緣層;附著溝道層;在該溝道層上形成一第一頂柵絕緣層及一第二頂柵絕緣層;在該第一頂柵絕緣層及該第二頂柵絕緣層之上分別形成一頂柵電極的一第三柵結構和該頂柵電極的一第四柵結構;腐蝕掉該犧牲層。
  13. 根據申請專利範圍第12項所述的製造方法,其中,在形成該第一底柵絕緣層和該第二底柵絕緣層之後,所述附著該溝道層包括:原位沉積該溝道層,使得該溝道層折疊貼服在該第一底柵絕緣層和該第二底柵絕緣層之上的第一凹槽結構及第二凹槽結構內。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108463889B (zh) * 2016-03-31 2020-11-06 华为技术有限公司 场效应管及其制造方法
CN109671628A (zh) 2017-10-16 2019-04-23 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US20190206904A1 (en) * 2017-12-28 2019-07-04 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Thin film transistor and method of making the same, and array substrate
US11183583B2 (en) 2020-04-25 2021-11-23 International Business Machines Corporation Vertical transport FET with bottom source and drain extensions
CN112599555B (zh) * 2020-12-16 2024-03-05 京东方科技集团股份有限公司 一种压电薄膜器件及其制备方法
CN117199137A (zh) * 2023-09-18 2023-12-08 先之科半导体科技(东莞)有限公司 一种具有脉冲功率放大器的场效应晶体管

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000196093A (ja) * 1998-12-25 2000-07-14 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP2001077342A (ja) * 1999-09-07 2001-03-23 Casio Comput Co Ltd 画像読取装置及びその製造方法
US20060209222A1 (en) * 2005-03-15 2006-09-21 Nec Lcd Technologies, Ltd. Liquid crystal display device and manufacturing method of the same
US20090159894A1 (en) * 2006-01-12 2009-06-25 Sharp Kabushiki Kaisha Semiconductor device and display device
US20110266543A1 (en) * 2007-08-09 2011-11-03 Hiroyuki Moriwaki Circuit board and display device
US20140054701A1 (en) * 2012-03-30 2014-02-27 Boe Technology Group Co., Ltd. Method of manufacturing transistor, transistor, array substrate and display device

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100541047B1 (ko) * 2003-01-20 2006-01-11 삼성전자주식회사 이중 게이트 모스 트랜지스터 및 그 제조방법
KR100689818B1 (ko) * 2004-11-05 2007-03-08 삼성전자주식회사 절연층상 단결정 반도체 박막 형성방법 및 그에 의해제조된 반도체소자
KR100711000B1 (ko) * 2005-11-28 2007-04-24 동부일렉트로닉스 주식회사 이중 게이트를 구비한 모스트랜지스터 및 그 제조방법
KR101718961B1 (ko) * 2010-11-05 2017-03-23 삼성전자주식회사 그래핀을 포함하는 반도체 소자 및 그 제조 방법
US9076873B2 (en) * 2011-01-07 2015-07-07 International Business Machines Corporation Graphene devices with local dual gates
US8530886B2 (en) * 2011-03-18 2013-09-10 International Business Machines Corporation Nitride gate dielectric for graphene MOSFET
KR101813173B1 (ko) * 2011-03-30 2017-12-29 삼성전자주식회사 반도체소자와 그 제조방법 및 반도체소자를 포함하는 전자장치
KR101920713B1 (ko) * 2011-12-23 2018-11-22 삼성전자주식회사 그래핀 소자 및 그 제조방법
CN103308584A (zh) * 2012-03-08 2013-09-18 中国科学院微电子研究所 场效应晶体管气体传感器及其制造方法
KR101910976B1 (ko) * 2012-07-16 2018-10-23 삼성전자주식회사 그래핀을 이용한 전계효과 트랜지스터
CN103077968A (zh) * 2013-01-04 2013-05-01 南京邮电大学 一种非对称峰值轻掺杂漏结构的石墨烯纳米条带场效应管
CN103208524B (zh) 2013-04-25 2016-06-29 西安电子科技大学 一种多层双栅石墨烯场效应的晶体管及其制备方法
EP2887398B1 (en) 2013-12-18 2017-09-13 Imec A bilayer graphene tunneling field effect transistor
CN104638010B (zh) * 2015-01-21 2018-06-05 中山大学 一种横向导通的GaN常关型MISFET器件及其制作方法
CN108463889B (zh) * 2016-03-31 2020-11-06 华为技术有限公司 场效应管及其制造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000196093A (ja) * 1998-12-25 2000-07-14 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP2001077342A (ja) * 1999-09-07 2001-03-23 Casio Comput Co Ltd 画像読取装置及びその製造方法
US20060209222A1 (en) * 2005-03-15 2006-09-21 Nec Lcd Technologies, Ltd. Liquid crystal display device and manufacturing method of the same
US20090159894A1 (en) * 2006-01-12 2009-06-25 Sharp Kabushiki Kaisha Semiconductor device and display device
US20110266543A1 (en) * 2007-08-09 2011-11-03 Hiroyuki Moriwaki Circuit board and display device
US20140054701A1 (en) * 2012-03-30 2014-02-27 Boe Technology Group Co., Ltd. Method of manufacturing transistor, transistor, array substrate and display device

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