CN109037341A - 具有拉长触点的mos晶体管结构 - Google Patents

具有拉长触点的mos晶体管结构 Download PDF

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CN109037341A
CN109037341A CN201810895059.XA CN201810895059A CN109037341A CN 109037341 A CN109037341 A CN 109037341A CN 201810895059 A CN201810895059 A CN 201810895059A CN 109037341 A CN109037341 A CN 109037341A
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contact
mos transistor
elongation
opening
area
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R·C·麦克马伦
K·本伊萨
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Texas Instruments Inc
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Abstract

本发明涉及具有拉长触点的MOS晶体管结构。具有位于第一方向的纵向轴线的拉长金属触点(192)被形成为电连接到具有位于第一方向的纵向轴线的拉长源极区(120V1，120V2)和漏极区(122V1，122V2)，以及具有位于第二方向的纵向轴线的拉长金属触点(194)被形成为电连接到具有位于第二方向的纵向轴线的拉长源极区(120H1，120H2)和漏极区(122H1，122H2)，其中，所述第二方向正交于所述第一方向。

Description

具有拉长触点的MOS晶体管结构
本申请是于2014年03月25日提交的名称为“具有拉长触点的MOS晶体管结构”的中国专利申请201480018285.X的分案申请。
技术领域
本发明涉及具有拉长触点的MOS晶体管结构和它们的制造。
背景技术
金属氧化物半导体(MOS)晶体管是可以作为n沟道(NMOS)器件或p沟道(PMOS)器件来实现的公知半导体器件。MOS晶体管具有空间隔开的源极区和漏极区，所述源极区和漏极区通过沟道隔开，并且栅极位于沟道上面。栅极通过栅极介电层与该沟道隔离。
金属栅极MOS晶体管是利用金属栅极和高k栅极介电层的一类MOS晶体管。电流生成方法例如通过在20nm及20nm以下将源极区和漏极区、沟道、栅极介电层和栅极形成为拉长(elongated)结构来制造金属栅极MOS晶体管。
金属栅极MOS晶体管连接到金属互连结构，该金属互连结构与MOS晶体管一起电连接以形成电路。金属互连结构包括金属径迹层，各金属径迹层通过隔离材料层彼此电隔离，并且延伸穿过隔离材料层的金属通孔电连接相邻的金属径迹层。
金属互连结构也包括延伸穿过隔离材料底层的金属触点，以电连接到MOS晶体管的源极区和漏极区。金属触点在金属触点开口中形成，金属触点开口延伸穿过隔离材料的底层以暴露源极区和漏极区。
通常，金属触点通过在隔离材料的底层上形成图案化硬掩膜来制造。图案化硬掩膜具有位于源极区和漏极区上方的若干方形开口。一旦已形成图案化硬掩膜，底部隔离层被蚀刻。
蚀刻形成暴露源极区的源极金属触点开口以及暴露漏极区的漏极金属触点开口。由于图案化硬掩膜中的方形开口，源极金属触点开口和漏极金属触点开口是方形的。随后图案化硬掩膜被去除。
此后，硅化物层在暴露的源极区和漏极区上形成，跟着形成位于源极和漏极金属触点开口中的金属触点，并接触源极和漏极硅化物层以及底部隔离层。由于方形的源极和漏极金属触点开口，金属触点是方形的。
发明内容
提供具有拉长触点的MOS晶体管结构及其制造的方法。
在公开的实施例中，半导体结构被形成有具有位于第一方向上的纵向轴线的拉长金属触点以及具有位于第二正交方向的拉长金属触点。形成接触并位于介电层上方的硬掩膜。介电层具有顶部表面。硬掩膜被蚀刻以形成第一拉长开口和第二拉长开口。第一拉长开口具有位于介电层顶部表面上方并与介电层顶部表面隔开的底部表面以及位于第一方向的纵向轴线。第二拉长开口具有位于介电层的顶部表面上方并与介电层的顶部表面隔开的底部表面以及位于第二方向的纵向轴线。第二方向基本(substantially)正交于第一方向。在已经形成第一拉长开口和第二拉长开口后，硬掩膜被蚀刻以形成第三拉长开口和第四拉长开口。第三拉长开口暴露在介电层顶部表面上的第一区域并具有位于第一方向的纵向轴线。第四拉长开口暴露在介电层顶部表面上的第二区域并具有位于第二方向的纵向轴线。
在更改实施例中，硬掩膜被形成在介电层上，以及第一图案化光致抗蚀剂(photoresist)层被形成在硬掩膜上。形成第一图案化光致抗蚀剂层包括将第一成像光投射到光致抗蚀剂层上。第一成像光在第一方向具有强偶极子分量(strong dipolecomponent)。通过第一图案化光致抗蚀剂层暴露的硬掩膜被蚀刻以形成第一拉长开口和第二拉长开口。第一拉长开口具有位于介电层的顶部表面上方并与介电层的顶部表面隔开的底部表面以及位于第一方向的纵向轴线。第二拉长开口具有位于介电层的顶部表面上方并与介电层的顶部表面隔开的底部表面以及位于第二方向的纵向轴线。第二方向基本正交于第一方向。第一图案化光致抗蚀剂层被去除，并且在第一图案化光致抗蚀剂层已被去除后在硬掩膜上形成第二图案化光致抗蚀剂层。形成第二图案化光致抗蚀剂层包括将第二成像光投射到光致抗蚀剂层上。第二成像光在第二方向具有强偶极子分量。通过第二图案化光致抗蚀剂层暴露的硬掩膜被蚀刻以形成第三拉长开口和第四拉长开口。第三拉长开口暴露在介电层顶部表面上的第一区域并具有位于第一方向的纵向轴线。第四拉长开口暴露在介电层顶部表面上的第二区域并具有位于第二方向的纵向轴线。
所述的示例半导体结构包括第一MOS晶体管的行和列。每个第一MOS晶体管具有第一拉长源极区，第一拉长源极区具有位于第一方向的纵向轴线。半导体结构也包括第二MOS晶体管的行和列。每个第二MOS晶体管具有第二拉长源极区，第二拉长源极区具有位于第二方向的纵向轴线。第二方向基本正交于第一方向。此外，半导体结构包括接触并位于第一和第二MOS晶体管上方的介电层。另外，半导体结构包括延伸穿过介电层的多个拉长金属触点。多个拉长金属触点中的第一数量拉长金属触点具有位于第一方向的纵向轴线，并且该第一数量拉长金属触点电连接到第一拉长源极区。多个拉长金属触点中的第二数量拉长金属触点具有位于第二方向的纵向轴线，并且该第二数量拉长金属触点电连接到第二拉长源极区。
附图说明
图1A是顶视图并且图1B-1E是分别从图1A沿剖面线1B-1B、1C-1C、1D-1D和1E-1E截取的横截面图，其示出形成具有拉长触点的MOS晶体管结构的示例方法的步骤。
图2A-2E、3A-3E、4A-4E、5A-5E、6A-6E、7A-7E和8A-8E是对应于图1A-1E的视图，其示出形成具有拉长触点的MOS晶体管结构的示例方法的步骤。
具体实施方式
图1A-1E到图8A-8E示出形成具有垂直拉长金属触点和水平拉长金属触点的MOS晶体管结构的示例方法的步骤。
如图1A-1E所示，方法100利用常规形成的金属栅极MOS晶体管结构108。MOS晶体管结构108依次包括半导体主体110，该半导体主体110具有单晶硅衬底区112和接触衬底区112的沟道隔离结构114。
另外，半导体主体110包括第一垂直拉长源极120V1和第二垂直拉长源极120V2、以及第一垂直拉长漏极122V1和第二垂直拉长漏极122V2，第一垂直拉长漏极122V1和第二垂直拉长漏极122V2中的每个接触衬底区112。半导体主体110也包括第一水平拉长源极120H1和第二水平拉长源极120H2，以及第一水平拉长漏极122H1和第二水平拉长漏极122H2，第一水平拉长漏极122H1和第二水平拉长漏极122H2中的每个接触衬底区112。
源极120V1、120V2、120H1和120H2以及漏极122V1、122V2、122H1和122H2中的每个具有与衬底区112的导电类型相反的导电类型。另外，源极120V1、120V2、120H1和120H2以及漏极122V1、122V2、122H1和122H2中的每个具有较轻掺杂区(lighter-doped region)LD和较重掺杂区(heavier-doped region)HD。
此外，衬底区112具有位于源极120V1和漏极122V1之间的垂直拉长沟道区124V1、位于源极120V2和漏极122V2之间的垂直拉长沟道区124V2、位于源极120H1和漏极122H1之间的水平拉长沟道区124H1以及位于源极120H2和漏极122H2之间的水平拉长沟道区124H2。
也如图1A-1E所示，MOS晶体管结构108包括垂直拉长高k栅极介电结构126V1以及垂直拉长金属栅极130V1，垂直拉长高k栅极介电结构126V1接触沟道区124V1并位于沟道区124V1上方，垂直拉长金属栅极130V1接触栅极介电结构126V1并位于沟道区124V1上方。MOS晶体管结构108附加地包括垂直拉长高k栅极介电结构126V2和垂直拉长金属栅极130V2，垂直拉长高k栅极介电结构126V2接触沟道区124V2并位于该沟道区124V2上方，垂直拉长金属栅极130V2接触栅极介电结构126V2并位于沟道区124V2上方。
MOS晶体管结构108还包括水平拉长高k栅极介电结构126H1和水平拉长金属栅极130H1，水平拉长高k栅极介电结构126H1接触沟道区124H1并位于沟道区124H1上方，水平拉长金属栅极130H1接触栅极介电结构126H1并位于沟道区124H1的上方。另外，MOS晶体管结构108包括水平拉长高k栅极介电结构126H2和水平拉长金属栅极130H2，水平拉长高k栅极介电结构126H2接触沟道区124H2并位于该沟道区124H2上方，水平拉长金属栅极130H2接触栅极介电结构126H2并位于沟道区124H2上方。
另外，MOS晶体管结构108包括横向围绕栅极130V1的侧壁隔板(spacer)132V1、横向围绕栅极130V2的侧壁隔板132V2、横向围绕栅极130H1的侧壁隔板132H1、以及横向围绕栅极130H2的侧壁隔板132H2。
MOS晶体管结构108还包括接触侧壁隔板132V1、132V2、132H1和132H2的底部介电层138。底部介电层138也接触源极120V1、120V2、120H1和120H2，漏极122V1、122V2、122H1和122H2，以及金属栅极130V1、130V2、130H1和130H2并位于它们上方。
源极120V1、漏极122V1、沟道区124V1、高k栅极介电结构126V1以及金属栅极130V1形成第一垂直取向MOS晶体管140，而源极120V2、漏极122V2、沟道区124V2、高k栅极介电结构126V2以及金属栅极130V2形成第二垂直取向MOS晶体管142。
垂直取向MOS晶体管140和142示出垂直取向MOS晶体管的阵列。虽然所述示例示出仅具有一行和两列的垂直取向MOS晶体管的阵列，但是，该阵列可以包括垂直取向MOS晶体管的许多垂直相邻行，垂直取向MOS晶体管的每一垂直相邻行具有垂直取向MOS晶体管的许多列。
另外，源极120H1、漏极122H1、沟道区124H1、高k栅极介电结构126H1以及金属栅极130H1形成第一水平取向MOS晶体管144，而源极120H2、漏极122H2、沟道区124H2、高k栅极介电结构126H2以及金属栅极130H2形成第二水平取向MOS晶体管146。
水平取向MOS晶体管144和146示出水平取向MOS晶体管的阵列。虽然所述示例示出仅具有两行和一列的水平取向MOS晶体管的阵列，但是，该阵列可以包括水平取向MOS晶体管的许多垂直相邻行，水平取向MOS晶体管的每个垂直相邻行具有水平取向MOS晶体管的许多列。
水平拉长源极120H1和120H2的宽度比垂直拉长源极120V1和120V2的宽度大近似3到10倍(3-10X)。同样，水平拉长漏极122H1和122H2的宽度比垂直拉长漏极122V1和122V2的宽度大近似3到10倍(3-10X)。此外，水平拉长沟道区124H1和124H2的沟道长度(源极和漏极之间的最短距离)比垂直拉长沟道区124V1和124V2的沟道长度大近似3到10倍(3-10X)。
如图1A-1E进一步所示，方法100以常规方式形成硬掩膜148以接触底部介电层138并位于底部介电层138的上方。在该示例中，硬掩膜148用氧化物层150和氮化物层152实现，氮化物层152接触氧化物层150并位于氧化物层150上方。
如图2A-2E所示，在形成硬掩膜148后，第一图案化光致抗蚀剂层154被形成在硬掩膜148上。第一图案化光致抗蚀剂层154具有若干垂直拉长的或开槽的开口156，开口156暴露硬掩膜148的顶部表面，并且开口156直接垂直位于垂直拉长源极120V1和120V2以及垂直拉长漏极122V1和122V2的上方。
另外，第一图案化光致抗蚀剂层154具有若干水平拉长的或开槽的开口158，开口158暴露硬掩膜148的顶部表面，并且开口158直接垂直位于水平拉长源极120H1和120H2以及水平拉长漏极122H1和122H2的上方。
间距是从特征件的一个边缘到相邻特征件的对应边缘的距离。最小间距等于2(Ki)*(λ/NA)，其中，Ki表示光刻(lithographic)工艺的难度(分辨能力)，λ表示成像光的波长，以及NA表示透镜的数值孔径。
因此，通过使用具有波长为193nm的电流生成成像光和具有数值孔径为1.35的透镜(用水浸泡)，当最小Ki接近其近似0.28的实际限值时，可以实现近似80nm的最小间距。在该示例中，垂直拉长开口156的宽度为近似20nm(其是最小间距80nm的四分之一)。还在该示例中，水平拉长开口158的宽度近似为60-200nm。
第一图案化光致抗蚀剂层154通过沉积光致抗蚀剂层、将成像光穿过称为掩膜的图案化黑色/透明玻璃板投射到光致抗蚀剂层上以在光致抗蚀剂层上形成图案化影像、并且去除影像化光致抗蚀剂区而形成，其中，影像化光致抗蚀剂区通过暴露于成像光而被软化。第一图案化光致抗蚀剂层154还可以包括底层防反射涂层。
在本示例中，穿过掩膜投射成像光以形成图案化影像，该图案化影像在垂直方向具有强偶极子分量。例如，两个离轴偶极子发射区提供强偶极子分量。具有强偶极子分量的光提供小到足以在强偶极子分量的方向精确形成的特征尺寸以及小到足以在正交于强偶极子分量的方向精确形成的特征尺寸，但是该特征尺寸仍然比在强偶极子分量方向形成的最小特征尺寸大(例如，大3到10倍(3-10X))。
因此，在图案化光致抗蚀剂层154中的与强偶极子分量的方向对准的垂直拉长开口156可以用小到能够精确形成的第一最小宽度形成，而与此同时，与强偶极子分量的方向正交的方向对准的水平拉长开口158可以以小到能够精确形成的第二最小宽度被形成在图案化光致抗蚀剂层154中，但是第二最小宽度仍然大于第一最小宽度(例如，大3到10倍(3-10X)。
如图3A-3E所示，在第一图案化光致抗蚀剂层154已经形成后，硬掩膜148的顶部表面上未覆盖区域被蚀刻以在硬掩膜148中形成若干垂直拉长的或开槽的开口160，开口160直接垂直位于垂直拉长源极120V1和120V2以及垂直拉长漏极122V1和122V2的上方。垂直拉长的或开槽的开口160的底部表面160-1与底部介电层138的顶部表面垂直间隔开。
另外，蚀刻还在硬掩膜148中形成若干水平拉长的或开槽的开口162，开口162直接垂直位于水平拉长源极120H1和120H2以及水平拉长漏极122H1和122H2的上方。水平拉长的或开槽的开口162的底部表面162-1也与底部介电层138的顶部表面垂直间隔开。
在示例中，开口160和162延伸穿过氮化物层152并暴露氧化物层150。还在该示例中，垂直拉长开口160的宽度大约是20nm，而水平拉长开口162的宽度大约是60-200nm。此后，图案化光致抗蚀剂层154以常规方式例如以灰工艺被去除。
如图4A-4E所示，在已去除图案化光致抗蚀剂层154后，第二图案化光致抗蚀剂层164被形成在硬掩膜148上。第二图案化光致抗蚀剂层164还可以包括底层防反射涂层。第二图案化光致抗蚀剂层164具有若干垂直拉长的或开槽的开口166，开口166在硬掩膜148中暴露垂直拉长开口160，并直接垂直位于垂直拉长源极120V1和120V2以及垂直拉长漏极122V1和122V2上方。在示例中，垂直拉长的或开槽的开口166暴露氧化物层150的顶部表面。
另外，第二图案化光致抗蚀剂层164具有若干水平拉长的或开槽的开口168，开口168在硬掩膜148中暴露水平拉长开口162，并直接垂直位于水平拉长源极120H1和120H2以及水平拉长漏极122H1和122H2的上方。在示例中，水平拉长的或开槽的开口168暴露氧化物层150的顶部表面。
第二图案化光致抗蚀剂层164通过以下形成：沉积光致抗蚀剂层；将成像光穿过称为掩膜的图案化黑色/透明玻璃板投射到光致抗蚀剂层上，以在光致抗蚀剂层上形成图案化影像；并去除成像的光致抗蚀剂区，该光致抗蚀剂区通过暴露到成像光而被软化。第二图案化光致抗蚀剂层164还可以包括底层防反射涂层。
在该示例中，将成像光穿过掩膜投射以形成图案化影像，图案化影像在水平方向具有强偶极子分量。例如，两个离轴偶极子发射区提供强偶极子分量。如上所述，具有强偶极子分量的光提供小到足以在强偶极子分量的方向精确形成的特征大小、以及小到足以在正交于强偶极子分量的方向精确形成的特征大小，但是特征大小比在强偶极子分量方向形成的最小特征大小大(例如，大3到10倍(3-10X))。
因此，在图案化光致抗蚀剂层164中的与强偶极子分量的方向对准的水平拉长开口168可以用小到能够精确形成的第一最小宽度形成，而与此同时，与强偶极子分量的方向正交的方向对准的垂直拉长开口156可以以小到能够精确形成的第二最小宽度被形成在图案化光致抗蚀剂层154中，但是第二最小宽度仍然大于第一最小宽度(例如，大3到10倍(3-10X))。
虽然水平拉长开口168可以用小到能够精确形成的第一最小宽度形成，但是水平拉长开口168被替代地形成为具有精确定义的放宽的宽度(例如，大约等于第二最小宽度)。在该示例中，放宽的宽度可以是从60nm到200nm。另外，虽然垂直拉长的开口166可以用第二最小宽度形成，但是垂直拉长的开口166也可以被形成为具有精确定义的放宽宽度。
如图5A-5E所示，在第二图案化光致抗蚀剂层164已经被形成后，硬掩膜148的未覆盖区域被蚀刻以在硬掩膜148中形成若干垂直拉长的或开槽的开口170，开口170暴露底部介电层138的顶部表面并且直接垂直位于垂直拉长源极120V1和120V2以及垂直拉长漏极122V1和122V2的上方。
另外，蚀刻也在硬掩膜148中形成若干水平拉长的或开槽的开口172，开口172暴露底部介电层138的顶部表面并直接垂直位于水平拉长源极120H1和120H2以及水平拉长漏极122H1和122H2的上方。在该示例中，水平拉长开口172的宽度大约为60-200nm。此后，图案化光致抗蚀剂层164以常规方式例如以灰工艺被去除。
如图6A-6E所示，在已去除图案化光致抗蚀剂层164后，在底部介电层138的顶部表面上的未覆盖区域被蚀刻。蚀刻在底部介电层138中形成若干垂直拉长金属触点开口180，垂直拉长金属触点开口180暴露垂直拉长源极区120V1和120V2的重度掺杂区HD的几乎所有顶部表面以及垂直拉长漏极区122V1和122V2的重度掺杂区HD的几乎所有顶部表面。
蚀刻还在底部介电层138中形成若干水平拉长金属触点开口182，水平拉长金属触点开口182暴露水平拉长源极区120H1和120H2的重度掺杂区HD的几乎所有顶部表面以及水平拉长漏极区122H1和122H2的重度掺杂区HD的几乎所有顶部表面。
在示例中，由于硬掩膜开口170的宽度，垂直拉长金属触点开口180中的每个具有约20nm的宽度，而由于硬掩膜开口172的宽度，水平拉长金属触点开口182中的每个具有约60-200nm的宽度。在金属触点开口180和182已形成后，硬掩膜148的剩余部分以常规方式被去除。
如图7A-7E所示，一旦已经去除硬掩膜148，源极金属硅化物区186V1按常规被形成以接触源极区120V1并位于源极区120V1上方，源极金属硅化物区186V2按常规被形成以接触源极区120V2并位于源极区120V2上方，源极金属硅化物区186H1按常规被形成以接触源极区120H1并位于源极区120H1上方，以及源极金属硅化物区186H2按常规被形成以接触源极区120H2并位于源极区120H2上方。
此外，漏极金属硅化物区188V1按常规被形成以接触漏极区122V1并位于漏极区122V1上方，漏极金属硅化物区188V2按常规被形成以接触漏极区122V2并位于漏极区122V2上方，漏极金属硅化物区188H1按常规被形成以接触漏极区122H1并位于漏极区122H1上方，漏极金属硅化物区188H2按常规被形成以接触漏极区122H2并位于漏极区122H2上方。
在源极金属硅化物区186V1、186V2、186H1和186H2以及漏极金属硅化物区188V1、188V2、188H1和188H2已经被形成后，金属接触层190诸如钨(W)层被沉积以接触底部介电层138的顶部表面并填充在底部介电层138中的金属触点开口180和182。
如图8A-8E所示，在金属接触层190已经被形成后，金属接触层190以常规方式诸如用化学机械抛光被平坦化，以暴露底部介电层138的顶部表面。平坦化形成在金属触点开口180中的垂直拉长的金属触点192和在金属触点开口182中的水平拉长金属触点194。
垂直拉长金属触点192电连接到源极金属硅化物区186V1和186V2以及漏极金属硅化物区188V1和188V2。水平拉长金属触点194电连接到源极金属硅化物区186H1和186H2以及漏极金属硅化物区188H1和188H2。
上述垂直拉长结构中的每个具有位于垂直方向上的纵向轴线，而上述水平拉长结构中的每个具有位于水平方向的纵向轴线。随后，方法100继续常规步骤以完成金属互连结构的形成。
因此，半导体结构196经形成包括第一MOS晶体管140和142的行和列，其中，第一MOS晶体管140和142具有位于第一方向的纵向轴线的拉长源极区120V1和120V2以及拉长漏极区122V1和122V2。
半导体结构196也包括第二MOS晶体管144和146的行和列，其中，其中第二MOS晶体管144和146具有拉长源极区120H1和120H2以及拉长漏极区122H1和122H2，其具有位于和第一方向基本正交的第二方向的纵向轴线。此外，半导体结构包括接触并位于第一和第二MOS晶体管140、142、144和146上方的介电层138。
另外，半导体结构196包括第一数量的垂直拉长金属触点192和延伸穿过介电层138的第二数量的水平拉长金属触点。垂直拉长金属触点192具有位于第一方向的纵向轴线，垂直拉长金属触点192具有第一宽度并电连接到垂直拉长源极区120V1和120V2以及垂直拉长漏极区122V1和122V2。
水平拉长金属触点194具有位于第二方向的纵向轴线，水平拉长金属触点194具有基本大于第一宽度的第二宽度并电连接到水平拉长源极区120H1和120H2以及水平拉长漏极区122H1和122H2。
上述方法的一个优点是垂直拉长金属触点和水平拉长金属触点两者可以以很好的光刻精度形成。第一光致抗蚀剂掩膜间接地限定具有最高光刻精度的垂直拉长金属触点的宽度和水平拉长金属触点的长度，并且第二光致抗蚀剂掩膜间接地限定具有最高光刻精度的垂直拉长金属触点的长度和水平拉长金属触点的宽度。
另一优点是垂直拉长的金属触点开口180暴露源极和漏极金属硅化物区186V1、186V2、188V1和188V2的基本所有顶部表面，而水平拉长的金属触点开口182暴露源极和漏极金属硅化物区186H1、186H2、188H1和188H2的基本所有顶部表面。结果，由于更大的表面面积，当与方形金属触点相比时，提供了减少的接触电阻的方法。
虽然本方法就垂直取向和水平取向MOS晶体管进行了描述，但是本方法可以应用于第一组的取向基本正交于第二组取向的任何两组MOS晶体管。
本领域中的技术人员应当明白在本发明要求保护的范围内，可以对所述示例实施例进行更改，并且许多其他实施例也是可能的。

Claims (3)

1.一种半导体结构，其包括：
第一MOS晶体管的行和列，每个第一MOS晶体管具有第一拉长源极区，所述第一拉长源极区具有位于第一方向的纵向轴线；
第二MOS晶体管的行和列，每个第二MOS晶体管具有第二拉长源极区，所述第二拉长源极区具有位于第二方向的纵向轴线，所述第二方向基本正交于所述第一方向；
介电层，所述介电层接触并位于所述第一和第二MOS晶体管上方；以及
延伸穿过所述介电层的多个拉长金属触点，所述多个拉长金属触点中的第一数量的拉长金属触点具有位于所述第一方向的纵向轴线并电连接到所述第一拉长源极区，所述多个拉长金属触点中的第二数量的拉长金属触点具有位于所述第二方向的纵向轴线并电连接到所述第二拉长源极区。
2.根据权利要求1所述的结构，其还包括：
多个第一硅化物区，所述多个第一硅化物区接触所述第一拉长源极区和所述多个拉长金属触点中的所述第一数量的拉长金属触点；以及
多个第二硅化物区，所述多个第二硅化物区接触所述第二拉长源极区和所述多个拉长金属触点中的所述第二数量的拉长金属触点。
3.根据权利要求2所述的结构，其中所述多个拉长金属触点的所述第一数量的拉长金属触点中的每个具有基本小于所述多个拉长金属触点的所述第二数量的拉长金属触点中的每个的宽度的宽度。
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