TW201913879A - 半導體裝置結構 - Google Patents

半導體裝置結構 Download PDF

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TW201913879A
TW201913879A TW107114687A TW107114687A TW201913879A TW 201913879 A TW201913879 A TW 201913879A TW 107114687 A TW107114687 A TW 107114687A TW 107114687 A TW107114687 A TW 107114687A TW 201913879 A TW201913879 A TW 201913879A
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Taiwan
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layer
semiconductor device
gate
fin
isolation
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TW107114687A
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TWI755527B (zh
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朱峯慶
李威養
楊豐誠
陳燕銘
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台灣積體電路製造股份有限公司
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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

提供半導體裝置結構。半導體裝置結構包括基板，其具有基底與第一鰭狀結構於基底上。半導體裝置結構包括隔離層於基底上。第一鰭狀結構部份地位於隔離層中。半導體裝置結構包括第一閘極結構，其位於第一鰭狀結構上並橫越第一鰭狀結構。半導體裝置結構包括第一源極結構與第一汲極結構，其位於第一鰭狀結構上與第一閘極結構的兩側上。第一源極結構與第一汲極結構之組成為n型導電材料。半導體裝置結構包括蓋層，其覆蓋第一源極結構與第一汲極結構。蓋層摻雜IIIA族元素。

Description

半導體裝置結構
本發明實施例關於半導體裝置結構，更特別關於源極與汲極結構上的蓋層。
半導體積體電路產業已經歷快速成長。積體電路材料與設計的技術進步，使每一代的積體電路比前一代的積體電路更小且電路更複雜。然而這些進展會增加積體電路製程的複雜度。
隨著積體電路進展，功能密度(比如固定晶片面積中的內連線裝置數目)通常隨著幾何尺寸(比如製程形成的最小構件)縮小而增加。尺寸縮小的製程通常有利於增加產能並降低相關成本。
然而結構尺寸持續縮小(比如兩相鄰鰭狀結構之間的距離持續縮小)，因此越來越難進行製程。如此一來，如何形成可信且越來越小的半導體裝置為一大挑戰。
本發明一實施例提供之半導體裝置結構，包括：基板，具有基底與第一鰭狀結構於基底上；隔離層，位於基底上，其中第一鰭狀結構部份地位於隔離層中；第一閘極結構，位於第一鰭狀結構上並橫越第一鰭狀結構；第一源極結構與第一汲極結構，位於第一鰭狀結構上與第一閘極結構的兩側上， 其中第一源極結構與第一汲極結構之組成為n型導電材料；以及蓋層，覆蓋第一源極結構與第一汲極結構，其中蓋層摻雜IIIA族元素。
D1、D2、D3‧‧‧距離
G、G1、G2、G11、G22‧‧‧閘極結構
I-I’、II-II’、III-III’、IV-IV’、V-V’‧‧‧剖線
M1、M2‧‧‧遮罩層
P1、P2、P3、R、152、154‧‧‧溝槽
R1、R2、R3、R4‧‧‧穿孔
S‧‧‧側壁
T1、T2‧‧‧厚度
W1、W2‧‧‧寬度
110‧‧‧基板
111‧‧‧基底
112、114、116、118‧‧‧鰭狀結構
120‧‧‧隔離層
130、222、224‧‧‧閘極介電層
140‧‧‧閘極
142、164a‧‧‧上表面
150‧‧‧間隔物層
162P、164N‧‧‧應力體
164b‧‧‧下表面
164c‧‧‧側壁
170‧‧‧蓋層
180‧‧‧蝕刻停止層
190‧‧‧介電層
210‧‧‧隔離結構
232、234‧‧‧功函數金屬層
242、244‧‧‧閘極層
252、254‧‧‧接點插塞
第1A至1N圖係一些實施例中，用於形成半導體裝置結構的製程其多種階段的透視圖。
第1K-1圖係一些實施例中，半導體裝置結構沿著第1K圖中剖線I-I’的剖視圖。
第1N-1圖係一些實施例中，半導體裝置結構沿著第1N圖中剖線I-I’的剖視圖。
第1N-2圖係一些實施例中，半導體裝置結構沿著第1N圖中剖線II-II’的剖視圖。
第1N-3圖係一些實施例中，半導體裝置結構沿著第1N圖中剖線III-III’的剖視圖。
第1N-4圖係一些實施例中，半導體裝置結構沿著第1N圖中剖線IV-IV’的剖視圖。
第1N-5圖係一些實施例中，半導體裝置結構沿著第1N圖中剖線V-V’的剖視圖。
下述揭露內容提供許多不同實施例或實例以實施本發明的不同結構。下述特定構件與排列的實施例係用以簡化本發明而非侷限本發明。舉例來說，形成第一構件於第二構件上的敘述包含兩者直接接觸，或兩者之間隔有其他額外構件而 非直接接觸。此外，本發明的多個實例可採用重複標號及/或符號使說明簡化及明確，但這些重複不代表多種實施例中相同標號的元件之間具有相同的對應關係。
此外，空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。應理解在方法之前、之中、與之後可進行額外步驟，且方法的其他實施例可置換或省略下述的一些步驟。
鰭狀物可由任何合適方法圖案化。舉例來說，鰭狀物的圖案化方法採用一或多道光微影製程，包含雙重圖案化或多重圖案化製程。一般而言，雙重圖案化或多重圖案化製程結合光微影與自對準製程，其產生的圖案間距可小於單一的直接光微影製程所能得到的最小間距。舉例來說，一實施例形成犧牲層於基板上，並採用光微影製程圖案化犧牲層。採用自對準製程，沿著圖案化的犧牲層側壁形成間隔物。接著移除犧牲層，再以保留的間隔物圖案化鰭狀物。
第1A至1N圖係一些實施例中，用於形成半導體裝置結構的製程其多種階段的透視圖。如第1A圖所示的一些實施例，提供基板110。舉例來說，基板110包含半導體基板。舉例來說，半導體基板包含半導體晶圓(如矽晶圓)或半導體晶圓的一部份。
在一些實施例中，基板110之組成為半導體元素材 料，比如單晶、多晶、或非晶結構的矽或鍺。在一些其他實施例中，基板110之組成為半導體化合物如碳化矽、砷化鎵、磷化鎵、磷化銦、或砷化銦；半導體合金如矽鍺、磷砷化鎵、或上述之組合。基板110亦可包含多層的半導體材料、絕緣層上半導體基板(絕緣層上矽或絕緣層上鍺)、或上述之組合。
如第1A圖所示的一些實施例，基板110具有基底111與鰭狀結構112、114、116、與118。在一些實施例中，鰭狀結構112、114、116、與118位於基底111上。在一些實施例中，鰭狀結構112、114、116、與118彼此之間分隔有溝槽P1、P2、與P3。
在一些實施例中，鰭狀結構112與114之間的距離D1，小於鰭狀結構114與116之間的距離D2。在一些實施例中，鰭狀結構116與118之間的距離D3小於距離D2。
如第1B圖所示的一些實施例，隔離層120形成於基底111上。在一實施例中，每一鰭狀結構112、114、116、或118部份地位於隔離層120中。在一些實施例中，隔離層120包含氧化物如氧化矽。在一些實施例中，隔離層120的形成方法為化學氣相沉積製程與回蝕刻製程。
如第1B圖所示的一些實施例，閘極介電層130與閘極140形成於鰭狀結構112、114、116、與118以及隔離層120上。在一些實施例中，閘極140形成於閘極介電層130上。
在一些實施例中，閘極介電層130位於閘極140以及鰭狀結構112、114、116、與118之間。在一些實施例中，閘極介電層130亦位於閘極140與隔離層120之間。在一些實施例 中，閘極140與閘極介電層130一起形成閘極結構G。在一些實施例中，閘極結構G的部份位於溝槽P1、P2、與P3中。
在一些實施例中，閘極介電層130之組成為氧化矽。在一些實施例中，閘極介電層130之形成方法採用化學氣相沉積製程與蝕刻製程。在一些實施例中，閘極140之組成為多晶矽。在一些實施例中，閘極140的形成方法採用化學氣相沉積製程與蝕刻製程。
如第1B圖所示的一些實施例，間隔物層150形成於閘極結構G的側壁S上。在一些實施例中，間隔物層150圍繞閘極結構G。在一些實施例中，間隔物層150位於鰭狀結構112、114、116、與118以及隔離層120上。
在一些實施例中，間隔物層150包含絕緣材料如氧化矽、氮化矽、氮氧化矽、或碳化矽。在一些實施例中，間隔物層150的形成方法包括沉積製程與非等向蝕刻製程。
如第1C圖所示的一些實施例，遮罩層M1形成於隔離層120上以覆蓋鰭狀結構112與114。在一些實施例中，遮罩層M1之組成為介電材料。介電材料可包含氮化矽、氮氧化矽、碳化矽、另一合適介電材料、或上述之組合。
在一些實施例中，遮罩材料層沉積於隔離層120、鰭狀結構112、114、116、與118、以及閘極結構G上。遮罩材料層的沉積方法可採用化學氣相沉積製程、物理氣相沉積製程、旋轉塗佈製程、另一可行製程、或上述之組合。之後可採用光微影製程與蝕刻製程移除部份的遮罩材料層。舉例來說，圖案化光阻層(未圖示)可形成於遮罩材料層上，並蝕刻圖案化 光阻層未覆蓋的部份遮罩材料層。如此一來，可形成遮罩層M1。
接著如第1C圖所示的一些實施例，移除隔離層120之外且閘極結構G與間隔物層150未覆蓋的部份鰭狀結構116與118。在一些實施例中，移除製程包含蝕刻製程。
如第1D圖所示的一些實施例，應力體162P形成於鰭狀結構116與118上。在一些實施例中，應力體162P直接接觸鰭狀結構116與118。在一些實施例中，應力體162P位於閘極結構G的兩側上。在一些實施例中，應力體162P之一者為源極結構，而另一者為汲極結構。
在一些實施例中，源極結構與汲極結構之組成為p型導電材料。p型導電材料包含矽鍺或另一合適的p型導電材料。在一些實施例中，應力體162P的形成方法採用磊晶製程。在一些實施例中，應力體162P摻雜IIIA族元素。IIIA族元素包含硼或另一合適材料。
如第1E圖所示的一些實施例，移除遮罩層M1。移除製程包含蝕刻製程或另一合適製程。如第1E圖所示的一些實施例，在移除製程後，形成遮罩層M2於隔離層120上以覆蓋鰭狀結構116與118以及應力體162P。在一些實施例中，遮罩層M2之組成為介電材料。介電材料可包含氮化矽、氮氧化矽、碳化矽、另一合適的介電材料、或上述之組合。
在一些實施例中，遮罩材料層沉積於隔離層120、鰭狀結構112、114、116、與118、閘極結構G、以及應力體162P上。遮罩材料層的沉積方法可採用化學氣相沉積製程、物理氣 相沉積製程、旋轉塗佈製程、另一可行製程、或上述之組合。之後可移除部份的遮罩材料層，且移除方法可採用光微影製程與蝕刻製程。舉例來說，圖案化光阻層(未圖示)可形成於遮罩材料層上，並蝕刻圖案化光阻層未覆蓋的部份遮罩材料層。如此一來，可形成遮罩層M2。
之後如第1E圖所示的一些實施例，移除隔離層120之外且閘極結構G與間隔物層150未覆蓋的部份鰭狀結構112與114。在一些實施例中，移除製程包含蝕刻製程。
如第1F圖所示的一些實施例中，應力體164N形成於鰭狀結構112與114上。在一些實施例中，應力體164N直接接觸鰭狀結構112與114。在一些實施例中，應力體164N位於閘極結構G的兩側上。在一些實施例中，應力體164N之一者為源極結構，而另一者為汲極結構。在一些實施例中，每一應力體164N具有上表面164a、側壁164c、與下表面164b。
在一些實施例中，應力體164N的組成為n型導電材料。N型導電材料包括磷化矽或另一合適的n型導電材料。在一些實施例中，應力體164N之形成方法採用磊晶製程。
在一些實施例中，應力體164N摻雜VA族元素。VA族元素包含磷、銻、或另一合適的VA族材料。在一些實施例中，VA族元素(如磷)的濃度介於約3E21原子/cm3至約7E21原子/cm3之間。如第1F圖所示的一些實施例，移除遮罩層M2。移除製程包含蝕刻製程或另一合適製程。
如第1G圖所示的一些實施例，蓋層170形成於應力體164N上。在一些實施例中，蓋層170順應性地覆蓋應力體 164N。在一些實施例中，蓋層170直接接觸應力體164N與隔離層120。
在一些實施例中，蓋層170之組成為p型導電材料，比如矽鍺或類似物。在一些實施例中，蓋層170摻雜IIIA族元素，其與摻雜於應力體162P中的IIIA族元素相同。IIIA族元素包含硼或另一合適材料。
在一些實施例中，蓋層170中IIIA族元素(如硼)的第一平均濃度，小於應力體162P中IIIA族元素的第二平均濃度。在一些實施例中，第一平均濃度介於約4E20原子/cm3至約9E20原子/cm3之間。
在一些實施例中，第二平均濃度介於約1E21原子/cm3至約9E21原子/cm3之間。在一些實施例中，第一平均濃度小於摻雜於應力體164N中的VA族元素濃度。
在一些實施例中，蓋層170與應力體164N的組成為不同材料。在一些實施例中，後續蝕刻製程中的蓋層170其蝕刻速率低於應力體164N其蝕刻速率。如此一來，一些實施例的蓋層170可避免下方的應力體164N在後續蝕刻製程中受損。
在一些實施例中，蓋層170的平均厚度介於約2nm至約6nm之間。在一些實施例中，蓋層170的平均厚度介於約2nm至約4nm之間。在一些實施例中，蓋層170在應力體164N的上表面164a上(或與應力體164N的上表面164a相鄰)的厚度T1，大於蓋層170與應力體164N之下表面164b相鄰的厚度T2。在一些實施例中，蓋層170的形成方法採用磊晶製程。
在一些實施例中，蓋層170與應力體164N的總寬度 W1大於應力體162P的寬度W2。在一些實施例中，蓋層170覆蓋應力體164N的上表面164a與側壁164c。在一些實施例中，蓋層170未覆蓋應力體164N的下表面164b。
如第1H圖所示的一些實施例，蝕刻停止層180沉積於閘極結構G、間隔物層150、隔離層120、蓋層170、與應力體162P上。在一些實施例中，蝕刻停止層180直接接觸閘極結構G、間隔物層150、隔離層120、蓋層170、與應力體162P。
在一些實施例中，蓋層170位於蝕刻停止層180與應力體164N之間，以分隔蝕刻停止層180與應力體164N。在一些實施例中，蓋層170的平均厚度小於蝕刻停止層180的平均厚度。
如第1H圖所示的一些實施例，介電層190形成於蝕刻停止層180上。在一些實施例中，介電層190包含氧化物如氧化矽。在一些實施例中，介電層190的形成方法為化學氣相沉積製程。
在第1I圖所示的一些實施例中，接著在介電層190上進行平坦化製程，直到露出閘極140的上表面142。在一些實施例中，平坦化製程包括化學機械研磨製程。
如第1J圖所示的一些實施例，移除鰭狀結構114與116之間的隔離層120、閘極介電層130、閘極140、間隔物層150、蝕刻停止層180、與介電層190的部份。
在一些實施例中，移除製程形成溝槽R，其穿過鰭狀結構114與116之間的閘極介電層130、閘極140、間隔物層150、蝕刻停止層180、與介電層190。在一些實施例中，溝槽R 穿越至鰭狀結構114與116之間的隔離層120中。
在一些實施例中，溝槽R將閘極結構G分為閘極結構G1與閘極結構G2。在一些實施例中，閘極結構G1位於鰭狀結構112與114上。在一些實施例中，閘極結構G2位於鰭狀結構116與118上。
在一些實施例中，移除製程包括光微影製程與蝕刻製程。在一些實施例中，蝕刻製程包括乾蝕刻製程。在一些實施例中，乾蝕刻製程採用的製程氣體包含氯氣及/或四氯化矽。
第1K-1圖係一些實施例中，半導體裝置結構沿著沿著第1K圖中剖線I-I’的剖視圖。如第1K與1K-1圖所示的一些實施例，隔離結構210形成於溝槽R中。在一些實施例中，隔離結構210位於閘極結構G1與G2之間，並位於應力體164N與162P之間。在一些實施例中，隔離結構210穿過介電層190。
在一些實施例中，隔離結構210直接接觸閘極結構G1與G2(如閘極140與閘極介電層130)、蓋層170、應力體162P、蝕刻停止層180、間隔物層150、介電層190、與隔離層120。
在一些實施例中，蓋層170與應力體164N延伸至隔離結構210中。在一些實施例中，應力體162P延伸至隔離結構210中。在一些實施例中，蓋層170分隔隔離結構210與應力體164N。在一些實施例中，蓋層170直接接觸隔離結構210。
在一些實施例中，隔離結構210之組成為絕緣材料如氧化矽、氮化矽、氮氧化矽、碳化矽、或類似物。在一些實施例中，隔離結構210與介電層190之材料組成不同。在一些實 施例中，隔離結構210與介電層190之材料組成相同。在一些實施例中，隔離結構210之形成方法為沉積製程與平坦化製程。
如第1L圖所示的一些實施例，移除閘極結構G1與G2。在一些實施例中，移除製程包含濕蝕刻製程。在一些實施例中，移除製程之後形成溝槽152與154於間隔物層150中。在一些實施例中，溝槽152露出鰭狀結構112與114的部份。在一些實施例中，溝槽154露出鰭狀結構116與118的部份。
如第1M圖所示的一些實施例，閘極介電層222與224分別形成於溝槽152與154中，以覆蓋溝槽152與154的下表面。閘極介電層222與224之組成為氧化矽、氮化矽、氮氧化矽、高介電常數的介電材料、另一合適的介電材料、或上述之組合。
高介電常數的介電材料包含氧化鉿、氧化鋯、氧化鋁、氧化鉿-氧化鋁合金、氧化鉿矽、氮氧化鉿矽、氧化鉿鉭、氧化鉿鈦、氧化鉿鋯、另一合適的高介電常數材料、或上述之組合。
之後如第1M圖所示的一些實施例，分別沉積功函數金屬層232與234於閘極介電層222與224上。功函數金屬層232與234提供電晶體所需的功函數，以增進裝置效能如改善臨界電壓。
在形成n型金氧半電晶體的實施例中，功函數金屬層234可為n型金屬，其可提供適用於裝置的功函數值如小於或等於約4.5eV。n型金屬之組成可為金屬、金屬碳化物、金屬氮化物、或上述之組合。舉例來說，n型金屬之組成為鉭、氮化鉭、或上述之組合。
在形成p型金氧半電晶體的實施例中，功函數金屬層234可為p型金屬，其可提供適用於裝置的功函數值如大於或等於約4.8eV。p型金屬之組成可為金屬、金屬碳化物、金屬氮化物、其他合適材料、或上述之組合。
舉例來說，p型金屬之組成為鈦、氮化鈦、其他合適材料、或上述之組合。在一些實施例中，功函數金屬層232與234之形成方法為沉積製程與平坦化製程。沉積製程包含物理氣相沉積製程、化學氣相沉積製程、原子層沉積製程、電鍍製程、另一合適方法、或上述之組合。
在一些實施例中，功函數金屬層232與234之組成為不同材料。在一些實施例中，分開形成功函數金屬層232與234。舉例來說，在形成功函數金屬層232時，以第一遮罩層(未圖示)覆蓋溝槽154；且在形成功函數金屬層234時，以第二遮罩層(未圖示)覆蓋溝槽152。
在一些實施例中，功函數金屬層232與234之組成為相同材料。在一些實施例中，功函數金屬層232與234係由相同的沉積製程形成。
之後如第1M圖所示的一些實施例，閘極層242與244(又稱作金屬閘極層)分別沉積於功函數金屬層232與234上，以填入溝槽152與154。在一些實施例中，閘極層242與244之組成為合適的金屬材料如鋁、鎢、金、鉑、鈷、另一合適金屬、上述之合金、或上述之組合。
在一些實施例中，閘極242、功函數金屬層232、與閘極介電層222一起形成閘極結構G11。在一些實施例中，閘 極244、功函數金屬層234、與閘極介電層224一起形成閘極結構G22。
第1N-1圖係一些實施例中，半導體裝置結構沿著第1N圖中剖線I-I’的剖視圖。第1N-2圖係一些實施例中，半導體裝置結構沿著第1N圖中剖線II-II’的剖視圖。第1N-3圖係一些實施例中，半導體裝置結構沿著第1N圖中剖線III-III’的剖視圖。第1N-4圖係一些實施例中，半導體裝置結構沿著第1N圖中剖線IV-IV’的剖視圖。第1N-5圖係一些實施例中，半導體裝置結構沿著第1N圖中剖線V-V’的剖視圖。
如第1N圖與第1N-1至1N-4圖所示的一些實施例，穿孔R1與R2形成於介電層190、蝕刻停止層180、與蓋層170中。在一些實施例中，穿孔R1與R2穿過介電層190、蝕刻停止層180、與蓋層170，並延伸至應力體164N。
如第1N與1N-5圖所示的一些實施例，穿孔R3與R4形成於介電層190及蝕刻停止層180中。在一些實施例中，穿孔R3與R4穿過介電層190與蝕刻停止層180，並延伸至應力體162P。
在一些實施例中，穿孔R1、R2、R3、與R4的形成方法採用蝕刻製程。由於蓋層170薄(比如小於或等於6nm)，蝕刻製程可輕易移除蓋層170。
之後如第1N圖與第1N-1至1N-5圖所示的一些實施例，接點插塞252形成於穿孔R1與R2中，而接點插塞254形成於穿孔R3與R4中。在一些實施例中，接點插塞252穿過介電層190、蝕刻停止層180、與蓋層170以達應力體164N。在一些實 施例中，每一接點插塞252電性連接至其下方的應力體164N。
在一些實施例中，接點插塞254穿過介電層190與蝕刻停止層180以達應力體162P。在一些實施例中，每一接點插塞254電性連接至其下方的應力體162P。在一些實施例中，接點插塞252與254之組成為合適的導電材料如金屬材料(比如鋁、鎢、金、鉑、鈷、另一合適金屬、上述之合金、或上述之組合)。
在一些實施例中，提供半導體裝置結構與其形成方法。用於形成半導體裝置結構的方法形成具有n型導電性的蓋層於源極結構與汲極結構(或應力體上)，以在後續蝕刻製程中避免損傷源極結構與汲極結構。蓋層摻雜IIIA族元素。
在一些實施例中，提供半導體裝置結構。半導體裝置結構包括基板，其具有基底與第一鰭狀結構於基底上。半導體裝置結構包括隔離層於基底上。第一鰭狀結構部份地位於隔離層中。半導體裝置結構包括第一閘極結構，其位於第一鰭狀結構上並橫越第一鰭狀結構。半導體裝置結構包括第一源極結構與第一汲極結構，其位於第一鰭狀結構上與第一閘極結構的兩側上。第一源極結構與第一汲極結構之組成為n型導電材料。半導體裝置結構包括蓋層，其覆蓋第一源極結構與第一汲極結構。蓋層摻雜IIIA族元素。
在一些實施例中，上述半導體裝置結構的蓋層組成為矽鍺。
在一些實施例中，上述半導體裝置結構的IIIA族元素為硼。
在一些實施例中，上述半導體裝置結構的n型導電材料為磷化矽。
在一些實施例中，上述半導體裝置結構的蓋層其與第一源極結構的上表面相鄰的厚度，大於蓋層其與第一源極結構的下表面相鄰的厚度。
在一些實施例中，上述半導體裝置結構的基板更包括第二鰭狀結構於基底上，且半導體裝置構更包括：第二閘極結構，位於第二鰭狀結構上並橫越第二鰭狀結構；以及第二源極結構與第二汲極結構，位於第二鰭狀結構上以及第二閘極結構的兩側上；其中第二源極結構與第二汲極結構之組成為p型導電材料，且第二源極結構與第二汲極結構摻雜IIIA族元素。
在一些實施例中，上述半導體裝置結構更包括介電層於隔離層、第一源極結構、第一汲極結構、第二源極結構、與第二汲極結構上，其中第一閘極結構與第二閘極結構埋置於介電層中；以及隔離結構，位於第一閘極結構與第二閘極結構之間、位於第一源極結構與第二源極結構之間、以及位於第一汲極結構與第二汲極結構之間，其中隔離結構穿過介電層。
在一些實施例中，上述半導體裝置結構的隔離結構直接接觸第一閘極結構、第二閘極結構、蓋層、介電層、與隔離層。
在一些實施例中，上述半導體裝置結構的隔離結構更直接接觸第二源極結構與第二汲極結構。
在一些實施例中，上述半導體裝置結構的蓋層延 伸至隔離結構中，且蓋層分開隔離結構與第一源極結構，並分開隔離結構與第一汲極結構。
在一些實施例中，上述半導體裝置結構的蓋層直接接觸第一源極結構、第一汲極結構、隔離層、與隔離結構。
在一些實施例中，上述半導體裝置結構的蓋層中IIIA族元素的第一平均濃度，低於第二源極結構與第二汲極結構中IIIA族元素的第二平均濃度。
在一些實施例中，上述半導體裝置結構更包括接點插塞穿過蓋層以達第一源極結構，以電性連接至第一源極結構。
在一些實施例中，提供半導體裝置結構。半導體裝置結構包括基板，其具有基底與第一鰭狀結構位於基底上。半導體裝置結構包括隔離層於基底上。第一鰭狀結構部份地位於隔離層中。半導體裝置結構包括第一閘極結構，其位於第一鰭狀結構上並橫越第一鰭狀結構。半導體裝置結構包括第一應力體與第二應力體，其位於第一鰭狀結構上與第一閘極結構的兩側上。第一應力體與第二應力體之組成為n型導電材料。半導體裝置結構包括蓋層，其覆蓋第一應力體的第一上表面與第一側壁，以及第二應力體的第二上表面與第二側壁。蓋層摻雜IIIA族元素。在一實施例中，蓋層未覆蓋第一應力體的第一下表面與第二應力體的第二下表面。
在一些實施例中，上述半導體裝置結構的基板更包括第二鰭狀結構於基底上，且半導體裝置結構更包括：第二閘極結構，位於第二鰭狀結構上並橫越第二鰭狀結構；以及第 三應力體與第四應力體，位於第二鰭狀結構上與第二閘極結構的兩側上；其中第三應力體與第四應力體之組成為p型導電材料，且第三應力體與第四應力體摻雜IIIA元素；介電層，位於隔離層、第一應力體、第二應力體、第三應力體、與第四應力體上，其中第一閘極結構與第二閘極結構埋置於介電層中；以及隔離結構，位於第一閘極結構與第二閘極結構之間、位於第一應力體與第三應力體之間、以及位於第二應力體與第四應力體之間，其中隔離結構穿過介電層。
在一些實施例中，上述半導體裝置結構的蓋層與第一應力體延伸至隔離結構中。
在一些實施例中，上述半導體置結構的第三應力體延伸至隔離結構中。
在一些實施例中，上述半導體裝置結構更包括蝕刻停止層，覆蓋蓋層、第一應力體、與第二應力體，其中蓋層分隔蝕刻停止層與第一應力體，並分隔蝕刻停止層與第二應力體。
在一些實施例中，上述半導體裝置結構的蓋層比蝕刻停止層薄。
在一些實施例中，提供用以形成半導體裝置結構的方法。方法包括提供基板，其具有基底、第一鰭狀結構、與第二鰭狀結構。第一鰭狀結構與第二鰭狀結構位於基底上。方法包括隔離層於基底上。第一鰭狀結構與第二鰭狀結構部份地位於隔離層中。方法包括形成閘極結構於第一鰭狀結構與第二鰭狀結構上，且閘極結構橫越第一鰭狀結構與第二鰭狀結構。 方法包括形成源極結構與汲極結構於第一鰭狀結構上與閘極結構的兩側上。源極結構與汲極結構之組成為n型導電材料。方法包括形成蓋層於源極結構與汲極結構上。蓋層摻雜IIIA族元素。方法包括形成介電層於隔離層、源極結構、與汲極結構上。方法包括移除第一鰭狀結構與第二鰭狀結構之間的閘極結構與介電層的部份，以形成溝槽於閘極結構與介電層中。溝槽將閘極結構分為第一閘極結構與第二閘極結構，其各自位於第一鰭狀結構與第二鰭狀結構上。方法包括形成隔離結構於溝槽中。隔離結構位於第一閘極結構與第二閘極結構之間，並位於蓋層與第二鰭狀結構之間。
本發明已以數個實施例揭露如上，以利本技術領域中具有通常知識者理解本發明。本技術領域中具有通常知識者可採用本發明為基礎，設計或調整其他製程與結構，用以實施實施例的相同目的，及/或達到實施例的相同優點。本技術領域中具有通常知識者應理解上述等效置換並未偏離本發明之精神與範疇，並可在未偏離本發明之精神與範疇下進行這些不同的改變、置換、與調整。

Claims (1)

  1. 一種半導體裝置結構，包括：一基板，具有一基底與一第一鰭狀結構於該基底上；一隔離層，位於該基底上，其中該第一鰭狀結構部份地位於該隔離層中；一第一閘極結構，位於該第一鰭狀結構上並橫越該第一鰭狀結構；一第一源極結構與一第一汲極結構，位於該第一鰭狀結構上與該第一閘極結構的兩側上，其中該第一源極結構與該第一汲極結構之組成為n型導電材料；以及一蓋層，覆蓋該第一源極結構與該第一汲極結構，其中該蓋層摻雜IIIA族元素。
TW107114687A 2017-08-31 2018-04-30 半導體裝置結構與其形成方法 TWI755527B (zh)

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US20210119049A1 (en) 2021-04-22
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