TWI619409B - Method for manufacturing surface-treated copper foil, laminated board, printed wiring board, electronic device, copper foil with carrier and printed wiring board - Google Patents

Method for manufacturing surface-treated copper foil, laminated board, printed wiring board, electronic device, copper foil with carrier and printed wiring board Download PDF

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TWI619409B
TWI619409B TW103138688A TW103138688A TWI619409B TW I619409 B TWI619409 B TW I619409B TW 103138688 A TW103138688 A TW 103138688A TW 103138688 A TW103138688 A TW 103138688A TW I619409 B TWI619409 B TW I619409B
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layer
copper foil
carrier
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ultra
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TW201524280A (en
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Terumasa Moriyama
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Jx Nippon Mining & Metals Corp
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00Layered products comprising a layer of metal
    • B32B15/04Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material
    • B32B15/08Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material of synthetic resin
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00Layered products comprising a layer of metal
    • B32B15/20Layered products comprising a layer of metal comprising aluminium or copper
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B32LAYERED PRODUCTS
    • B32BLAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B33/00Layered products characterised by particular properties or particular surface features, e.g. particular surface coatings; Layered products designed for particular purposes not covered by another single class
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Laminated Bodies (AREA)

Abstract

提供一種即便用於高頻電路基板,傳輸損耗亦獲得良好抑制之表面處理銅箔。一種表面處理銅箔,於至少一表面形成有表面處理層,表面處理層中之Co、Ni、Fe合計附著量為1000μg/dm2以下,表面處理層具有Zn金屬層或含有Zn之合金處理層,表面處理層表面利用雷射顯微鏡所測得之三維表面積相對於二維表面積的比為1.0~1.9,至少一表面之表面粗糙度Rz JIS為2.2μm以下。 Provided is a surface-treated copper foil in which transmission loss is well suppressed even when used for a high-frequency circuit substrate. A surface-treated copper foil having a surface-treated layer formed on at least one surface. The total adhesion amount of Co, Ni, and Fe in the surface-treated layer is 1000 μg / dm 2 or less. The surface-treated layer has a Zn metal layer or an alloy-treated layer containing Zn. The ratio of the three-dimensional surface area to the two-dimensional surface area measured by the laser microscope on the surface of the surface treatment layer is 1.0 to 1.9, and the surface roughness Rz JIS of at least one surface is 2.2 μm or less.

Description

表面處理銅箔、積層板、印刷配線板、電子機器、附載體銅箔及印刷配線板之製造方法 Method for manufacturing surface-treated copper foil, laminated board, printed wiring board, electronic device, copper foil with carrier and printed wiring board

本發明係關於一種表面處理銅箔、積層板、印刷配線板、電子機器、附載體銅箔、及印刷配線板之製造方法,尤其是關於一種適合高頻電路基板用途之表面處理銅箔、積層板、印刷配線板、電子機器、附載體銅箔、及印刷配線板之製造方法。 The present invention relates to a method for manufacturing a surface-treated copper foil, a laminated board, a printed wiring board, an electronic device, a copper foil with a carrier, and a printed wiring board, and more particularly to a surface-treated copper foil, a laminated board suitable for high-frequency circuit substrate applications Board, printed wiring board, electronic device, copper foil with carrier, and manufacturing method of printed wiring board.

關於印刷配線板,此半個世紀以來取得了很大的進展,如今幾乎已被使用於所有的電子機器。隨著近年來電子機器之小型化、高性能化的需求增大,搭載零件之高密度構裝化及訊號之高頻化亦不斷發展,對印刷配線板要求優異之高頻對應。 Regarding printed wiring boards, great progress has been made in this half century, and it is now used in almost all electronic devices. As the demand for miniaturization and high performance of electronic devices has increased in recent years, high-density mounting of components and high-frequency signals have been continuously developed, and excellent high-frequency response is required for printed wiring boards.

對於高頻用基板而言,為了確保輸出訊號之品質,而要求減少傳輸損耗。傳輸損耗主要是起因於樹脂(基板側)之介電質損耗與起因於導體(銅箔側)之導體損耗。關於介電質損耗,樹脂之介電常數及介電損耗正切變得越小,該介電質損耗越減少。於高頻訊號中,導體損耗之主要原因在於:頻率變得越高,由於電流僅於導體表面流動之集膚效應,電流流經之剖面積越減少,電阻變得越高。 For high frequency substrates, in order to ensure the quality of the output signal, it is required to reduce the transmission loss. The transmission loss is mainly due to the dielectric loss caused by the resin (substrate side) and the conductor loss caused by the conductor (copper foil side). Regarding the dielectric loss, the smaller the dielectric constant and the dielectric loss tangent of the resin, the smaller the dielectric loss. In high-frequency signals, the main reason for conductor losses is that the higher the frequency becomes, the smaller the cross-sectional area through which the current flows is due to the skin effect of current flowing only on the surface of the conductor, and the higher the resistance becomes.

作為減少高頻用銅箔之傳輸損耗的技術,例如於專利文獻1 中揭示有一種高頻電路用金屬箔,係於金屬箔表面之單面或兩面被覆銀或銀合金,於該銀或銀合金被覆層上,設置厚度小於上述銀或銀合金被覆層之銀或銀合金以外的被覆層。而且,記載有:藉此,可提供一種即便於如衛星通訊所使用之超高頻區域中亦可減少因集膚效應造成之損耗的金屬箔。 As a technique for reducing the transmission loss of high-frequency copper foil, for example, Patent Document 1 It is disclosed that a metal foil for high-frequency circuits is coated on one or both sides of the surface of the metal foil with silver or a silver alloy, and the silver or silver alloy coating is provided with a silver or Coatings other than silver alloy. Furthermore, it is described that by this, it is possible to provide a metal foil that can reduce the loss due to the skin effect even in an ultra-high frequency region such as that used in satellite communications.

又,於專利文獻2中,揭示有一種高頻電路用粗化處理壓延 銅箔,其特徵在於:為印刷電路基板用素材,且壓延銅箔之再結晶退火後之壓延面藉由X射線繞射求出之(200)面的積分強度(I(200))相對於細粉末銅藉由X射線繞射求出之(200)面的積分強度(I0(200)),為I(200)/I0(200)>40,對該壓延面進行利用電鍍之粗化處理後的粗化處理面之算術平均粗糙度(以下,稱為Ra)為0.02μm~0.2μm,十點平均粗糙度(以下,稱為Rz)為0.1μm~1.5μm。而且,記載有:藉此,可提供一種可於超過1GHz之高頻率下使用的印刷電路板。 Further, Patent Document 2 discloses a roughened rolled copper foil for high-frequency circuits, which is characterized in that it is a material for a printed circuit board, and the rolled surface after recrystallization annealing of the rolled copper foil is wound by X-rays. The integrated intensity (I (200)) of the (200) plane obtained by injection is I (200) relative to the integrated intensity (I 0 (200)) of the (200) plane obtained by X-ray diffraction of fine powder copper. ) / I 0 (200)> 40, and the arithmetic average roughness (hereinafter, referred to as Ra) of the roughened surface after the roughening treatment using electroplating on the rolled surface is 0.02 μm to 0.2 μm, and the ten-point average roughness is The degree (hereinafter, referred to as Rz) is 0.1 μm to 1.5 μm. In addition, it is described that a printed circuit board that can be used at a high frequency exceeding 1 GHz can be provided.

進而,於專利文獻3中揭示有一種電解銅箔,其特徵在於:銅箔表面之一部分係由塊狀突起構成之表面粗糙度為2~4μm的凹凸面。而且,記載有:藉此,可提供一種高頻傳輸特性優異之電解銅箔。 Furthermore, Patent Document 3 discloses an electrolytic copper foil characterized in that a part of the surface of the copper foil is a concave-convex surface having a surface roughness of 2 to 4 μm which is formed by block-shaped protrusions. Furthermore, it is described that by this, it is possible to provide an electrolytic copper foil excellent in high-frequency transmission characteristics.

[專利文獻1]日本專利第4161304號公報 [Patent Document 1] Japanese Patent No. 4161304

[專利文獻2]日本專利第4704025號公報 [Patent Document 2] Japanese Patent No. 4704025

[專利文獻3]日本特開2004-244656號公報 [Patent Document 3] Japanese Patent Laid-Open No. 2004-244656

起因於導體(銅箔側)之導體損耗,如上述般係因集膚效應 使得電阻變大,關於該電阻,已知不僅有銅箔本身之電阻的影響,亦有於銅箔表面由為了確保與樹脂基板之接著性而進行之粗化處理所形成之表面處理層之電阻的影響,具體而言,銅箔表面之粗糙度為導體損耗之主要原因,粗糙度越小,傳輸損耗越減少。 Conductor loss due to conductor (copper foil side), as described above, due to skin effect The resistance is increased. It is known that the resistance is not only the influence of the resistance of the copper foil itself, but also the resistance of the surface treatment layer formed on the surface of the copper foil by a roughening treatment to ensure adhesion to the resin substrate. Specifically, the roughness of the copper foil surface is the main cause of conductor loss. The smaller the roughness, the lower the transmission loss.

又,於進行粗化處理作為銅箔之表面處理的情形時,通常使 用Cu-Ni合金處理或Cu-Co-Ni合金處理,而進行耐熱處理及防銹處理的情形時,則通常使用Ni-Zn合金處理或Co-Ni合金處理。 When roughening is performed as the surface treatment of copper foil, it is usually In the case of a Cu-Ni alloy treatment or a Cu-Co-Ni alloy treatment, and a heat-resistant treatment and a rust prevention treatment, a Ni-Zn alloy treatment or a Co-Ni alloy treatment is usually used.

然而,於上述粗化處理、耐熱處理及防銹處理中通常使用之 Co、Ni以及Fe係於常溫顯示出強磁性之金屬,於作為成分而含有於表面處理層中之情形時,會產生如下問題:因磁性之影響,導體內之電流分佈以及磁場分佈會受到影響,銅箔之傳輸特性變差。 However, it is commonly used in the above-mentioned roughening treatment, heat resistance treatment, and rust prevention treatment. Co, Ni, and Fe are metals exhibiting strong magnetism at room temperature. When they are contained in the surface treatment layer as a component, the following problems arise: the influence of magnetic properties on the current distribution and magnetic field distribution in the conductor will be affected. , The transmission characteristics of copper foil become worse.

本發明之目的在於提供一種即便用於高頻電路基板,傳輸損 耗亦獲得良好抑制之表面處理銅箔、積層板、印刷配線板、電子機器、附載體銅箔、及印刷配線板之製造方法。 An object of the present invention is to provide a transmission loss even in a high-frequency circuit board. The surface treatment copper foil, laminated board, printed wiring board, electronic equipment, copper foil with carrier, and printed wiring board manufacturing method which also has good suppression of power consumption.

本發明人發現,為了抑制強磁性金屬對傳輸特性之影響,可 藉由將銅箔之表面處理層中的Co、Ni、Fe合計附著量控制為既定量以下,且含有於常溫不顯示出強磁性之Zn作為替代成分,而進一步減少高頻傳輸損耗。進而發現,除了先前之對高頻用銅箔所控管之表面粗糙度Rz明顯影響傳輸損耗外,更準確地表示與樹脂(介電質)之接觸面積的三維表面積相對於二維表面積之比亦會對傳輸損耗造成顯著的影響。 The inventors have found that, in order to suppress the influence of ferromagnetic metals on transmission characteristics, By controlling the total adhesion amount of Co, Ni, and Fe in the surface treatment layer of the copper foil to a predetermined amount or less, and containing Zn that does not exhibit strong magnetism at ordinary temperature as a substitute component, high-frequency transmission loss is further reduced. It was further found that, in addition to the previous effect on the surface roughness Rz of the copper foil controlled by high frequency, which significantly affected the transmission loss, the ratio of the three-dimensional surface area to the two-dimensional surface area of the contact area with the resin (dielectric) was more accurately represented It can also have a significant impact on transmission loss.

基於上述見解而完成之本發明於一態樣中,係一種表面處理 銅箔,於至少一表面形成有表面處理層,上述表面處理層中之Co、Ni、Fe的合計附著量為1000μg/dm2以下,上述表面處理層具有Zn金屬層或含有Zn之合金處理層,上述表面處理層表面利用雷射顯微鏡所測得之三維表面積相對於二維表面積的比為1.0~1.9,至少一表面之表面粗糙度Rz JIS為2.2μm以下。 In one aspect, the present invention completed based on the above findings is a surface-treated copper foil having a surface-treated layer formed on at least one surface thereof. The total adhesion amount of Co, Ni, and Fe in the surface-treated layer is 1000 μg / dm. 2 or less, the surface treatment layer a metal layer having a Zn or Zn alloy containing treatment layer of the surface treatment layer surface of a three-dimensional surface area measured using the two-dimensional laser microscope with respect to specific surface area of 1.0 to 1.9, at least one surface of The surface roughness Rz JIS is 2.2 μm or less.

本發明之表面處理銅箔於一實施形態中,上述表面處理層中之Co、Ni、Fe合計附著量為500μg/dm2以下。 In one embodiment of the surface-treated copper foil of the present invention, the total adhesion amount of Co, Ni, and Fe in the surface-treated layer is 500 μg / dm 2 or less.

本發明之表面處理銅箔於另一實施形態中,上述表面處理層中之Co、Ni、Fe合計附著量為300μg/dm2以下。 In another embodiment of the surface-treated copper foil of the present invention, the total adhesion amount of Co, Ni, and Fe in the surface-treated layer is 300 μg / dm 2 or less.

本發明之表面處理銅箔於再另一實施形態中,上述表面處理層中之Co、Ni、Fe合計附著量為0μg/dm2In still another embodiment of the surface-treated copper foil of the present invention, the total adhesion amount of Co, Ni, and Fe in the surface-treated layer is 0 μg / dm 2 .

本發明之表面處理銅箔於再另一實施形態中,兩表面之表面粗糙度Rz JIS為2.2μm以下。 In still another embodiment of the surface-treated copper foil of the present invention, the surface roughness Rz JIS of both surfaces is 2.2 μm or less.

本發明之表面處理銅箔於再另一實施形態中,上述表面處理層包含粗化處理層。 In still another embodiment of the surface-treated copper foil of the present invention, the surface-treated layer includes a roughened layer.

本發明之表面處理銅箔於再另一實施形態中,上述粗化處理層中之Cu附著量為0.10g/dm2以下。 In still another embodiment of the surface-treated copper foil of the present invention, the Cu adhesion amount in the roughened layer is 0.10 g / dm 2 or less.

本發明之表面處理銅箔於再另一實施形態中,於上述表面處理層中,於上述粗化處理層上設置有上述Zn金屬層或含有Zn之合金處理層。 In still another embodiment of the surface-treated copper foil of the present invention, in the surface-treated layer, the roughened layer is provided with the Zn metal layer or an alloy-treated layer containing Zn.

本發明之表面處理銅箔於再另一實施形態中,上述含有Zn 之合金處理層為Cu-Zn合金層。 In another embodiment, the surface-treated copper foil of the present invention contains Zn The alloy-treated layer is a Cu-Zn alloy layer.

本發明之表面處理銅箔於再另一實施形態中,上述表面處理 層中之Zn附著量為5mg/dm2以下。 In still another embodiment of the surface-treated copper foil of the present invention, the Zn adhesion amount in the surface-treated layer is 5 mg / dm 2 or less.

本發明之表面處理銅箔於再另一實施形態中,於上述表面處 理層中,於上述Zn金屬層或含有Zn之合金處理層上設置有鉻酸處理(chromate treatment)層。 In still another embodiment of the surface-treated copper foil of the present invention, the surface is In the physical layer, a chromate treatment layer is provided on the Zn metal layer or the Zn-containing alloy treatment layer.

本發明之表面處理銅箔於再另一實施形態中,於上述鉻酸處 理層上設置有矽烷偶合處理層。 In another embodiment, the surface-treated copper foil of the present invention is A silane coupling treatment layer is provided on the management layer.

本發明之表面處理銅箔於再另一實施方式中,上述表面處理 層中之Cu、Zn、Co、Ni、Fe合計附著量為0.10g/dm2以下。 In still another embodiment of the surface-treated copper foil of the present invention, the total adhesion amount of Cu, Zn, Co, Ni, and Fe in the surface-treated layer is 0.10 g / dm 2 or less.

本發明之表面處理銅箔於再另一實施形態中,係用於軟性印 刷配線板。 In another embodiment, the surface-treated copper foil of the present invention is used for flexible printing. Brush the wiring board.

本發明之表面處理銅箔於再另一實施形態中,係用於5GHz 以上之高頻電路基板。 In another embodiment, the surface-treated copper foil of the present invention is used at 5 GHz. The above high frequency circuit board.

本發明於另一態樣中,係一種將本發明之表面處理銅箔與樹 脂基板加以積層而製得之積層板。 In another aspect, the present invention relates to a method of combining the surface-treated copper foil and tree of the present invention. A laminated board prepared by laminating a lipid substrate.

本發明於再另一態樣中,係一種以本發明之積層板作為材料 之印刷配線板。 The present invention, in yet another aspect, is a laminated board of the present invention as a material. Printed wiring board.

本發明於再另一態樣中,係一種使用本發明之印刷配線板之 電子機器。 In still another aspect, the present invention is a printed wiring board using the printed wiring board of the present invention. Electronic machine.

本發明於再另一態樣中,係一種附載體銅箔,於載體之一面 或兩面依序具有中間層、極薄銅層,上述極薄銅層為本發明之表面處理銅 箔。 In still another aspect, the present invention is a copper foil with a carrier on one side of the carrier. Or both sides have an intermediate layer and an ultra-thin copper layer in order. The above-mentioned ultra-thin copper layer is the surface-treated copper of the present invention. Foil.

本發明之附載體銅箔於一實施形態中,於上述載體之一面依序具有上述中間層、上述極薄銅層,於上述載體之另一面具有粗化處理層。 In one embodiment of the copper foil with a carrier of the present invention, the intermediate layer, the ultra-thin copper layer are sequentially provided on one side of the carrier, and the roughened layer is provided on the other side of the carrier.

本發明於再另一態樣中,係一種將本發明之附載體銅箔與樹脂基板加以積層而製得之積層板。 In still another aspect, the present invention is a laminated board prepared by laminating the copper foil with a carrier and a resin substrate of the present invention.

本發明於再另一態樣中,係一種印刷配線板之製造方法,包括如下步驟:準備本發明之附載體銅箔與絕緣基板之步驟;將上述附載體銅箔與絕緣基板積層之步驟;將上述附載體銅箔與絕緣基板積層後,經過將上述附載體銅箔之載體剝離之步驟而形成覆金屬積層板,然後,藉由半加成法(semi-additive process)、減成法(subtractive process)、部分加成法(partly additive process)或改良半加成法(modified semi-additive process)中之任一種方法而形成電路之步驟。 In yet another aspect, the present invention is a method for manufacturing a printed wiring board, comprising the steps of: preparing the copper foil with a carrier and an insulating substrate of the present invention; and laminating the copper foil with a carrier and the insulating substrate as described above; After the copper foil with a carrier and the insulating substrate are laminated, a metal-clad laminated board is formed through a step of peeling the carrier of the copper foil with a carrier, and then a semi-additive process and a subtractive method ( a step of forming a circuit by any one of a subtractive process, a partially additive process, or a modified semi-additive process.

本發明於再另一態樣中,係一種印刷配線板之製造方法,包括如下步驟:於本發明之附載體銅箔的上述極薄銅層側表面或上述載體側表面形成電路之步驟;以掩埋上述電路之方式,於上述附載體銅箔之上述極薄銅層側表面或上述載體側表面形成樹脂層之步驟;於上述樹脂層上形成電路之步驟;於上述樹脂層上形成電路後,將上述載體或上述極薄銅層剝離之步 驟;及將上述載體或上述極薄銅層剝離後,將上述極薄銅層或上述載體去除,藉此使形成於上述極薄銅層側表面或上述載體側表面被上述樹脂層掩埋之電路露出之步驟。 In yet another aspect, the present invention is a method for manufacturing a printed wiring board, comprising the steps of: forming a circuit on the above-mentioned ultra-thin copper layer side surface or the above-mentioned carrier side surface of the copper foil with a carrier of the present invention; The method of burying the circuit, a step of forming a resin layer on the ultra-thin copper layer side surface of the copper foil with a carrier or the carrier side surface; a step of forming a circuit on the resin layer; and after forming a circuit on the resin layer, Step of peeling the carrier or the ultra-thin copper layer And after the carrier or the ultra-thin copper layer is peeled off, the ultra-thin copper layer or the carrier is removed, so that the circuit formed on the ultra-thin copper layer side surface or the carrier-side surface is buried by the resin layer Exposed steps.

根據本發明,可提供一種即便用於高頻電路基板,傳輸損耗亦獲得良好抑制之表面處理銅箔、積層板、印刷配線板、電子機器、附載體銅箔、及印刷配線板之製造方法。 According to the present invention, it is possible to provide a method for manufacturing a surface-treated copper foil, a laminated board, a printed wiring board, an electronic device, a copper foil with a carrier, and a printed wiring board that have a good transmission loss suppression even when used in a high-frequency circuit board.

圖1係表示實施例及比較例之Co、Ni、Fe合計附著量與表面粗糙度Rz之關係的圖表。 FIG. 1 is a graph showing the relationship between the total adhesion amount of Co, Ni, and Fe and the surface roughness Rz in Examples and Comparative Examples.

圖2係表示實施例及比較例之Co、Ni、Fe合計附著量與三維表面積相對於二維表面積之比之關係的圖表。 FIG. 2 is a graph showing the relationship between the total adhesion amount of Co, Ni, and Fe and the ratio of the three-dimensional surface area to the two-dimensional surface area in the examples and comparative examples.

圖3係表示實施例及比較例之Co、Ni、Fe、Cu、Zn合計附著量與傳輸損耗之關係的圖表。 FIG. 3 is a graph showing the relationship between the total adhesion amount of Co, Ni, Fe, Cu, and Zn and transmission loss in Examples and Comparative Examples.

(銅箔基材) (Copper foil substrate)

可用於本發明之銅箔基材的形態並無特別限制,典型而言,可以壓延銅箔或電解銅箔之形態使用。一般而言,電解銅箔係使銅自硫酸銅鍍浴電解析出至鈦或不鏽鋼之轉筒上而製造,壓延銅箔則是反覆進行利用壓延輥之塑性加工與熱處理而製造。於要求可撓性之用途中,大多應用壓延銅箔。 The form of the copper foil base material that can be used in the present invention is not particularly limited. Typically, it can be used in the form of rolled copper foil or electrolytic copper foil. Generally speaking, electrolytic copper foil is produced by electrolyzing copper from a copper sulfate plating bath onto a titanium or stainless steel drum, and rolled copper foil is produced by repeatedly performing plastic processing and heat treatment using a calender roll. In applications where flexibility is required, rolled copper foil is mostly used.

作為銅箔基材之材料,除通常用作印刷配線板之導體圖案的精銅或無氧銅等高純度之銅以外,例如亦可使用摻Sn之銅、摻Ag之銅、添加有Cr、Zr或Mg等之銅合金、添加有Ni及Si等之卡遜(corson)系銅合金之類的銅合金。再者,於本說明書中單獨使用「銅箔」之用語時,亦包括銅合金箔。於使用銅合金箔作為高頻電路基板用之銅箔的情形時,亦可為與銅相比電阻率不明顯上升者。 As the material of the copper foil base material, in addition to high-purity copper such as fine copper or oxygen-free copper, which is usually used as a conductor pattern of printed wiring boards, for example, Sn-doped copper, Ag-doped copper, Cr, Copper alloys such as Zr or Mg, and copper alloys such as corson-based copper alloys to which Ni and Si are added. Furthermore, when the term "copper foil" is used alone in this specification, copper alloy foil is also included. When a copper alloy foil is used as a copper foil for a high-frequency circuit board, the resistivity may not be significantly increased compared to copper.

再者,銅箔基材之板厚無需特別限定,例如為1~300μm、或者3~100μm、或者5μm~70μm、或者6μm~35μm、或者9μm~18μm。 The thickness of the copper foil substrate is not particularly limited, and is, for example, 1 to 300 μm, or 3 to 100 μm, or 5 to 70 μm, or 6 to 35 μm, or 9 to 18 μm.

(表面處理層) (Surface treatment layer)

於銅箔基材之表面,較佳形成有基於選自粗化處理層、防銹層、耐熱層、矽烷偶合處理層中之一種以上之層的表面處理層。本發明之表面處理層可如上述般形成於與樹脂之接著面(M面),亦可形成於與接著面(M面)相反側之面(S面),亦可形成於兩面。 On the surface of the copper foil substrate, a surface treatment layer based on one or more selected from the group consisting of a roughening treatment layer, a rust prevention layer, a heat-resistant layer, and a silane coupling treatment layer is preferably formed. The surface treatment layer of the present invention may be formed on the adhesion surface (M surface) with the resin as described above, or on the surface (S surface) opposite to the adhesion surface (M surface), or on both surfaces.

粗化處理例如可藉由以銅或銅合金形成粗化粒子來進行。粗化處理可為微細者。又,亦可於粗化處理後,進行覆蓋鍍敷處理。藉由該等粗化處理、防銹處理、耐熱處理、矽烷處理、於處理液中之浸漬處理或鍍敷處理所形成之表面處理層,亦可含有選自由Cu、Ni、Fe、Co、Zn、Cr、Mo、W、P、As、Ag、Sn、Ge組成之群中之任一種單質或任一種以上之合金,或者有機物。 The roughening treatment can be performed, for example, by forming roughened particles with copper or a copper alloy. The roughening process may be fine. After the roughening treatment, a covering plating treatment may be performed. The surface treatment layer formed by such roughening treatment, rust prevention treatment, heat treatment, silane treatment, immersion treatment in a treatment liquid, or plating treatment may also contain a material selected from the group consisting of Cu, Ni, Fe, Co, and Zn. , Cr, Mo, W, P, As, Ag, Sn, Ge in any group of simple substance or any one or more alloys, or organic matter.

為了抑制強磁性金屬對傳輸特性之影響,而將銅箔之表面處 理層中之Co、Ni、Fe合計附著量如下述般控制為既定量以下,且含有在常溫不顯示出強磁性之Zn作為替代成分,藉此可進一步減少高頻傳輸損耗。 因此,表面處理層具有Zn金屬層或含有Zn之合金處理層。又,含有Zn之合金處理層亦可為Cu-Zn合金層。藉由設為Cu-Zn合金層,相較於設為Zn單獨之金屬層,可提高耐熱性與耐化學品性。 In order to suppress the influence of ferromagnetic metals on the transmission characteristics, The total adhesion amount of Co, Ni, and Fe in the physical layer is controlled to be less than a predetermined amount as described below, and Zn, which does not show strong magnetism at normal temperature, is used as an alternative component, thereby further reducing high-frequency transmission loss. Therefore, the surface treatment layer has a Zn metal layer or an alloy treatment layer containing Zn. The alloy-treated layer containing Zn may be a Cu-Zn alloy layer. By using a Cu-Zn alloy layer, heat resistance and chemical resistance can be improved compared to a metal layer made of Zn alone.

當表面處理層係使用粗化處理層、防銹層、耐熱層、矽烷偶 合處理層中之任一種而形成的情形時,該等層之順序並無特別限定,例如亦可於銅箔表面形成粗化處理層,於該粗化處理層上設置Zn金屬層或含有Zn之合金處理層作為防銹、耐熱層。又,亦可於Zn金屬層或含有Zn之合金處理層上設置鉻酸處理層。進而,亦可於鉻酸處理層上設置矽烷偶合處理層。 When the surface treatment layer is a roughened layer, a rust-proof layer, a heat-resistant layer, and a silane coupler In the case where any one of the treatment layers is formed, the order of the layers is not particularly limited. For example, a roughening treatment layer may be formed on the surface of a copper foil, and a Zn metal layer or a Zn-containing layer may be provided on the roughening treatment layer. The alloy-treated layer serves as a rust-proof and heat-resistant layer. A chromic acid treatment layer may be provided on the Zn metal layer or the Zn-containing alloy treatment layer. Furthermore, a silane coupling treatment layer may be provided on the chromic acid treatment layer.

(金屬附著量) (Metal adhesion amount)

本發明之表面處理銅箔,於表面處理層中,Co、Ni、Fe之合計附著量被控制為1000μg/dm2以下。本發明之表面處理銅箔,如上述般對成為傳輸損耗之原因的磁導率相對較高且導電率相對較低之Co、Ni、Fe附著量加以控制,因此可減少高頻傳輸損耗。表面處理層中之Co、Ni、Fe合計附著量較佳為500μg/dm2以下,更佳為300μg/dm2以下,再更佳為0μg/dm2(表示分析之定量下限值以下)。 In the surface-treated copper foil of the present invention, the total adhesion amount of Co, Ni, and Fe in the surface-treated layer is controlled to 1000 μg / dm 2 or less. As described above, the surface-treated copper foil of the present invention controls the adhesion amount of Co, Ni, and Fe, which are relatively high in magnetic permeability and relatively low in electric conductivity, as a cause of transmission loss, so that high-frequency transmission loss can be reduced. The total adhesion amount of Co, Ni, and Fe in the surface treatment layer is preferably 500 μg / dm 2 or less, more preferably 300 μg / dm 2 or less, and even more preferably 0 μg / dm 2 (indicating the quantitative lower limit of analysis).

於表面處理層包含粗化處理層之情形時,該粗化處理層中之 Cu附著量較佳為0.10g/dm2以下。根據此種構成,可進一步減少高頻傳輸損耗。粗化處理層中之Cu附著量更佳為0.09g/dm2以下,再更佳為0.08g/dm2以下,典型為0.04~0.08g/dm2When the surface treatment layer includes a roughening treatment layer, the Cu adhesion amount in the roughening treatment layer is preferably 0.10 g / dm 2 or less. According to this configuration, high-frequency transmission loss can be further reduced. The Cu adhesion amount in the roughened layer is more preferably 0.09 g / dm 2 or less, even more preferably 0.08 g / dm 2 or less, and typically 0.04 to 0.08 g / dm 2 .

表面處理層中之Zn附著量較佳為5mg/dm2以下。根據此種構成,耐化學品性會獲得提升,耐熱性變良好。表面處理層中之Zn附著 量更佳為4.5mg/dm2以下,再更佳為4mg/dm2以下,典型為0.1~4.5mg/dm2The adhesion amount of Zn in the surface treatment layer is preferably 5 mg / dm 2 or less. With this configuration, chemical resistance is improved, and heat resistance is improved. The Zn adhesion amount in the surface treatment layer is more preferably 4.5 mg / dm 2 or less, even more preferably 4 mg / dm 2 or less, and typically 0.1 to 4.5 mg / dm 2 .

表面處理層中之Cu、Zn、Co、Ni、Fe合計附著量,較佳為 0.10g/dm2以下。根據此種構成,可進一步減少高頻傳輸損耗。表面處理層中之Cu、Zn、Co、Ni、Fe合計附著量更佳為0.09g/dm2以下,再更佳為0.08g/dm2以下,典型為0.04~0.08g/dm2The total adhesion amount of Cu, Zn, Co, Ni, and Fe in the surface treatment layer is preferably 0.10 g / dm 2 or less. According to this configuration, high-frequency transmission loss can be further reduced. The total adhesion amount of Cu, Zn, Co, Ni, and Fe in the surface treatment layer is more preferably 0.09 g / dm 2 or less, even more preferably 0.08 g / dm 2 or less, and typically 0.04 to 0.08 g / dm 2 .

(表面粗糙度Rz) (Surface roughness Rz)

銅箔表面之粗糙度係導體損耗之主要原因,粗糙度越小,傳輸損耗越減少。就此種觀點而言,本發明之表面處理銅箔可將至少一表面之表面粗糙度Rz JIS控制為2.2μm以下,而可良好地減少傳輸損耗。又,較佳為兩表面之表面粗糙度Rz JIS在2.2μm以下。根據此種構成,可進一步減少高頻傳輸損耗。 The roughness of the copper foil surface is the main cause of conductor loss. The smaller the roughness, the smaller the transmission loss. From such a viewpoint, the surface-treated copper foil of the present invention can control the surface roughness Rz JIS of at least one surface to 2.2 μm or less, and can reduce transmission loss well. The surface roughness Rz JIS of both surfaces is preferably 2.2 μm or less. According to this configuration, high-frequency transmission loss can be further reduced.

表面粗糙度Rz JIS更佳為1.5μm以下,再更佳為1.2μm以下,典型為0.5~2.2μm。 The surface roughness Rz JIS is more preferably 1.5 μm or less, even more preferably 1.2 μm or less, and typically 0.5 to 2.2 μm.

(表面積比) (Surface area ratio)

除了先前之對於高頻用銅箔所控管之表面粗糙度Rz外,亦必須將更準確地表示與影響高頻傳輸損耗之樹脂(介電質)之接觸面積的三維表面積相對於二維表面積之比控制在適當範圍。就此種觀點而言,本發明之表面處理銅箔,表面處理層表面利用雷射顯微鏡所測得之三維表面積相對於二維表面積之比被控制為1.0~1.9,從而即便用於高頻電路基板,傳輸損耗亦可更良好地獲得抑制。該表面積比於定義上無法成為未達1.0之值,若超過1.9,則有產生高頻傳輸損耗變大之問題之虞。該表面積比較佳為1.0~1.9, 更佳為1.0~1.6,再更佳為1.3~1.6。 In addition to the surface roughness Rz previously controlled for high-frequency copper foil, the three-dimensional surface area must be more accurately represented than the two-dimensional surface area in contact with the resin (dielectric) that affects high-frequency transmission loss. The ratio is controlled in an appropriate range. From this point of view, the surface-treated copper foil of the present invention has a ratio of the three-dimensional surface area to the two-dimensional surface area measured by a laser microscope on the surface of the surface-treated layer controlled to 1.0 to 1.9, so that it can be used even in high-frequency circuit substrates. , Transmission loss can also be better suppressed. This surface area ratio cannot be defined as a value less than 1.0, and if it exceeds 1.9, there is a possibility that a high-frequency transmission loss may increase. The surface area is preferably 1.0 ~ 1.9, It is more preferably 1.0 to 1.6, and even more preferably 1.3 to 1.6.

(表面處理銅箔之製造方法) (Manufacturing method of surface treated copper foil)

於本發明中,較佳對銅箔基材(壓延銅箔或電解銅箔)之一表面或兩表面實施對酸洗後之銅箔表面進行瘤狀電沈積之粗化處理。藉由粗化處理,而獲得與樹脂(介電質)之密合性(剝離強度)。於本發明中,該粗化處理例如可藉由選自由Cu、Ni、Fe、Co、Zn、Cr、Mo、W、P、As、Ag、Sn、Ge組成之群中之任一種單質或任一種以上之合金的鍍敷,或者利用有機物之表面處理等來進行。有時進行通常之鍍銅等作為粗化前之預處理,亦有時在粗化後,為了賦予耐熱性、耐化學品性,而以上述金屬進行覆蓋鍍敷作為表面處理。再者,亦可不進行粗化處理,而進行選自由Cu、Ni、Fe、Co、Zn、Cr、Mo、W、P、As、Ag、Sn、Ge組成之群中之任一種單質或任一種以上之合金的鍍敷。然後,亦有時為了賦予耐熱性、耐化學品性,而以上述金屬進行覆蓋鍍敷作為表面處理。於進行粗化處理之情形時,有與樹脂之密合強度變高的優點。又,於不進行粗化處理之情形時,有如下優點:表面處理銅箔之製造步驟得以簡化,因此生產性提高,且可降低成本,又,可使粗糙度變小。對於壓延銅箔與電解銅箔,亦有時使處理之內容些許不同。藉由調整此種銅箔表面之鍍敷處理的液組成、鍍敷時間、電流密度,可控制本發明之表面處理層中的Co、Ni、Fe合計附著量,於表面處理層中形成Zn金屬層或含有Zn之合金處理層,控制表面處理層表面利用雷射顯微鏡所測得之三維表面積相對於二維表面積的比,進而控制表面粗糙度Rz JIS。 In the present invention, one or both surfaces of a copper foil substrate (rolled copper foil or electrolytic copper foil) is preferably subjected to a roughening treatment of nodular electrodeposition on the surface of the copper foil after pickling. By the roughening treatment, adhesiveness (peel strength) with the resin (dielectric) is obtained. In the present invention, the roughening treatment may be performed by any element or any one selected from the group consisting of Cu, Ni, Fe, Co, Zn, Cr, Mo, W, P, As, Ag, Sn, and Ge. One or more alloys are plated, or surface treatment of an organic substance is used. In general, copper plating or the like may be used as a pretreatment before roughening, or after the roughening, in order to impart heat resistance and chemical resistance, the above-mentioned metal may be subjected to cover plating as a surface treatment. In addition, without roughening, any elementary substance or any element selected from the group consisting of Cu, Ni, Fe, Co, Zn, Cr, Mo, W, P, As, Ag, Sn, and Ge may be performed. Plating of the above alloys. Then, in order to provide heat resistance and chemical resistance, cover plating with the above-mentioned metal may be used as a surface treatment. When the roughening treatment is performed, there is an advantage that the adhesion strength with the resin becomes high. In addition, when the roughening treatment is not performed, there are advantages in that the manufacturing steps of the surface-treated copper foil are simplified, so that productivity is improved, costs can be reduced, and roughness can be reduced. For rolled copper foil and electrolytic copper foil, the content of the treatment may be slightly different. By adjusting the composition, plating time, and current density of the plating treatment on the surface of such a copper foil, the total adhesion amount of Co, Ni, and Fe in the surface treatment layer of the present invention can be controlled to form Zn metal in the surface treatment layer. Layer or an alloy-treated layer containing Zn, and controls the ratio of the three-dimensional surface area to the two-dimensional surface area measured by the laser microscope on the surface of the surface-treated layer, thereby controlling the surface roughness Rz JIS.

又,表面粗糙度Rz成為上述範圍之電解銅箔,可藉由以下 方法製作。 The electrolytic copper foil having a surface roughness Rz in the above range can be obtained by the following method: Method of making.

<電解液組成> <Electrolyte composition>

銅:90~110g/L Copper: 90 ~ 110g / L

硫酸:90~110g/L Sulfuric acid: 90 ~ 110g / L

氯:50~100ppm Chlorine: 50 ~ 100ppm

調平劑(leveling agent)1(雙(3-磺丙基)二硫化物):10~30ppm Leveling agent 1 (bis (3-sulfopropyl) disulfide): 10 ~ 30ppm

調平劑2(胺化合物):10~30ppm Leveling agent 2 (amine compound): 10 ~ 30ppm

上述胺化合物可使用下述化學式之胺化合物。 As the amine compound, an amine compound of the following chemical formula can be used.

(上述化學式中,R1及R2為選自由羥烷基、醚基、芳基、經芳香族取代之烷基、不飽和烴基、烷基組成之群中者)。 (In the above chemical formula, R 1 and R 2 are selected from the group consisting of a hydroxyalkyl group, an ether group, an aryl group, an aromatic-substituted alkyl group, an unsaturated hydrocarbon group, and an alkyl group).

<製造條件> <Manufacturing conditions>

電流密度:70~100A/dm2 Current density: 70 ~ 100A / dm 2

電解液溫度:50~60℃ Electrolyte temperature: 50 ~ 60 ℃

電解液線速度:3~5m/sec Linear speed of electrolyte: 3 ~ 5m / sec

電解時間:0.5~10分鐘 Electrolysis time: 0.5 ~ 10 minutes

可將本發明之表面處理銅箔自表面處理層側貼合於樹脂基 板而製造積層板。又,若有必要,可進一步對該表面處理銅箔進行加工而形成電路,藉此製造印刷配線板等。樹脂基板只要為具有可應用於印刷配線板或印刷電路板等之特性者,則並無特別限制,例如,剛性PWB用可使用紙基材酚樹脂、紙基材環氧樹脂、合成纖維布基材環氧樹脂、氟樹脂含浸布、玻璃布-紙複合基材環氧樹脂、玻璃布-玻璃不織布複合基材環氧樹脂及玻璃布基材環氧樹脂等,可撓性印刷基板(FPC)用可使用聚酯膜或聚醯亞胺膜、液晶聚合物(LCP)膜、氟樹脂及氟樹脂-聚醯亞胺複合材料等。再者,由於液晶聚合物(LCP)之介電損耗小,故而高頻電路用途之印刷配線板或印刷電路板較佳使用液晶聚合物(LCP)膜。再者,於本發明中,「印刷配線板」亦包括安裝有零件之印刷配線板及印刷電路板及印刷基板。 又,亦可將本發明之印刷配線板連接2個以上,而製造連接有2個以上之印刷配線板的印刷配線板,又,亦可將至少1個本發明之印刷配線板與另一個本發明之印刷配線板或不相當於本發明之印刷配線板的印刷配線板加以連接,使用此種印刷配線板製造電子機器。再者,於本發明中,「銅電路」亦包括銅配線。 The surface-treated copper foil of the present invention can be bonded to a resin base from the surface-treated layer side Laminated board. If necessary, the surface-treated copper foil may be further processed to form a circuit, thereby producing a printed wiring board or the like. The resin substrate is not particularly limited as long as it has characteristics applicable to printed wiring boards or printed circuit boards. For example, for rigid PWB, paper substrate phenol resin, paper substrate epoxy resin, and synthetic fiber cloth substrate can be used. Material epoxy resin, fluororesin impregnated cloth, glass cloth-paper composite substrate epoxy resin, glass cloth-glass nonwoven composite substrate epoxy resin and glass cloth substrate epoxy resin, etc., flexible printed circuit board (FPC) Polyester film or polyimide film, liquid crystal polymer (LCP) film, fluororesin and fluororesin-polyimide composite materials can be used. Furthermore, since the dielectric loss of the liquid crystal polymer (LCP) is small, it is preferable to use a liquid crystal polymer (LCP) film for printed wiring boards or printed circuit boards for high-frequency circuit applications. Furthermore, in the present invention, the "printed wiring board" also includes a printed wiring board, a printed circuit board, and a printed circuit board on which components are mounted. In addition, two or more printed wiring boards of the present invention may be connected, and a printed wiring board to which two or more printed wiring boards are connected may be manufactured. At least one printed wiring board of the present invention may be connected to another printed wiring board. The printed wiring board of the present invention or a printed wiring board that is not equivalent to the printed wiring board of the present invention is connected, and an electronic device is manufactured using this printed wiring board. Furthermore, in the present invention, the "copper circuit" also includes copper wiring.

關於貼合之方法,於剛性PWB用之情形時,準備使玻璃布 等基材含浸樹脂,使樹脂硬化直至半硬化狀態之預浸體。可藉由使銅箔與預浸體重疊並加熱加壓而進行。於FPC之情形時,經由接合劑或不使用接合劑而使液晶聚合物或聚醯亞胺膜等基材於高溫高壓下與銅箔積層接合,或對聚醯亞胺前驅物進行塗佈、乾燥、硬化等,藉此可製造積層板。 Regarding the bonding method, in the case of rigid PWB, prepare to make glass cloth The substrate is impregnated with resin, and the resin is hardened to a semi-hardened prepreg. This can be performed by overlapping a copper foil with a prepreg and applying heat and pressure. In the case of FPC, a substrate such as a liquid crystal polymer or a polyimide film is bonded to a copper foil laminate at a high temperature and pressure via a bonding agent or without a bonding agent, or a polyimide precursor is coated, By drying, hardening, etc., a laminated board can be manufactured.

本發明之積層板可用於各種印刷配線板(PWB)或印刷電 路板,並無特別限制。作為印刷配線板,例如就導體圖案之層數的觀點而 言,可應用於單面PWB、兩面PWB、多層PWB(3層以上),就絕緣基板材料之種類的觀點而言,可應用於剛性PWB、軟性PWB(FPC)、剛性-彈性PWB。 The laminated board of the present invention can be used in various printed wiring boards (PWB) or printed wiring boards. There are no particular restrictions on road boards. As a printed wiring board, for example, from the viewpoint of the number of layers of a conductor pattern In other words, it can be applied to single-sided PWB, double-sided PWB, multilayer PWB (3 or more layers), and from the viewpoint of the type of insulating substrate material, it can be applied to rigid PWB, flexible PWB (FPC), and rigid-elastic PWB.

又,作為另一實施形態,本發明亦可為一種下述之表面處理銅箔,於至少一表面形成有表面處理層,上述表面處理層包含粗化處理層,上述表面處理層中之Co、Ni、Fe合計附著量為300μg/dm2以下,上述表面處理層具有Zn金屬層或含有Zn之合金處理層,上述表面處理層表面利用雷射顯微鏡所測得之三維表面積相對於二維表面積之比為1.0~1.9,至少一表面之表面粗糙度Rz JIS為2.2μm以下,於兩表面形成有上述表面處理層,上述兩表面之表面粗糙度Rz JIS為2.2μm以下。 Furthermore, as another embodiment, the present invention may also be a surface-treated copper foil described below. A surface-treated layer is formed on at least one surface. The surface-treated layer includes a roughened layer. Co, The total adhesion amount of Ni and Fe is 300 μg / dm 2 or less. The surface treatment layer has a Zn metal layer or an alloy treatment layer containing Zn. The surface of the surface treatment layer has a three-dimensional surface area relative to a two-dimensional surface area measured by a laser microscope. The ratio is 1.0 to 1.9, the surface roughness Rz JIS of at least one surface is 2.2 μm or less, the surface treatment layer is formed on both surfaces, and the surface roughness Rz JIS of the two surfaces is 2.2 μm or less.

又,作為另一實施形態,本發明亦可為一種下述之表面處理銅箔,於至少一表面形成有表面處理層,上述表面處理層包含粗化處理層,上述表面處理層中之Co、Ni、Fe合計附著量為300μg/dm2以下,上述表面處理層具有Zn金屬層或含有Zn之合金處理層,上述表面處理層表面利用雷射顯微鏡所測得之三維表面積相對於二維表面積之比為1.0~1.9,至少一表面之表面粗糙度Rz JIS為2.2μm以下,上述含有Zn之合金處理層為Cu-Zn合金層。 Furthermore, as another embodiment, the present invention may also be a surface-treated copper foil described below. A surface-treated layer is formed on at least one surface. The surface-treated layer includes a roughened layer. Co, The total adhesion amount of Ni and Fe is 300 μg / dm 2 or less. The surface treatment layer has a Zn metal layer or an alloy treatment layer containing Zn. The surface of the surface treatment layer has a three-dimensional surface area relative to a two-dimensional surface area measured by a laser microscope. The ratio is 1.0 to 1.9, the surface roughness Rz JIS of at least one surface is 2.2 μm or less, and the above-mentioned Zn-containing alloy treatment layer is a Cu-Zn alloy layer.

又,作為另一實施形態,本發明亦可為一種下述之表面處理銅箔,於至少一表面形成有表面處理層, 上述表面處理層包含粗化處理層,上述表面處理層中之Co、Ni、Fe合計附著量為300μg/dm2以下,上述表面處理層具有Zn金屬層或含有Zn之合金處理層,上述表面處理層表面利用雷射顯微鏡所測得之三維表面積相對於二維表面積之比為1.0~1.9,至少一表面之表面粗糙度Rz JIS為2.2μm以下,上述表面處理層中之Cu、Zn、Co、Ni、Fe合計附著量為0.10g/dm2以下。 Furthermore, as another embodiment, the present invention may also be a surface-treated copper foil as described below. A surface-treated layer is formed on at least one surface. The surface-treated layer includes a roughened layer, and Co, The total adhesion amount of Ni and Fe is 300 μg / dm 2 or less. The surface treatment layer has a Zn metal layer or an alloy treatment layer containing Zn. The surface of the surface treatment layer has a three-dimensional surface area relative to a two-dimensional surface area measured by a laser microscope. The ratio is 1.0 to 1.9, the surface roughness Rz JIS of at least one surface is 2.2 μm or less, and the total adhesion amount of Cu, Zn, Co, Ni, and Fe in the surface treatment layer is 0.10 g / dm 2 or less.

又,作為另一實施形態,本發明亦可為一種下述之表面處理銅箔,於至少一表面形成有表面處理層,上述表面處理層中之Co、Ni、Fe合計附著量為986μg/dm2以下,上述表面處理層具有Zn金屬層或含有Zn之合金處理層,上述表面處理層表面利用雷射顯微鏡所測得之三維表面積相對於二維表面積之比為1.0~1.9,於兩表面形成有上述表面處理層,上述兩表面之表面粗糙度Rz JIS為0.6μm以下。 Furthermore, as another embodiment, the present invention may be a surface-treated copper foil as described below. A surface-treated layer is formed on at least one surface. The total adhesion amount of Co, Ni, and Fe in the surface-treated layer is 986 μg / dm. 2 or less, the surface treatment layer a metal layer having a Zn or Zn alloy containing treatment layer of the surface treatment layer surface measured by a laser microscope with respect to surface area ratio of the three-dimensional surface area is 1.0 to 1.9, is formed on both surfaces The surface treatment layer is provided, and the surface roughness Rz JIS of the two surfaces is 0.6 μm or less.

(附載體銅箔) (With carrier copper foil)

作為本發明之另一實施形態的附載體銅箔,於載體之一面或兩面依序具有中間層、極薄銅層。而且,上述極薄銅層係作為上述本發明之一實施形態的表面處理銅箔。 As another embodiment of the present invention, the copper foil with a carrier has an intermediate layer and an ultra-thin copper layer in this order on one or both sides of the carrier. The ultra-thin copper layer is a surface-treated copper foil according to an embodiment of the present invention.

<載體> <Carrier>

可用於本發明之載體,典型為金屬箔或樹脂膜,例如以銅箔、銅合金箔、鎳箔、鎳合金箔、鐵箔、鐵合金箔、不鏽鋼箔、鋁箔、鋁合金箔、絕緣樹脂膜(例如聚醯亞胺膜、液晶聚合物(LCP)膜、聚對酞酸乙二酯(PET) 膜、聚醯胺膜、聚酯膜、氟樹脂膜等)之形態提供。 The carrier that can be used in the present invention is typically a metal foil or a resin film, such as copper foil, copper alloy foil, nickel foil, nickel alloy foil, iron foil, iron alloy foil, stainless steel foil, aluminum foil, aluminum alloy foil, insulating resin film ( For example, polyimide film, liquid crystal polymer (LCP) film, polyethylene terephthalate (PET) Film, polyamide film, polyester film, fluororesin film, etc.).

作為可用於本發明之載體,較佳使用銅箔。其原因在於:銅箔由於導電率高,故容易形成其後之中間層、極薄銅層。載體典型係以壓延銅箔或電解銅箔之形態提供。一般而言,電解銅箔係使銅自硫酸銅鍍浴電解析出至鈦或不鏽鋼之轉筒上而製造,壓延銅箔則是反覆進行利用壓延輥之塑性加工與熱處理而製造。作為銅箔之材料,除精銅或無氧銅等高純度之銅以外,例如亦可使用摻有Sn之銅、摻Ag之銅、添加有Cr、Zr或Mg等之銅合金、添加有Ni及Si等之卡遜系銅合金之類的銅合金。 As a carrier usable in the present invention, copper foil is preferably used. This is because the copper foil has a high electrical conductivity, so it is easy to form an intermediate layer and an extremely thin copper layer thereafter. The carrier is typically provided in the form of a rolled copper foil or an electrolytic copper foil. Generally speaking, electrolytic copper foil is produced by electrolyzing copper from a copper sulfate plating bath onto a titanium or stainless steel drum, and rolled copper foil is produced by repeatedly performing plastic processing and heat treatment using a calender roll. As the material of the copper foil, in addition to high-purity copper such as refined copper or oxygen-free copper, for example, copper doped with Sn, copper doped with Ag, copper alloy added with Cr, Zr, or Mg, and Ni may be added. Copper alloys such as Carson-based copper alloys such as Si.

關於可用於本發明之載體的厚度,並無特別限制,只要適當 調節成可作為載體之適合厚度即可,例如可設為5μm以上。但是,若過厚則生產成本會提高,故通常較佳設為35μm以下。因此,載體之厚度典型為12~70μm,更典型為18~35μm。 Regarding the thickness of the carrier that can be used in the present invention, there is no particular limitation as long as it is appropriate What is necessary is just to adjust it to a suitable thickness as a carrier, and it can be set to 5 micrometers or more, for example. However, if it is too thick, the production cost will increase, so it is usually preferably 35 μm or less. Therefore, the thickness of the carrier is typically 12 to 70 μm, and more typically 18 to 35 μm.

又,用於本發明之載體,可藉由如下述般控制形成中間層之 側的表面粗糙度Rz及表面積比,而控制表面處理後之極薄銅層表面(即表面處理層表面)之表面粗糙度Rz及表面積比。 In addition, the carrier used in the present invention can be controlled to form an intermediate layer as described below. The surface roughness Rz and the surface area ratio of the side, and the surface roughness Rz and the surface area ratio of the surface of the ultra-thin copper layer after the surface treatment (that is, the surface of the surface treatment layer) are controlled.

關於用於本發明之載體,預先控制中間層形成前之載體之形 成中間層之側的表面之TD之粗糙度(Rz)及表面積比亦是重要的。具體而言,中間層形成前之載體的TD之表面粗糙度(Rz)為0.20~1.50μm,較佳為0.20~1.00μm,表面積比為1.0~1.9,較佳為1.0~1.5。作為此種銅箔,可藉由如下方式製作,即調整壓延油之油膜當量進行壓延,或者進行化學蝕刻之類的化學研磨或磷酸溶液中之電解研磨,又,添加既定之添加劑製造電解銅箔。藉由以上述方式將處理前之銅箔的TD之表面粗糙度(Rz)與 表面積比設為上述範圍,可輕易控制處理後之銅箔的表面粗糙度(Rz)與表面積比。 Regarding the carrier used in the present invention, the shape of the carrier before the intermediate layer is formed is controlled in advance The roughness (Rz) and surface area ratio of the TD of the surface forming the side of the intermediate layer are also important. Specifically, the surface roughness (Rz) of the TD of the carrier before the formation of the intermediate layer is 0.20 to 1.50 μm, preferably 0.20 to 1.00 μm, and the surface area ratio is 1.0 to 1.9, preferably 1.0 to 1.5. Such a copper foil can be produced by adjusting the oil film equivalent of the rolling oil to perform rolling, chemical polishing such as chemical etching or electrolytic polishing in a phosphoric acid solution, and adding predetermined additives to produce an electrolytic copper foil. . The surface roughness (Rz) of the TD of the copper foil before processing is The surface area ratio is set to the above range, and the surface roughness (Rz) and surface area ratio of the copper foil after processing can be easily controlled.

再者,壓延可藉由將下式所規定之油膜當量設為13000~35000以下而進行。 The rolling can be performed by setting the oil film equivalent specified in the following formula to 13,000 to 35,000.

油膜當量={(壓延油黏度[cSt])×(過板速度[mPm]+輥圓周速度[mpm])}/{(輥之咬角[rad])×(材料之降伏應力[kg/mm2])} Oil film equivalent = {(rolling oil viscosity [cSt]) × (crossing speed [mPm] + roller peripheral speed [mpm])} / {(roller bite angle [rad]) × (material falling stress [kg / mm 2 ])}

壓延油黏度[cSt]係40℃之動態黏度。 The rolling oil viscosity [cSt] is a dynamic viscosity at 40 ° C.

為了使油膜當量於13000~35000之範圍內較低,可使用如下之公知方法,即使用低黏度之壓延油,或者減緩過板速度等。又,為了使油膜當量於13000~35000之範圍內較高,可使用如下之公知方法,即使用高黏度之壓延油,或者提高過板速度等。 In order to lower the oil film equivalent in the range of 13,000 to 35,000, a known method such as using a low-viscosity rolling oil or slowing down the board speed can be used. In addition, in order to make the oil film equivalent in the range of 13,000 to 35,000 higher, a known method such as using a high-viscosity calender oil or increasing the plate speed can be used.

又,表面粗糙度Rz及表面積比成為上述範圍之電解銅箔,可藉由以下方法製作。可使用該電解銅箔作為載體。 An electrolytic copper foil having a surface roughness Rz and a surface area ratio within the above range can be produced by the following method. This electrolytic copper foil can be used as a carrier.

<電解液組成> <Electrolyte composition>

銅:90~110g/L Copper: 90 ~ 110g / L

硫酸:90~110g/L Sulfuric acid: 90 ~ 110g / L

氯:50~100ppm Chlorine: 50 ~ 100ppm

調平劑1(雙(3-磺丙基)二硫化物):10~30ppm Leveling agent 1 (bis (3-sulfopropyl) disulfide): 10 ~ 30ppm

調平劑2(胺化合物):10~30ppm Leveling agent 2 (amine compound): 10 ~ 30ppm

上述胺化合物可使用下述化學式之胺化合物。 As the amine compound, an amine compound of the following chemical formula can be used.

(上述化學式中,R1及R2為選自由羥烷基、醚基、芳基、經芳香族取代之烷基、不飽和烴基、烷基組成之群中者)。 (In the above chemical formula, R 1 and R 2 are selected from the group consisting of a hydroxyalkyl group, an ether group, an aryl group, an aromatic-substituted alkyl group, an unsaturated hydrocarbon group, and an alkyl group).

<製造條件> <Manufacturing conditions>

電流密度:70~100A/dm2 Current density: 70 ~ 100A / dm 2

電解液溫度:50~60℃ Electrolyte temperature: 50 ~ 60 ℃

電解液線速度:3~5m/sec Linear speed of electrolyte: 3 ~ 5m / sec

電解時間:0.5~10分鐘(根據析出之銅厚、電流密度進行調整) Electrolysis time: 0.5 ~ 10 minutes (adjusted according to the copper thickness and current density)

再者,亦可於載體設置極薄銅層之側的表面為相反側的表面設置粗化處理層。可使用公知之方法設置該粗化處理層,亦可藉由上述粗化處理設置該粗化處理層。於載體設置極薄銅層之側的表面為相反側的表面設置粗化處理層之情況具有如下優點:當將載體自具有該粗化處理層之表面側積層於樹脂基板等支持體時,載體與樹脂基板變得難以剝離。 Furthermore, a roughening treatment layer may be provided on the surface on the side where the ultra-thin copper layer is provided on the carrier as the surface on the opposite side. The roughening treatment layer may be provided by a known method, or the roughening treatment layer may be provided by the above-mentioned roughening treatment. The case where the roughened layer is provided on the surface on the side where the ultra-thin copper layer is provided on the opposite side of the carrier has the advantage that when the carrier is laminated from a surface side having the roughened layer on a support such as a resin substrate, the carrier It becomes difficult to peel off from the resin substrate.

<中間層> <Middle layer>

於載體上設置中間層。亦可於載體與中間層之間設置其他層。於本發明中使用之中間層只要為如下述之構成,則並無特別限定,即於附載體銅箔向絕緣基板積層之步驟前,極薄銅層難以自載體剝離,另一方面,於向 絕緣基板積層之步驟後,極薄銅層可自載體剝離。例如,本發明之附載體銅箔的中間層亦可含有選自由Cr、Ni、Co、Fe、Mo、Ti、W、P、Cu、Al、Zn、該等之合金、該等之水合物、該等之氧化物、有機物組成之群中的1種或2種以上。又,中間層亦可為複數層。 An intermediate layer is provided on the carrier. Other layers may be provided between the carrier and the intermediate layer. The intermediate layer used in the present invention is not particularly limited as long as it has a structure as follows: before the step of laminating the copper foil with a carrier onto an insulating substrate, it is difficult to peel the ultra-thin copper layer from the carrier. After the step of laminating the insulating substrate, the ultra-thin copper layer can be peeled from the carrier. For example, the intermediate layer of the copper foil with a carrier of the present invention may also contain a material selected from the group consisting of Cr, Ni, Co, Fe, Mo, Ti, W, P, Cu, Al, Zn, these alloys, these hydrates, One or two or more of these oxides and organic compounds. The intermediate layer may be a plurality of layers.

又,例如,中間層可藉由如下方式構成:自載體側形成由選自以Cr、Ni、Co、Fe、Mo、Ti、W、P、Cu、Al、Zn構成之元素群中1種元素構成的單一金屬層,或由選自以Cr、Ni、Co、Fe、Mo、Ti、W、P、Cu、Al、Zn構成之元素群中1種或2種以上之元素構成的合金層,於其上形成由選自以Cr、Ni、Co、Fe、Mo、Ti、W、P、Cu、Al、Zn構成之元素群中1種或2種以上之元素的水合物或氧化物或有機物構成之層。 In addition, for example, the intermediate layer may be configured by forming one element selected from the group consisting of Cr, Ni, Co, Fe, Mo, Ti, W, P, Cu, Al, and Zn from the carrier side. A single metal layer or an alloy layer composed of one or more elements selected from the group consisting of Cr, Ni, Co, Fe, Mo, Ti, W, P, Cu, Al, and Zn, A hydrate, oxide, or organic substance of one or more elements selected from the group consisting of Cr, Ni, Co, Fe, Mo, Ti, W, P, Cu, Al, and Zn is formed thereon The layer of composition.

又,例如,中間層可藉由如下方式構成:自載體側形成由選自以Cr、Ni、Co、Fe、Mo、Ti、W、P、Cu、Al、Zn構成之元素群1種元素構成的單一金屬層,或由選自以Cr、Ni、Co、Fe、Mo、Ti、W、P、Cu、Al、Zn構成之元素群中1種或2種以上之元素構成的合金層,於其上形成由選自以Cr、Ni、Co、Fe、Mo、Ti、W、P、Cu、Al、Zn構成之元素群中1種元素構成的單一金屬層,或由選自以Cr、Ni、Co、Fe、Mo、Ti、W、P、Cu、Al、Zn構成之元素群中1種或2種以上之元素構成的合金層。 In addition, for example, the intermediate layer may be formed by forming one element selected from the group consisting of Cr, Ni, Co, Fe, Mo, Ti, W, P, Cu, Al, and Zn from the carrier side. A single metal layer, or an alloy layer composed of one or more elements selected from the group consisting of Cr, Ni, Co, Fe, Mo, Ti, W, P, Cu, Al, Zn, and A single metal layer composed of one element selected from the group consisting of Cr, Ni, Co, Fe, Mo, Ti, W, P, Cu, Al, and Zn is formed thereon, or a metal layer selected from Cr, Ni An alloy layer composed of one or two or more elements in the element group consisting of, Co, Fe, Mo, Ti, W, P, Cu, Al, and Zn.

又,中間層可使用公知之有機物作為上述有機物,又,較佳使用含氮有機化合物、含硫有機化合物及羧酸中之任一種以上。例如,作為具體之含氮有機化合物,較佳使用為具有取代基之三唑化合物的1,2,3-苯并三唑、羧基苯并三唑、N',N'-雙(苯并三唑基甲基)脲、1H-1,2,4-三唑及3-胺基-1H-1,2,4-三唑等。 The intermediate layer may use a known organic substance as the organic substance, and it is preferable to use any one or more of a nitrogen-containing organic compound, a sulfur-containing organic compound, and a carboxylic acid. For example, as the specific nitrogen-containing organic compound, 1,2,3-benzotriazole, carboxybenzotriazole, N ', N'-bis (benzotriazole), which is a triazole compound having a substituent, are preferably used. Oxazolylmethyl) urea, 1H-1,2,4-triazole, and 3-amino-1H-1,2,4-triazole.

含硫有機化合物較佳使用巰基苯并噻唑、2-巰基苯并噻唑鈉、三聚硫氰酸(thiocyanuric acid)及2-苯并咪唑硫醇等。 As the sulfur-containing organic compound, mercaptobenzothiazole, sodium 2-mercaptobenzothiazole, thiocyanuric acid, 2-benzimidazole thiol, and the like are preferably used.

作為羧酸,尤佳使用單羧酸,其中較佳使用油酸、亞麻油酸及次亞麻油酸等。 As the carboxylic acid, a monocarboxylic acid is particularly preferably used, and among them, oleic acid, linoleic acid, and linolenic acid are preferably used.

又,例如中間層可於載體上依序積層鎳層、鎳-磷合金層或鎳-鈷合金層、及含鉻層而構成。鎳與銅之接著力高於鉻與銅之接著力,因此於剝離極薄銅層時,於極薄銅層與含鉻層之界面會發生剝離。又,對於中間層之鎳,期待防止銅成分自載體向極薄銅層擴散之阻隔效果。中間層中之鎳的附著量較佳為100μg/dm2以上40000μg/dm2以下,更佳為100μg/dm2以上4000μg/dm2以下,更佳為100μg/dm2以上2500μg/dm2以下,更佳為100μg/dm2以上且未達1000μg/dm2,中間層中之鉻的附著量較佳為5μg/dm2以上100μg/dm2以下。僅於單面設置中間層之情形時,較佳於載體之相反面設置鍍Ni層等防銹層。上述中間層之鉻層可藉由鍍鉻或鉻酸處理來設置。 For example, the intermediate layer may be formed by sequentially stacking a nickel layer, a nickel-phosphorus alloy layer or a nickel-cobalt alloy layer, and a chromium-containing layer on a carrier. The adhesion force between nickel and copper is higher than the adhesion force between chromium and copper. Therefore, when the ultra-thin copper layer is peeled off, peeling occurs at the interface between the ultra-thin copper layer and the chromium-containing layer. Further, for the nickel in the intermediate layer, a barrier effect to prevent the copper component from diffusing from the carrier to the ultra-thin copper layer is expected. The amount of deposition of nickel intermediate layer is preferably from 100μg / dm 2 or more 40000μg / dm 2 or less, more preferably 100μg / dm 2 or more 4000μg / dm 2 or less, more preferably 100μg / dm 2 or more 2500μg / dm 2 or less, It is more preferably 100 μg / dm 2 or more and less than 1000 μg / dm 2 , and the adhesion amount of chromium in the intermediate layer is preferably 5 μg / dm 2 or more and 100 μg / dm 2 or less. When an intermediate layer is provided only on one side, it is preferable to provide a rust-proof layer such as a Ni plating layer on the opposite side of the carrier. The chromium layer of the intermediate layer can be provided by chromium plating or chromic acid treatment.

若中間層之厚度變得過大,則有時中間層之厚度會對表面處理後之極薄銅層表面的表面粗糙度Rz及光澤度造成影響,因此極薄銅層之表面處理層表面的中間層厚度較佳為1~1000nm,較佳為1~500nm,較佳為2~200nm,較佳為2~100nm,更佳為3~60nm。再者,中間層亦可設置於載體之兩面。 If the thickness of the intermediate layer becomes too large, the thickness of the intermediate layer may affect the surface roughness Rz and gloss of the surface of the ultra-thin copper layer after the surface treatment. The layer thickness is preferably 1 to 1000 nm, preferably 1 to 500 nm, preferably 2 to 200 nm, preferably 2 to 100 nm, and more preferably 3 to 60 nm. Furthermore, the intermediate layer may be provided on both sides of the carrier.

<極薄銅層> <Ultra-thin copper layer>

於中間層上設置極薄銅層。亦可於中間層與極薄銅層之間設置其他層。具有該載體之極薄銅層係作為本發明之一實施方式的表面處理金屬 材。極薄銅層之厚度並無特別限制,一般而言較載體薄,例如為12μm以下。典型為0.5~12μm,更典型為1.5~5μm。又,亦可於中間層上設置極薄銅層前,為了減少極薄銅層之針孔,而進行利用銅-磷合金之打底鍍敷(strike plating)。打底鍍敷可列舉焦磷酸銅鍍敷液等。再者,極薄銅層亦可設置於載體之兩面。極薄銅層可為含有銅合金之層,亦可為由銅合金構成之層,極薄銅層亦可含有有機物或無機物。再者,作為極薄銅層,較佳使用Cu濃度為75mass%以上之極薄銅層。其原因在於:Cu濃度為75mass%以上之極薄銅層的導電率高,適合於電路等用途。 An extremely thin copper layer is provided on the intermediate layer. Other layers may be provided between the intermediate layer and the ultra-thin copper layer. An extremely thin copper layer having the carrier is a surface-treated metal according to an embodiment of the present invention material. The thickness of the ultra-thin copper layer is not particularly limited, and is generally thinner than the carrier, for example, 12 μm or less. It is typically 0.5 to 12 μm, and more typically 1.5 to 5 μm. In addition, before the ultra-thin copper layer is provided on the intermediate layer, in order to reduce pinholes in the ultra-thin copper layer, a strike plating using a copper-phosphorus alloy may be performed. Examples of the primer plating include copper pyrophosphate plating solution. Furthermore, an ultra-thin copper layer can also be provided on both sides of the carrier. The ultra-thin copper layer may be a layer containing a copper alloy or a layer composed of a copper alloy, and the ultra-thin copper layer may also contain an organic substance or an inorganic substance. Furthermore, as the ultra-thin copper layer, an ultra-thin copper layer having a Cu concentration of 75 mass% or more is preferably used. The reason is that an extremely thin copper layer having a Cu concentration of 75 mass% or more has high electrical conductivity, and is suitable for applications such as circuits.

又,本發明之極薄銅層亦可為以下述條件形成之極薄銅層。其原因在於:藉由形成平滑之極薄銅層,而控制附載體銅箔之表面處理層的表面粗糙度Rz及表面積比。 The ultra-thin copper layer of the present invention may be an ultra-thin copper layer formed under the following conditions. The reason is that the surface roughness Rz and the surface area ratio of the surface treatment layer of the copper foil with a carrier are controlled by forming a smooth ultra-thin copper layer.

˙電解液組成 组成 Electrolyte composition

銅:80~120g/L Copper: 80 ~ 120g / L

硫酸:80~120g/L Sulfuric acid: 80 ~ 120g / L

氯:30~100ppm Chlorine: 30 ~ 100ppm

調平劑1(雙(3-磺丙基)二硫化物):10~30ppm Leveling agent 1 (bis (3-sulfopropyl) disulfide): 10 ~ 30ppm

調平劑2(胺化合物):10~30ppm Leveling agent 2 (amine compound): 10 ~ 30ppm

上述胺化合物可使用下述化學式之胺化合物。 As the amine compound, an amine compound of the following chemical formula can be used.

(上述化學式中,R1及R2為選自由羥烷基、醚基、芳基、經芳香族取代之烷基、不飽和烴基、烷基組成之群中者)。 (In the above chemical formula, R 1 and R 2 are selected from the group consisting of a hydroxyalkyl group, an ether group, an aryl group, an aromatic-substituted alkyl group, an unsaturated hydrocarbon group, and an alkyl group).

˙製造條件 ˙Manufacturing conditions

電流密度:70~100A/dm2 Current density: 70 ~ 100A / dm 2

電解液溫度:50~65℃ Electrolyte temperature: 50 ~ 65 ℃

電解液線速度:1.5~5m/sec Linear speed of electrolyte: 1.5 ~ 5m / sec

電解時間:0.5~10分鐘(根據析出之銅厚、電流密度進行調整) Electrolysis time: 0.5 ~ 10 minutes (adjusted according to the copper thickness and current density)

以下,揭示若干使用本發明之附載體銅箔的印刷配線板製造步驟之例。 Hereinafter, some examples of manufacturing steps of a printed wiring board using the copper foil with a carrier of the present invention will be disclosed.

於本發明之印刷配線板製造方法的一實施形態中,包括如下步驟:準備本發明之附載體銅箔與絕緣基板之步驟;將上述附載體銅箔與絕緣基板積層之步驟;將上述附載體銅箔與絕緣基板以極薄銅層側與絕緣基板對向之方式積層後,經過剝離上述附載體銅箔之載體的步驟而形成覆銅積層板,然後藉由半加成法、改良半加成法、部分加成法及減成法中之任一方法形成電路之步驟。絕緣基板亦可為具有內層電路之絕緣基板。 An embodiment of the method for manufacturing a printed wiring board of the present invention includes the following steps: a step of preparing the copper foil with a carrier and an insulating substrate of the present invention; a step of laminating the copper foil with a carrier and an insulating substrate; After the copper foil and the insulating substrate are laminated in such a way that the ultra-thin copper layer side faces the insulating substrate, the copper-clad laminated board is formed through the step of peeling the carrier of the copper foil with a carrier, and then the semi-additive method is used to improve the semi-additive The steps of forming a circuit by any of the formation method, partial addition method, and subtraction method. The insulating substrate may also be an insulating substrate having an inner-layer circuit.

於本發明中,所謂半加成法係指下述方法:於絕緣基板或銅 箔種晶層(seed layer)上進行薄的無電鍍敷,形成圖案後,使用電鍍及蝕刻形成導體圖案。 In the present invention, the so-called semi-additive method refers to the following method: on an insulating substrate or copper A thin electroless plating is performed on the foil seed layer to form a pattern, and then a conductor pattern is formed using plating and etching.

因此,於使用半加成法之本發明之印刷配線板製造方法的一 實施形態中,包括如下步驟:準備本發明之附載體銅箔與絕緣基板之步驟;將上述附載體銅箔與絕緣基板積層之步驟;積層上述附載體銅箔與絕緣基板後,將上述附載體銅箔之載體剝離之步驟;藉由使用酸等腐蝕溶液之蝕刻或電漿等方法,將經剝離上述載體而露出之極薄銅層全部去除之步驟;於藉由蝕刻將上述極薄銅層去除而露出之上述樹脂,設置穿孔(through hole)或/及盲孔(blind via)之步驟;對含有上述穿孔或/及盲孔之區域進行除膠渣處理(desmear treatment)之步驟;對含有上述樹脂及上述穿孔或/及盲孔之區域設置無電鍍層之步驟;於上述無電鍍層上設置鍍敷阻劑之步驟;對上述鍍敷阻劑進行曝光,然後將形成電路之區域的鍍敷阻劑去除之步驟;於經去除上述鍍敷阻劑之形成上述電路的區域設置電鍍層之步驟;將上述鍍敷阻劑去除之步驟;藉由快速蝕刻(flash etching)等,將存在於形成上述電路之區域以外之區域的無電鍍層去除之步驟。 Therefore, a method for manufacturing a printed wiring board of the present invention using a semi-additive method The embodiment includes the following steps: a step of preparing the copper foil with a carrier and an insulating substrate of the present invention; a step of laminating the copper foil with a carrier and an insulating substrate; a layer of the copper foil with a carrier and an insulating substrate; The step of peeling the carrier of the copper foil; the step of completely removing the ultra-thin copper layer exposed by peeling the carrier by etching using an etching solution such as an acid or plasma, etc .; and removing the ultra-thin copper layer by etching The above-mentioned resin exposed and removed is provided with a step of through hole or / and blind via; a step of performing desmear treatment on the area containing the above hole or / and blind via; A step of providing an electroless plating layer on the above resin and the above-mentioned perforations or / and blind holes; a step of providing a plating resist on the above electroless plating layer; exposing the above plating resist, and then plating the area where the circuit is formed The step of removing the resist; the step of providing a plating layer in the area where the circuit is formed after removing the plating resist; the step of removing the plating resist; by rapid etching (f lash etching) and the like, a step of removing an electroless plating layer existing in a region other than a region where the circuit is formed.

於使用半加成法之本發明之印刷配線板製造方法的另一實 施形態中,包括如下步驟:準備本發明之附載體銅箔與絕緣基板之步驟;將上述附載體銅箔與絕緣基板積層之步驟;積層上述附載體銅箔與絕緣基板後,將上述附載體銅箔之載體剝離之步驟;藉由使用酸等腐蝕溶液之蝕刻或電漿等方法,將經剝離上述載體而露出之極薄銅層全部去除之步驟;對藉由蝕刻將上述極薄銅層去除而露出之上述樹脂的表面,設置無電鍍層之步驟;於上述無電鍍層上設置鍍敷阻劑之步驟;對上述鍍敷阻劑進行曝 光,然後將形成電路之區域的鍍敷阻劑去除之步驟;於經去除上述鍍敷阻劑之形成上述電路的區域設置電鍍層之步驟;將上述鍍敷阻劑去除之步驟;藉由快速蝕刻等,將存在於形成上述電路之區域以外之區域的無電鍍層及極薄銅層去除之步驟。 Another embodiment of the method for manufacturing a printed wiring board of the present invention using a semi-additive method The embodiment includes the following steps: preparing the copper foil with a carrier and an insulating substrate of the present invention; laminating the copper foil with a carrier and an insulating substrate; laminating the copper foil with a carrier and the insulating substrate; The step of peeling the carrier of the copper foil; the step of removing all the ultra-thin copper layer exposed by peeling the carrier by etching using an etching solution such as an acid or a plasma; the method of removing the ultra-thin copper layer by etching A step of providing an electroless plating layer on the surface of the resin that is removed and exposed; a step of providing a plating resist on the electroless plating layer; and exposing the plating resist Light, and then the step of removing the plating resist in the area where the circuit is formed; the step of providing a plating layer in the area where the circuit is formed after removing the plating resist; the step of removing the plating resist; A step of removing an electroless plating layer and an ultra-thin copper layer existing in a region other than a region where the circuit is formed by etching or the like.

於本發明中,所謂改良半加成法係指下述方法:於絕緣層上 積層金屬箔,利用鍍敷阻劑保護非電路形成部,藉由電鍍增加電路形成部之銅厚後,去除阻劑,藉由(快速)蝕刻去除上述電路形成部以外之金屬箔,藉此於絕緣層上形成電路。 In the present invention, the so-called modified semi-additive method refers to the following method: on the insulating layer Laminated metal foil protects the non-circuit forming part with a plating resist. After the copper thickness of the circuit forming part is increased by electroplating, the resist is removed, and the metal foil other than the circuit forming part is removed by (rapid) etching. A circuit is formed on the insulating layer.

因此,於使用改良半加成法之本發明之印刷配線板製造方法 的一實施形態中,包括如下步驟:準備本發明之附載體銅箔與絕緣基板之步驟;將上述附載體銅箔與絕緣基板積層之步驟;積層上述附載體銅箔與絕緣基板後,將上述附載體銅箔之載體剝離之步驟;於將上述載體剝離而露出之極薄銅層與絕緣基板,設置穿孔或/及盲孔之步驟;對含有上述穿孔或/及盲孔之區域進行除膠渣處理之步驟;對含有上述穿孔或/及盲孔之區域設置無電鍍層之步驟;於將上述載體剝離而露出之極薄銅層表面,設置鍍敷阻劑之步驟;設置上述鍍敷阻劑後,藉由電鍍形成電路之步驟;將上述鍍敷阻劑去除之步驟;藉由快速蝕刻,將藉由去除上述鍍敷阻劑而露出之極薄銅層去除之步驟。 Therefore, a method for manufacturing a printed wiring board of the present invention using an improved semi-additive method In one embodiment, the method includes the following steps: preparing the copper foil with a carrier and an insulating substrate of the present invention; laminating the copper foil with a carrier and an insulating substrate; laminating the copper foil with a carrier and the insulating substrate; The step of peeling the carrier with the copper foil with the carrier; the step of setting a perforation or / and a blind hole in the ultra-thin copper layer and the insulating substrate exposed by peeling the above carrier; and removing the glue in the area containing the perforation or / and the blind hole Step of slag treatment; step of providing an electroless plating layer on the area containing the above-mentioned perforations or / and blind holes; step of setting a plating resist on the surface of the ultra-thin copper layer exposed by peeling the carrier; setting of the above-mentioned plating resist A step of forming a circuit by electroplating after plating; a step of removing the above-mentioned plating resist; a step of removing an extremely thin copper layer exposed by removing the above-mentioned plating resist by rapid etching.

又,將電路形成於上述樹脂層上之步驟,亦可為將另外之附 載體銅箔自極薄銅層側貼合於上述樹脂層上,使用貼合於上述樹脂層之附載體銅箔形成上述電路之步驟。又,貼合於上述樹脂層上之另外之附載體銅箔,亦可為本發明之附載體銅箔。又,於上述樹脂層上形成電路之步驟, 亦可藉由半加成法、減成法、部分加成法或改良半加成法中之任一方法進行。又,於上述表面形成電路之附載體銅箔,亦可於該附載體銅箔之載體的表面具有基板或樹脂層。 In addition, the step of forming a circuit on the resin layer may be an additional step The carrier copper foil is bonded to the resin layer from the side of the ultra-thin copper layer, and the above-mentioned circuit is formed by using the copper foil with a carrier attached to the resin layer. Moreover, another copper foil with a carrier adhered to the said resin layer may also be the copper foil with a carrier of this invention. In addition, the step of forming a circuit on the resin layer, It may be performed by any one of a semi-additive method, a subtractive method, a partial additive method, or an improved semi-additive method. Moreover, the copper foil with a carrier which forms a circuit on the said surface may have a board | substrate or a resin layer on the surface of the said copper foil with a carrier.

於使用改良半加成法的本發明之印刷配線板製造方法之另 一實施形態中,包括如下步驟:準備本發明之附載體銅箔與絕緣基板之步驟;將上述附載體銅箔與絕緣基板積層之步驟;積層上述附載體銅箔與絕緣基板後,將上述附載體銅箔之載體剝離之步驟;於將上述載體剝離而露出之極薄銅層上設置鍍敷阻劑之步驟;對上述鍍敷阻劑進行曝光,然後將形成電路之區域的鍍敷阻劑去除之步驟;於經去除上述鍍敷阻劑之形成上述電路的區域,設置電鍍層之步驟;將上述鍍敷阻劑去除之步驟;藉由快速蝕刻等,將存在於形成上述電路之區域以外之區域的無電鍍層及極薄銅層去除之步驟。 Another method for manufacturing a printed wiring board of the present invention using an improved semi-additive method In one embodiment, the method includes the following steps: preparing the copper foil with a carrier and an insulating substrate according to the present invention; laminating the copper foil with a carrier and an insulating substrate; laminating the copper foil with a carrier and the insulating substrate; The step of peeling the carrier of the copper foil of the carrier; the step of setting a plating resist on the extremely thin copper layer exposed by peeling the carrier; exposing the above plating resist, and then plating the resist in the area where the circuit is formed A step of removing; a step of providing an electroplated layer in a region where the above-mentioned circuit is formed by removing the above-mentioned plating resist; a step of removing the above-mentioned plating resist; by rapid etching etc., it will exist outside the region where the above-mentioned circuit is formed Step of removing the electroless plating layer and the ultra-thin copper layer in the area.

於本發明中,所謂部分加成法係指下述方法:向設有導體層 而成之基板、視需要開出穿孔或通孔(via hole)用之孔之基板上賦予觸媒核,進行蝕刻而形成導體電路,視需要設置阻焊劑或鍍敷阻劑後,在上述導體電路上,藉由無電鍍敷處理對穿孔或通孔等進行增厚,藉此製造印刷配線板。 In the present invention, the so-called partial addition method refers to a method in which a conductive layer is provided The formed substrate and the substrate with holes or via holes (if necessary) are provided with a catalyst core and etched to form a conductor circuit. If necessary, a solder resist or a plating resist is provided, and then the above conductor is provided. On a circuit, a printed wiring board is manufactured by thickening perforations, through holes, and the like by an electroless plating process.

因此,於使用部分加成法的本發明之印刷配線板製造方法之 一實施形態中,包括如下步驟:準備本發明之附載體銅箔與絕緣基板之步驟;將上述附載體銅箔與絕緣基板積層之步驟;積層上述附載體銅箔與絕緣基板後,將上述附載體銅箔之載體剝離之步驟;於剝離上述載體而露出之極薄銅層與絕緣基板,設置穿孔或/及盲孔之步驟;對含有上述穿孔或 /及盲孔之區域進行除膠渣處理之步驟;向含有上述穿孔或/及盲孔之區域賦予觸媒核之步驟;於經剝離上述載體而露出之極薄銅層表面設置抗蝕劑之步驟;對上述抗蝕劑進行曝光,形成電路圖案之步驟;藉由使用酸等腐蝕溶液之蝕刻或電漿等方法,將上述極薄銅層及上述觸媒核去除而形成電路之步驟;將上述抗蝕劑去除之步驟;於藉由使用酸等腐蝕溶液之蝕刻或電漿等方法,將上述極薄銅層及上述觸媒核去除而露出之上述絕緣基板表面,設置阻焊劑或鍍敷阻劑之步驟;於未設置有上述阻焊劑或鍍敷阻劑之區域設置無電鍍層之步驟。 Therefore, in the method for manufacturing a printed wiring board of the present invention using a partial addition method, In one embodiment, the method includes the following steps: preparing the copper foil with a carrier and an insulating substrate according to the present invention; laminating the copper foil with a carrier and an insulating substrate; laminating the copper foil with a carrier and the insulating substrate; The step of peeling the carrier of the copper foil of the carrier; the step of providing a perforation or / and a blind hole in the ultra-thin copper layer and the insulating substrate exposed by peeling the above carrier; / And the process of removing the glue residue in the area of the blind hole; the step of providing a catalyst core to the area containing the above-mentioned perforation or / and the blind hole; Step; a step of exposing the resist to form a circuit pattern; a step of forming a circuit by removing the ultra-thin copper layer and the catalyst core by an etching method using an etching solution such as an acid or a plasma; The step of removing the above-mentioned resist; setting a solder resist or plating on the surface of the insulating substrate exposed by removing the ultra-thin copper layer and the catalyst core by using etching or plasma using an etching solution such as an acid, etc. Resist step; a step of providing an electroless plating layer in an area where the above solder resist or plating resist is not provided.

於本發明中,所謂減成法係指下述方法:藉由蝕刻等,選擇 性地將覆銅積層板上之銅箔的不要部分去除,形成導體圖案。 In the present invention, the so-called subtractive method refers to the following method: selection by etching or the like The unnecessary part of the copper foil on the copper-clad laminated board is removed, and a conductor pattern is formed.

因此,於使用減成法的本發明之印刷配線板製造方法之一實 施形態中,包括如下步驟:準備本發明之附載體銅箔與絕緣基板之步驟;將上述附載體銅箔與絕緣基板積層之步驟;積層上述附載體銅箔與絕緣基板後,將上述附載體銅箔之載體剝離之步驟;於剝離上述載體而露出之極薄銅層與絕緣基板,設置穿孔或/及盲孔之步驟;對含有上述穿孔及/或盲孔之區域進行除膠渣處理之步驟;對含有上述穿孔或/及盲孔之區域設置無電鍍層之步驟;於上述無電鍍層之表面設置電鍍層之步驟;於上述電鍍層或/及上述極薄銅層之表面設置抗蝕劑之步驟;對上述抗蝕劑進行曝光,形成電路圖案之步驟;藉由使用酸等腐蝕溶液之蝕刻或電漿等方法,將上述極薄銅層及上述無電鍍層及上述電鍍層去除,形成電路之步驟;將上述抗蝕劑去除之步驟。 Therefore, it is one of the methods for manufacturing a printed wiring board of the present invention using a subtractive method. The embodiment includes the following steps: preparing the copper foil with a carrier and an insulating substrate of the present invention; laminating the copper foil with a carrier and an insulating substrate; laminating the copper foil with a carrier and the insulating substrate; The step of peeling the carrier of the copper foil; the step of providing perforations or blind holes in the ultra-thin copper layer and the insulating substrate exposed by peeling the above-mentioned carrier; Step; a step of providing an electroless plating layer on the area containing the above-mentioned perforations or / and blind holes; a step of providing a plating layer on the surface of the above-mentioned electroless plating layer; providing a resist on the surface of the above-mentioned plating layer or / and the ultra-thin copper layer Step of exposing the resist; forming a circuit pattern by exposing the resist; removing the ultra-thin copper layer, the electroless plating layer, and the electroplating layer by etching or plasma using an etching solution such as an acid, A step of forming a circuit; a step of removing the resist.

於使用減成法的本發明之印刷配線板製造方法之另一實施 形態中,包括如下步驟:準備本發明之附載體銅箔與絕緣基板之步驟;將上述附載體銅箔與絕緣基板積層之步驟;積層上述附載體銅箔與絕緣基板後,將上述附載體銅箔之載體剝離之步驟;於經剝離上述載體而露出之極薄銅層與絕緣基板,設置穿孔或/及盲孔之步驟;對含有上述穿孔或/及盲孔之區域進行除膠渣處理之步驟;對含有上述穿孔或/及盲孔之區域設置無電鍍層之步驟;於上述無電鍍層之表面形成遮罩之步驟;於未形成遮罩之上述無電鍍層之表面設置電鍍層之步驟;於上述電鍍層或/及上述極薄銅層之表面設置抗蝕劑之步驟;對上述抗蝕劑進行曝光,形成電路圖案之步驟;藉由使用酸等腐蝕溶液之蝕刻或電漿等方法,將上述極薄銅層及上述無電鍍層去除,形成電路之步驟;將上述抗蝕劑去除之步驟。 Another implementation of the printed wiring board manufacturing method of the present invention using the subtractive method The form includes the following steps: preparing the copper foil with a carrier and an insulating substrate of the present invention; laminating the copper foil with a carrier and the insulating substrate; laminating the copper foil with a carrier and the insulating substrate; The step of peeling the carrier of the foil; the step of providing perforations or blind holes in the ultra-thin copper layer and the insulating substrate exposed by peeling the above carrier; Steps: a step of providing an electroless plating layer on the area containing the above-mentioned perforations or / and blind holes; a step of forming a mask on the surface of the above electroless plating layer; a step of providing a plating layer on the surface of the above electroless plating layer where no mask is formed ; A step of providing a resist on the surface of the above-mentioned electroplated layer or / and the above-mentioned extremely thin copper layer; a step of exposing the above-mentioned resist to form a circuit pattern; by an etching method using an etching solution such as an acid or a plasma A step of removing the ultra-thin copper layer and the electroless plating layer to form a circuit; and a step of removing the resist.

設置穿孔或/及盲孔之步驟及其後之除膠渣步驟,亦可不進 行。 The step of setting perforation or / and blind hole and the subsequent step of removing glue residue can be omitted. Row.

此處,詳細說明使用本發明之附載體銅箔的印刷配線板製造 方法之具體例。再者,此處雖以具有形成有粗化處理層之極薄銅層的附載體銅箔為例進行說明,但並不限於此,使用具有未形成粗化處理層之極薄銅層的附載體銅箔亦可同樣地進行下述之印刷配線板製造方法。 Here, the manufacturing of a printed wiring board using the copper foil with a carrier of the present invention will be described in detail. Specific examples of methods. Here, although a copper foil with a carrier having an ultra-thin copper layer formed with a roughened layer is described as an example, the present invention is not limited to this. The carrier copper foil can be similarly subjected to the following printed wiring board manufacturing method.

首先,準備具有表面形成有粗化處理層之極薄銅層的附載體銅箔(第1層)。 First, a copper foil with a carrier (first layer) having an ultra-thin copper layer having a roughened layer formed on the surface is prepared.

其次,於極薄銅層之粗化處理層上塗佈阻劑,進行曝光、顯影,而將阻劑蝕刻為既定形狀。 Next, a resist is coated on the roughened layer of the ultra-thin copper layer, exposed and developed, and the resist is etched into a predetermined shape.

其次,形成電路用之鍍敷後,將阻劑去除,藉此形成既定形狀之電路鍍敷。 Secondly, after forming a plating for a circuit, the resist is removed, thereby forming a circuit plating of a predetermined shape.

其次,以覆蓋電路鍍敷之方式(掩埋電路鍍敷之方式)於極薄銅層上設置嵌入樹脂而積層樹脂層,繼而使另外之附載體銅箔(第2層)自極薄銅層側接著。 Next, the resin layer is laminated on the ultra-thin copper layer by covering the circuit plating method (the method of burying the circuit plating method), and then the other copper foil with a carrier (the second layer) is placed from the side of the ultra-thin copper layer. then.

其次,自第2層之附載體銅箔剝離載體。 Next, the carrier was peeled from the copper foil with a carrier of the second layer.

其次,於樹脂層之既定位置進行雷射開孔,使電路鍍敷露出而形成盲孔 Secondly, laser drilling is performed at a predetermined position of the resin layer to expose the circuit plating and form blind holes.

其次,向盲孔埋入銅而形成填孔(via fill)。 Second, copper is buried in the blind via to form a via fill.

其次,於填孔上,以上述方式形成電路鍍敷。 Next, a circuit plating is formed on the hole filling in the manner described above.

其次,自第1層附載體銅箔剝離載體。 Next, the carrier was peeled from the first layer of copper foil with a carrier.

其次,藉由快速蝕刻將兩表面之極薄銅層去除,而使樹脂層內之電路鍍敷的表面露出。 Secondly, the ultra-thin copper layers on both surfaces are removed by rapid etching, so that the surface of the circuit plating in the resin layer is exposed.

其次,於樹脂層內之電路鍍敷上形成凸塊,於該焊料上形成銅柱(pillar)。以此方式製作使用本發明之附載體銅箔的印刷配線板。 Second, bumps are formed on the circuit plating in the resin layer, and copper pillars are formed on the solder. In this way, a printed wiring board using the copper foil with a carrier of the present invention was produced.

上述另外之附載體銅箔(第2層),可使用本發明之附載體 銅箔,亦可使用以往之附載體銅箔,進而可使用通常之銅箔。又,亦可於上述第2層之電路上進而形成1層或複數層之電路,亦可藉由半加成法、減成法、部分加成法或改良半加成法中之任一種方法進行該等之電路形成。 The above additional copper foil with carrier (second layer) can be used with the carrier of the present invention As the copper foil, a conventional copper foil with a carrier may be used, and further, a usual copper foil may be used. In addition, a circuit of one layer or a plurality of layers can be formed on the circuit of the second layer, and any one of a semi-additive method, a subtractive method, a partial additive method, or an improved semi-additive method can be used. Perform such circuit formation.

本發明之附載體銅箔較佳以滿足以下(1)之方式控制極薄 銅層表面之色差。於本發明中,所謂「極薄銅層表面之色差」係表示極薄銅層之表面之色差,或於實施有粗化處理等各種表面處理之情形時表示該表面處理層表面之色差。即,本發明之附載體銅箔較佳以滿足以下(1)之方式控制極薄銅層之粗化處理表面之色差。再者,於本發明之表面處理金 屬材中,所謂「粗化處理表面」,係指於粗化處理後,進行用以設置耐熱層、防銹層、耐候性層等之表面處理的情形時,進行該表面處理後之表面處理金屬材(極薄銅層)的表面。又,於表面處理金屬材為附載體銅箔之極薄銅層的情形時,所謂「粗化處理表面」,係指於粗化處理後,進行用以設置耐熱層、防銹層、耐候性層等之表面處理的情形時,進行該表面處理後之極薄銅層的表面。 The copper foil with a carrier of the present invention is preferably controlled to be extremely thin in a manner satisfying the following (1) Color difference on the surface of the copper layer. In the present invention, the "color difference on the surface of the ultra-thin copper layer" means the color difference on the surface of the ultra-thin copper layer, or the color difference on the surface of the surface-treated layer when various surface treatments such as roughening treatment are performed. That is, the copper foil with a carrier of the present invention preferably satisfies the following (1) to control the color difference of the roughened surface of the ultra-thin copper layer. Furthermore, the surface-treated gold of the present invention The term "roughened surface" refers to the case where after the roughening treatment, a surface treatment for providing a heat-resistant layer, a rust-proof layer, and a weather-resistant layer is performed, the surface treatment after the surface treatment is performed. The surface of a metal material (extremely thin copper layer). When the surface-treated metal material is an extremely thin copper layer with a copper foil with a carrier, the so-called "roughened surface" refers to the provision of a heat-resistant layer, a rust-proof layer, and weather resistance after the roughening treatment. In the case of a surface treatment of a layer or the like, the surface of the ultra-thin copper layer after the surface treatment is performed.

(1)關於極薄銅層表面之色差,基於JIS Z8730之色差△E*ab為45以上。 (1) Regarding the color difference on the surface of the ultra-thin copper layer, the color difference ΔE * ab based on JIS Z8730 is 45 or more.

此處,色差△L、△a、△b係分別利用色差計測量,加上黑 /白/紅/綠/黃/藍,使用基於JIS Z8730之L*a*b表色系統進行表示之綜合指標,以△L:白黑、△a:紅綠、△b:黃藍之形式表示。又,△E*ab係使用此等色差以下式表示。 Here, the color differences ΔL, △ a, and Δb are measured by a color difference meter, respectively, and the black / White / red / green / yellow / blue, a comprehensive indicator expressed using the L * a * b color system based on JIS Z8730, in the form of △ L: white and black, △ a: red and green, △ b: yellow and blue Means. In addition, ΔE * ab is expressed by the following formula using these color differences.

上述之色差可藉由提高形成極薄銅層時之電流密度,降低鍍敷液中之銅濃度,提高鍍敷液之線流速,來進行調整。 The aforementioned color difference can be adjusted by increasing the current density when forming an extremely thin copper layer, reducing the copper concentration in the plating solution, and increasing the linear flow velocity of the plating solution.

又,上述之色差亦可藉由對極薄銅層之表面實施粗化處理來設置粗化處理層,而進行調整。於設置粗化處理層之情形時,可藉由使用含有銅及選自由鎳、鈷、鎢、鉬組成之群中1種以上之元素的電解液,並使電流密度高於以往之電流密度(例如40~60A/dm2),使處理時間短於以往之處理時間(例如0.1~1.3秒),而進行調整。於極薄銅層之表面未設置粗化處理層之情形時,可藉由下述方式來達成:使用將Ni濃度設為其他元素之2 倍以上的鍍浴,用低於以往之電流密度(0.1~1.3A/dm2),並將處理時間(20秒~40秒)設定得較長,而對極薄銅層或耐熱層或防銹層或鉻酸處理層或矽烷偶合處理層之表面進行Ni合金鍍敷(例如Ni-W合金鍍敷、Ni-Co-P合金鍍敷、Ni-Zn合金鍍敷)處理。 In addition, the aforementioned chromatic aberration can also be adjusted by providing a roughening treatment layer by performing a roughening treatment on the surface of the ultra-thin copper layer. When a roughening treatment layer is provided, an electrolytic solution containing copper and one or more elements selected from the group consisting of nickel, cobalt, tungsten, and molybdenum can be used to make the current density higher than the conventional current density ( For example, 40 to 60 A / dm 2 ), the processing time is adjusted to be shorter than the conventional processing time (for example, 0.1 to 1.3 seconds). In the case where the surface of the ultra-thin copper layer is not provided with a roughening treatment layer, it can be achieved by using a plating bath having a Ni concentration of 2 times or more of other elements, and using a current density lower than that in the past ( 0.1 ~ 1.3A / dm 2 ), and set the processing time (20 seconds ~ 40 seconds) longer, and the surface of the ultra-thin copper layer or heat-resistant layer or rust-proof layer or chromic acid-treated layer or silane coupling treatment layer Ni alloy plating (for example, Ni-W alloy plating, Ni-Co-P alloy plating, Ni-Zn alloy plating) is performed.

關於極薄銅層表面之色差,若基於JIS Z8730之色差△E* ab為45以上,則例如於附載體銅箔之極薄銅層表面形成電路時,極薄銅層與電路之對比變得鮮明,結果,視認性變良好,而可精度良好地進行電路之位置對準。極薄銅層表面基於JIS Z8730之色差△E*ab較佳為50以上,更佳為55以上,再更佳為60以上。 Regarding the color difference on the surface of the ultra-thin copper layer, if the color difference based on JIS Z8730 is △ E * If ab is 45 or more, for example, when a circuit is formed on the surface of an ultra-thin copper layer with a copper foil with a carrier, the contrast between the ultra-thin copper layer and the circuit becomes clear. As a result, the visibility is improved, and the circuit position can be accurately performed alignment. The color difference ΔE * ab of the surface of the ultra-thin copper layer based on JIS Z8730 is preferably 50 or more, more preferably 55 or more, and even more preferably 60 or more.

當以上述方式控制極薄銅層表面之色差的情形時,與電路鍍 敷之對比變得鮮明,視認性變良好。因此,於如上述之印刷配線板之製造步驟中,可精度良好地於既定位置形成電路鍍敷。又,根據如上述之印刷配線板之製造方法,成為電路鍍敷埋入樹脂層之構成,因此,例如於上述藉由快速蝕刻去除極薄銅層時,電路鍍敷受到樹脂層保護,其形狀得以保持,藉此變得容易形成細微電路。又,由於電路鍍敷受到樹脂層保護,因此耐遷移性提高,而良好地抑制電路之配線的導通。因此,變得容易形成細微電路。又,於藉由快速蝕刻去除極薄銅層時,電路鍍敷之露出面成為自樹脂層凹陷之形狀,因此變得容易於該電路鍍敷上形成凸塊,並且變得容易於其上形成銅柱,製造效率提高。 When the color difference of the surface of the ultra-thin copper layer is controlled in the above manner, The contrast becomes clear and the visibility becomes better. Therefore, in the manufacturing steps of the printed wiring board as described above, it is possible to form a circuit plating at a predetermined position with high accuracy. In addition, according to the manufacturing method of the printed wiring board as described above, the circuit plating is embedded with a resin layer. Therefore, for example, when the ultra-thin copper layer is removed by rapid etching as described above, the circuit plating is protected by the resin layer and has a shape. It is maintained, thereby making it easy to form a minute circuit. In addition, since the circuit plating is protected by the resin layer, the migration resistance is improved, and the conduction of the wiring of the circuit is well suppressed. Therefore, it becomes easy to form a fine circuit. In addition, when the ultra-thin copper layer is removed by rapid etching, the exposed surface of the circuit plating becomes a shape recessed from the resin layer, so it is easy to form bumps on the circuit plating, and it is easy to form the bumps thereon. Copper pillars improve manufacturing efficiency.

再者,嵌入樹脂(RESIN)可使用公知之樹脂、預浸體。例 如,可使用BT(雙順丁烯二醯亞胺三)樹脂或為含浸有BT樹脂之玻璃布的預浸體、Ajinomoto Fine-Techno股份有限公司製ABF膜或ABF。又,前 述嵌入樹脂(樹脂)可使用本說明書記載之樹脂層及/或樹脂及/或預浸體。 In addition, as the embedding resin (RESIN), a known resin or prepreg can be used. For example, BT (biscis ) Resin or prepreg of glass cloth impregnated with BT resin, ABF film or ABF made by Ajinomoto Fine-Techno Co., Ltd. As the embedding resin (resin), a resin layer and / or a resin and / or a prepreg described in this specification can be used.

又,前述被用於第一層之附載體銅箔,在該附載體銅箔之表 面亦可具有基板或樹脂層。被用於第一層之附載體銅箔因具有該基板或樹脂層而會獲得支持,不易產生皺摺,因此具有提升生產性之優點。另,前述基板或樹脂層若為具有支持被用於前述第一層之附載體銅箔的效果者,則可使用所有的基板或樹脂層。例如可使用本案說明書記載之載體、預浸體、樹脂層或公知的載體、預浸體、樹脂層、金屬板、金屬箔、無機化合物之板、無機化合物之箔、有機化合物之板、有機化合物之箔作為前述基板或樹脂層。 The copper foil with a carrier used for the first layer is described in the table of the copper foil with a carrier. The surface may have a substrate or a resin layer. The copper foil with a carrier used for the first layer is supported by the substrate or the resin layer, and is not prone to wrinkles, so it has the advantage of improving productivity. In addition, as long as the substrate or the resin layer has the effect of supporting the copper foil with a carrier used in the first layer, all the substrates or the resin layer can be used. For example, a carrier, a prepreg, a resin layer or a known carrier, a prepreg, a resin layer, a metal plate, a metal foil, a plate of an inorganic compound, a plate of an inorganic compound, a plate of an organic compound, or an organic compound may be used as described in the specification of this case. The foil serves as the aforementioned substrate or resin layer.

[實施例] [Example]

準備厚度18μm之壓延銅箔(JX日礦日石金屬公司製造之C1100)或厚度18μm之電解銅箔,作為實施例1~10及比較例1~6之銅箔基材。 A rolled copper foil (C1100 manufactured by JX Nippon Nissei Metals Co., Ltd.) or an electrolytic copper foil with a thickness of 18 μm was prepared as the copper foil substrates of Examples 1 to 10 and Comparative Examples 1 to 6.

其次,於表1~2所示之條件下進行鍍敷,作為表面處理。實施例1~4,係對藉由上述方法所製作之電解銅箔的析出面(Rz 0.6μm)進行表面處理,實施例5~7及比較例1、4~6,則是對上述電解銅箔之轉筒面(Rz 1.5μm)進行表面處理。比較例2、3,係利用不含有調平劑之電解液對所製作之電解銅箔的析出面(Rz 2.0μm)進行表面處理。又,實施例8~10係對控制為既定之表面粗糙度的壓延銅箔進行表面處理。表1表示各鍍敷液1~10之液組成、pH值、溫度、電流密度。表2表示以所記載之浴組成及時間依序進行鍍敷處理1~3。再者,於該鍍敷後藉由Zn、Ni或該等之合金鍍敷、 及鉻酸處理,確保耐熱性,並且藉由塗佈矽烷偶合劑提高剝離強度。 Next, plating was performed under the conditions shown in Tables 1 to 2 as a surface treatment. Examples 1 to 4 are surface-treated on the precipitation surface (Rz 0.6 μm) of the electrolytic copper foil produced by the above method. Examples 5 to 7 and Comparative Examples 1, 4 to 6 are for the above electrolytic copper foil. The roll surface (Rz 1.5 μm) of the foil was surface-treated. In Comparative Examples 2 and 3, the deposition surface (Rz 2.0 μm) of the produced electrolytic copper foil was surface-treated with an electrolytic solution containing no leveling agent. In addition, Examples 8 to 10 performed surface treatment on a rolled copper foil controlled to a predetermined surface roughness. Table 1 shows the liquid composition, pH value, temperature, and current density of each of the plating solutions 1 to 10. Table 2 shows that the plating treatments 1 to 3 were performed sequentially with the bath composition and time described. Furthermore, after the plating, Zn, Ni, or an alloy thereof is plated, And chromic acid treatment to ensure heat resistance and increase peel strength by applying a silane coupling agent.

矽烷偶合劑之塗佈條件如下。 The application conditions of the silane coupling agent are as follows.

˙3-甲基丙烯醯氧基丙基三甲氧基矽烷 ˙3-Methacryl 醯 methoxypropyltrimethoxysilane

˙矽烷濃度:0.6vol%(剩餘部分:水) ˙ Silane concentration: 0.6vol% (the rest: water)

˙處理溫度:30~40℃ ˙Processing temperature: 30 ~ 40 ℃

˙處理時間:5秒 ˙ Processing time: 5 seconds

˙矽烷處理後之乾燥:100℃×3秒 干燥 Drying after silane treatment: 100 ℃ × 3 seconds

再者,實施例1、9及下述之實施例11的表面處理相當於平滑鍍敷處理(並非粗化處理之表面處理),除此以外之實施例及比較例中的表面處理相當於粗化處理。 In addition, the surface treatments of Examples 1, 9 and the following Example 11 are equivalent to a smooth plating treatment (a surface treatment that is not a roughening treatment), and the surface treatments in the other Examples and Comparative Examples are equivalent to a roughening treatment.化 处理。 Processed.

又,準備以下所記載之附載體銅箔作為實施例11~15之基 材。 In addition, the copper foil with a carrier described below was prepared as a basis for Examples 11 to 15 material.

於實施例11~13,準備厚度18μm之電解銅箔(JX日礦日石金屬公司製造之HLP箔)作為載體,於實施例14,準備厚度18μm之電解銅箔(JX日礦日石金屬公司製造之JTC箔)作為載體,於實施例15,準備厚度18μm之壓延銅箔(JX日礦日石金屬公司製造之C1100)作為載體。並且,於下述條件下,於實施例11~13,在載體之析出面側的表面形成中間層,於實施例14,在載體之轉筒面(光澤面側)的表面形成中間層,於實施例15,在載體之表面形成中間層。然後,於各實施例中,在中間層之表面形成極薄銅層。再者,載體係於需要之情形時,藉由上述方法,控制形成中間層之側的表面中間層形成前之表面的表面粗糙度Rz與表面積比。 In Examples 11 to 13, an electrolytic copper foil with a thickness of 18 μm (HLP foil manufactured by JX Nippon Nissei Metal Co., Ltd.) was prepared as a carrier, and an electrolytic copper foil with a thickness of 18 μm (JX Nippon Nissei Metal Corp.) was prepared in Example 14 The manufactured JTC foil) was used as a carrier. In Example 15, a rolled copper foil (C1100 manufactured by JX Nippon Nissei Metal Co., Ltd.) with a thickness of 18 μm was prepared as a carrier. In addition, under the following conditions, an intermediate layer was formed on the surface of the carrier precipitation surface side in Examples 11 to 13, and in Example 14, an intermediate layer was formed on the surface of the carrier roller surface (gloss surface side) of the carrier. In Example 15, an intermediate layer is formed on the surface of the carrier. Then, in each embodiment, an ultra-thin copper layer is formed on the surface of the intermediate layer. In addition, when the carrier is required, the surface roughness of the surface on the side where the intermediate layer is formed before the intermediate layer is formed is controlled by the above method.

˙實施例11 ˙Example 11

<中間層> <Middle layer>

(1)Ni層(鍍Ni) (1) Ni layer (Ni plating)

針對載體,以下述條件,於輥對輥型之連續鍍敷線上進行電鍍,藉此形成1000μg/dm2之附著量的Ni層。將具體之鍍敷條件記載於下。 The carrier was plated on a roll-to-roll continuous plating line under the following conditions to form a Ni layer with an adhesion amount of 1000 μg / dm 2 . The specific plating conditions are described below.

硫酸鎳:270~280g/L Nickel sulfate: 270 ~ 280g / L

氯化鎳:35~45g/L Nickel chloride: 35 ~ 45g / L

乙酸鎳:10~20g/L Nickel acetate: 10 ~ 20g / L

硼酸:30~40g/L Boric acid: 30 ~ 40g / L

光澤劑:糖精、丁炔二醇(butynediol)等 Gloss agent: saccharin, butynediol, etc.

十二基硫酸鈉:55~75ppm Dodecyl sodium sulfate: 55 ~ 75ppm

pH值:4~6 pH value: 4 ~ 6

浴溫:55~65℃ Bath temperature: 55 ~ 65 ℃

電流密度:10A/dm2 Current density: 10A / dm 2

(2)Cr層(電解鉻酸處理) (2) Cr layer (electrolytic chromic acid treatment)

其次,對(1)中所形成之Ni層表面進行水洗及酸洗後,繼而藉由在輥對輥型之連續鍍敷線上,以下述條件,進行電解鉻酸處理,而使11μg/dm2之附著量的Cr層附著於Ni層上。 Next, the surface of the Ni layer formed in (1) was washed with water and pickled, and then subjected to electrolytic chromic acid treatment on a roll-to-roll continuous plating line under the following conditions to make 11 μg / dm 2 The Cr layer with an adhesion amount is attached to the Ni layer.

重鉻酸鉀1~10g/L、鋅0g/L Potassium dichromate 1 ~ 10g / L, zinc 0g / L

pH值:7~10 pH value: 7 ~ 10

液溫:40~60℃ Liquid temperature: 40 ~ 60 ℃

電流密度:2A/dm2 Current density: 2A / dm 2

<極薄銅層> <Ultra-thin copper layer>

其次,對(2)中所形成之Cr層表面進行水洗及酸洗後,繼而藉由在輥對輥型之連續鍍敷線上,以下述條件進行電鍍,而於Cr層上形成厚度1.5μm之極薄銅層,製作附載體極薄銅箔。 Next, the surface of the Cr layer formed in (2) was washed with water and pickled, and then plated on a roll-to-roll continuous plating line under the following conditions to form a 1.5 μm thick Cr layer. Ultra-thin copper layer to make ultra-thin copper foil with carrier.

銅濃度:90~110g/L Copper concentration: 90 ~ 110g / L

硫酸濃度:90~110g/L Sulfuric acid concentration: 90 ~ 110g / L

氯化物離子濃度:50~90ppm Chloride ion concentration: 50 ~ 90ppm

調平劑1(雙(3-磺丙基)二硫化物):10~30ppm Leveling agent 1 (bis (3-sulfopropyl) disulfide): 10 ~ 30ppm

調平劑2(胺化合物):10~30ppm Leveling agent 2 (amine compound): 10 ~ 30ppm

再者,使用下述胺化合物作為調平劑2。 The following amine compound was used as the leveling agent 2.

(上述化學式中,R1及R2為選自由羥烷基、醚基、芳基、經芳香族取代之烷基、不飽和烴基、烷基組成之群中者)。 (In the above chemical formula, R 1 and R 2 are selected from the group consisting of a hydroxyalkyl group, an ether group, an aryl group, an aromatic-substituted alkyl group, an unsaturated hydrocarbon group, and an alkyl group).

電解液溫度:50~80℃ Electrolyte temperature: 50 ~ 80 ℃

電流密度:100A/dm2 Current density: 100A / dm 2

電解液線速度:1.5~5m/sec Linear speed of electrolyte: 1.5 ~ 5m / sec

˙實施例12 ˙Example 12

<中間層> <Middle layer>

(1)Ni-Mo層(鎳鉬合金鍍敷) (1) Ni-Mo layer (nickel-molybdenum alloy plating)

對載體以下述條件於輥對輥型之連續鍍敷線上進行電鍍,藉此形成3000μg/dm2之附著量的Ni-Mo層。將具體之鍍敷條件記載於下。 The carrier was electroplated on a roll-to-roll continuous plating line under the following conditions to form a Ni-Mo layer with an adhesion amount of 3000 μg / dm 2 . The specific plating conditions are described below.

(液組成)硫酸Ni六水合物:50g/dm3、鉬酸鈉二水合物:60g/dm3、檸檬酸鈉:90g/dm3 (Liquid composition) Ni sulfate hexahydrate: 50 g / dm 3 , sodium molybdate dihydrate: 60 g / dm 3 , sodium citrate: 90 g / dm 3

(液溫)30℃ (Liquid temperature) 30 ℃

(電流密度)1~4A/dm2 (Current density) 1 ~ 4A / dm 2

(通電時間)3~25秒 (Power-on time) 3 ~ 25 seconds

<極薄銅層> <Ultra-thin copper layer>

於(1)中所形成之Ni-Mo層上形成極薄銅層。將極薄銅層之厚度設為2μm,除此以外,以與實施例11相同之條件形成極薄銅層。 An extremely thin copper layer is formed on the Ni-Mo layer formed in (1). An ultra-thin copper layer was formed under the same conditions as in Example 11 except that the thickness of the ultra-thin copper layer was set to 2 μm.

˙實施例13 ˙Example 13

<中間層> <Middle layer>

(1)Ni層(鍍Ni) (1) Ni layer (Ni plating)

以與實施例11相同之條件形成Ni層。 A Ni layer was formed under the same conditions as in Example 11.

(2)有機物層(有機物層形成處理) (2) Organic layer (organic layer forming treatment)

其次,對(1)中所形成之Ni層表面進行水洗及酸洗後,繼而以下述條件,將含有濃度1~30g/L之羧基苯并三唑(CBTA)之液溫40℃且pH值5的水溶液,向Ni層表面進行20~120秒噴霧洗滌,藉此形成有機物層。 Next, after the surface of the Ni layer formed in (1) was washed with water and pickled, the liquid temperature of the carboxybenzotriazole (CBTA) containing a concentration of 1 to 30 g / L was 40 ° C and the pH was set under the following conditions. The aqueous solution of 5 was spray-washed on the surface of the Ni layer for 20 to 120 seconds, thereby forming an organic layer.

<極薄銅層> <Ultra-thin copper layer>

於(2)中所形成之有機物層上形成極薄銅層。將極薄銅層之厚度設為3μm,除此以外,以與實施例11相同之條件形成極薄銅層。 An extremely thin copper layer is formed on the organic layer formed in (2). An ultra-thin copper layer was formed under the same conditions as in Example 11 except that the thickness of the ultra-thin copper layer was 3 μm.

˙實施例14、15 ˙Examples 14, 15

<中間層> <Middle layer>

(1)Co-Mo層(鈷鉬合金鍍敷) (1) Co-Mo layer (cobalt-molybdenum alloy plating)

對載體以下述條件於輥對輥型之連續鍍敷線上進行電鍍,藉此形成4000μg/dm2之附著量的Co-Mo層。將具體之鍍敷條件記載於下。 The carrier was electroplated on a roll-to-roll continuous plating line under the following conditions to form a Co-Mo layer with an adhesion amount of 4000 μg / dm 2 . The specific plating conditions are described below.

(液組成)硫酸Co:50g/dm3、鉬酸鈉二水合物:60g/dm3、檸檬酸鈉:90g/dm3 (Liquid composition) Co sulfate: 50 g / dm 3 , sodium molybdate dihydrate: 60 g / dm 3 , sodium citrate: 90 g / dm 3

(液溫)30℃ (Liquid temperature) 30 ℃

(電流密度)1~4A/dm2 (Current density) 1 ~ 4A / dm 2

(通電時間)3~25秒 (Power-on time) 3 ~ 25 seconds

<極薄銅層> <Ultra-thin copper layer>

於(1)中所形成之Co-Mo層上形成極薄銅層。於實施例14中,將極薄銅層之厚度設為3μm,於實施例15中,將極薄銅層之厚度設為5μm,除此以外,以與實施例11相同之條件形成極薄銅層。 An extremely thin copper layer is formed on the Co-Mo layer formed in (1). In Example 14, the thickness of the ultra-thin copper layer was set to 3 μm, and in Example 15, the thickness of the ultra-thin copper layer was set to 5 μm. Except that, the ultra-thin copper was formed under the same conditions as in Example 11. Floor.

針對藉由上述方式所製作之實施例及比較例的各樣品,如下述般進行各種評價。 Various samples of the examples and comparative examples produced as described above were subjected to various evaluations as described below.

<附著量之測量> <Measurement of adhesion amount>

關於表面處理層之Cu以外之各種金屬之附著量的測量,係使50mm×50mm之銅箔表面的皮膜溶解於混合有HNO3(2重量%)與HCl(5重量%)之溶液,利用ICP發射光譜分析裝置(精工電子納米科技股份有限公司製造,SFC-3100)對該溶液中之金屬濃度進行定量,而推導算出每單位面積之金屬量(μg/dm2)。此時,以與欲測量之面相反之面的金屬附著量不會 混入之方式,視需要進行遮蔽,來加以分析。再者,測量係針對進行過上述Zn、Co、Ni、Fe或該等之合金鍍敷、及鉻酸處理、進而矽烷偶合處理後的樣品進行。關於表面處理層之Cu附著量的測量,係自100mm×100mm尺寸之表面處理銅箔的重量減去藉由上述方法所測得之上述每單位面積之除Cu以外的各種金屬附著量及表面處理前銅箔之上述每單位面積的重量而求出。 For the measurement of the adhesion amount of various metals other than Cu in the surface treatment layer, a 50 mm × 50 mm copper foil surface film was dissolved in a solution mixed with HNO 3 (2% by weight) and HCl (5% by weight), and ICP was used. An emission spectrum analysis device (manufactured by Seiko Instruments Nano Technology Co., Ltd., SFC-3100) quantifies the metal concentration in the solution, and deduces the amount of metal per unit area (μg / dm 2 ). At this time, if necessary, the amount of metal deposited on the side opposite to the side to be measured will not be mixed, and if necessary, it will be masked for analysis. The measurement is performed on a sample that has been subjected to the above-mentioned Zn, Co, Ni, Fe, or an alloy plating thereof, a chromic acid treatment, and a silane coupling treatment. As for the measurement of the Cu adhesion amount of the surface treatment layer, it is the weight of the surface-treated copper foil with a size of 100 mm × 100 mm minus the above-mentioned measurement of the adhesion amount of various metals per unit area except for Cu per unit area and the surface treatment. The weight per unit area of the front copper foil was obtained.

<表面粗糙度Rz之測量> <Measurement of surface roughness Rz>

使用小阪研究所股份有限公司製造之接觸粗糙度計SP-11,依據JIS B0601-1994,對表面處理面測量十點平均粗糙度(Rz)。於測量基準長度0.8mm、評價長度4mm、截止值0.25mm、輸送速度0.1mm/sec之條件下,改變測量位置進行10次,將10次之測量值的平均值設為表面粗糙度Rz之值。又,對實施例及比較例中所使用之各電解銅箔及壓延銅箔,亦預先對表面處理前之粗糙度Rz進行測量。再者,十點平均粗糙度之測量係針對TD方向(銅箔之寬度方向(與銅箔製造裝置中之銅箔前進方向垂直的方向))進行。 Ten-point average roughness (Rz) was measured on the surface treated surface using a contact roughness meter SP-11 manufactured by Kosaka Research Co., Ltd. in accordance with JIS B0601-1994. Under the conditions of a measurement reference length of 0.8 mm, an evaluation length of 4 mm, a cutoff value of 0.25 mm, and a conveying speed of 0.1 mm / sec, the measurement position was changed 10 times, and the average value of the 10 measured values was set to the value of surface roughness Rz . In addition, for each of the electrolytic copper foil and the rolled copper foil used in the examples and comparative examples, the roughness Rz before the surface treatment was also measured. The measurement of the ten-point average roughness is performed with respect to the TD direction (the width direction of the copper foil (the direction perpendicular to the copper foil advancement direction in the copper foil manufacturing apparatus)).

<表面積比之測量> <Measurement of Surface Area Ratio>

關於三維表面積,係使用奧林巴斯股份有限公司製造之雷射顯微鏡LEXT OLS4000(雷射波長405nm,微分干渉方式),對表面處理銅箔之析出面中的二維表面積為66455μm2之區域進行測量。以所測得之三維表面積除以二維表面積所得之值作為表面積比。 As for the three-dimensional surface area, a laser microscope LEXT OLS4000 (laser wavelength 405 nm, differential drying method) manufactured by Olympus Co., Ltd. was used for a region having a two-dimensional surface area of 66455 μm 2 in the precipitation surface of the surface-treated copper foil. measuring. The surface area ratio was obtained by dividing the measured three-dimensional surface area by the two-dimensional surface area.

<傳輸損耗之測量> <Measurement of transmission loss>

將厚度18μm之各樣品與市售之液晶聚合物樹脂(可樂麗股份有限公 司製造之Vecstar CTZ-50μm)貼合後,藉由蝕刻,以特性阻抗成為50Ω之方式形成微波傳輸帶線路,使用HP公司製造之網路分析儀HP8720C測量穿透係數,而求出頻率20GHz下之傳輸損耗。作為頻率20GHz之傳輸損耗的評價,係將未達5.0dB/10cm設為◎,在5.0dB/10cm以上且未達6.0dB/10cm設為○,6.0dB/10cm以上設為×。傳輸損耗之大小由於會受到所使用之樹脂的相對介電常數、介電損耗正切及厚度的影響,故而將對一般用印刷配線板所使用之銅箔(比較例2中所使用之銅箔)具有明顯傳輸損耗降低效果者設為上述判定基準。 Each sample with a thickness of 18 μm and a commercially available liquid crystal polymer resin (Kuraray Co., Ltd. Vecstar CTZ-50μm manufactured by the company after bonding, forming a microwave transmission line by etching so that the characteristic impedance becomes 50Ω, using a network analyzer HP8720C manufactured by HP to measure the penetration coefficient, and finding the frequency at 20GHz Transmission loss. As the evaluation of the transmission loss at a frequency of 20 GHz, it is set to ◎ for 5.0 dB / 10 cm or less, and ○ for 5.0 dB / 10 cm or more and 6.0 dB / 10 cm or less, and × for 6.0 dB / 10 cm or more. The size of the transmission loss is affected by the relative dielectric constant, dielectric loss tangent, and thickness of the resin used. Therefore, it will be used for copper foils used in general printed wiring boards (copper foils used in Comparative Example 2). Those who have a significant reduction in transmission loss are set as the above-mentioned determination criterion.

將試驗結果示於表3。 The test results are shown in Table 3.

(評價結果) (Evaluation results)

關於實施例1~15,表面處理層中之Co、Ni、Fe合計附著量均為1000μg/dm2以下,表面處理層均具有Zn金屬層或含有Zn之合金處理層,表面積比均為1.0~1.9,表面粗糙度Rz JIS均為2.2μm以下。因此,實施例1~15之傳輸損耗均良好地獲得抑制。 Regarding Examples 1 to 15, the total adhesion amounts of Co, Ni, and Fe in the surface treatment layer were all 1000 μg / dm 2 or less. The surface treatment layers all had a Zn metal layer or an alloy treatment layer containing Zn, and the surface area ratios were all 1.0 to 1.9, the surface roughness Rz JIS are all 2.2 μm or less. Therefore, the transmission losses of Examples 1 to 15 were all well suppressed.

比較例1由於表面積比超過1.9,故傳輸損耗大。 In Comparative Example 1, since the surface area ratio exceeds 1.9, the transmission loss is large.

比較例2由於表面粗糙度Rz JIS超過2.2μm,表面積比超過1.9,故傳輸損耗大。 In Comparative Example 2, since the surface roughness Rz JIS exceeds 2.2 μm and the surface area ratio exceeds 1.9, the transmission loss is large.

比較例3由於表面粗糙度Rz JIS超過2.2μm,故傳輸損耗大。 In Comparative Example 3, since the surface roughness Rz JIS exceeds 2.2 μm, the transmission loss is large.

比較例4~6由於將實施例7之鍍敷處理3變更為含有Co、Ni、Fe者,且表面處理層中之Co、Ni、Fe合計附著量超過1000μg/dm2,故比較例4~6之傳輸損耗大於實施例7。 Comparative Examples 4 to 6 Comparative Example 4 to 6 changed the plating treatment 3 of Example 7 to those containing Co, Ni, and Fe, and the total adhesion amount of Co, Ni, and Fe in the surface treatment layer exceeded 1000 μg / dm 2 . The transmission loss of 6 is larger than that of Embodiment 7.

圖1為表示實施例及比較例之Co、Ni、Fe合計附著量與表面粗糙度Rz之關係的圖表。圖2為表示實施例及比較例之Co、Ni、Fe合計附著量與三維表面積相對於二維表面積之比之關係的圖表。圖3則表示實施例及比較例之Co、Ni、Fe、Cu、Zn合計附著量與傳輸損耗之關係的圖表。 FIG. 1 is a graph showing the relationship between the total adhesion amount of Co, Ni, and Fe and the surface roughness Rz in Examples and Comparative Examples. FIG. 2 is a graph showing the relationship between the total adhesion amount of Co, Ni, and Fe and the ratio of the three-dimensional surface area to the two-dimensional surface area in the examples and comparative examples. FIG. 3 is a graph showing the relationship between the total adhesion amount of Co, Ni, Fe, Cu, and Zn and transmission loss in Examples and Comparative Examples.

Claims (25)

一種表面處理銅箔,於至少一表面形成有表面處理層,該表面處理層中之Co、Ni、Fe合計附著量為1000μg/dm2以下,該表面處理層具有Zn金屬層或含有Zn之合金處理層,該表面處理層表面之二維表面積為66455μm2的區域利用雷射顯微鏡所測得之三維表面積相對於二維表面積的比為1.0~1.9,至少一表面之表面粗糙度Rz JIS為2.2μm以下。 A surface-treated copper foil having a surface-treated layer formed on at least one surface thereof. The total adhesion amount of Co, Ni, and Fe in the surface-treated layer is 1000 μg / dm 2 or less. The surface-treated layer has a Zn metal layer or an alloy containing Zn. Treatment layer, the surface of the surface treatment layer has a two-dimensional surface area of 66455 μm 2 , and the ratio of the three-dimensional surface area to the two-dimensional surface area measured by a laser microscope is 1.0 to 1.9, and the surface roughness Rz JIS of at least one surface is 2.2 μm or less. 如申請專利範圍第1項之表面處理銅箔,其中,該表面處理層中之Co、Ni、Fe合計附著量為500μg/dm2以下。 For example, the surface-treated copper foil of the first patent application scope, wherein the total adhesion amount of Co, Ni, and Fe in the surface-treated layer is 500 μg / dm 2 or less. 如申請專利範圍第2項之表面處理銅箔,其中,該表面處理層中之Co、Ni、Fe合計附著量為300μg/dm2以下。 For example, the surface-treated copper foil according to item 2 of the scope of patent application, wherein the total adhesion amount of Co, Ni, and Fe in the surface-treated layer is 300 μg / dm 2 or less. 如申請專利範圍第3項之表面處理銅箔,其中,該表面處理層中之Co、Ni、Fe合計附著量為0μg/dm2For example, the surface-treated copper foil of item 3 of the scope of application for a patent, wherein the total adhesion amount of Co, Ni, and Fe in the surface-treated layer is 0 μg / dm 2 . 如申請專利範圍第1項之表面處理銅箔,其中,兩表面之表面粗糙度Rz JIS為2.2μm以下。 For example, the surface-treated copper foil of the first scope of the patent application, wherein the surface roughness Rz JIS of both surfaces is 2.2 μm or less. 如申請專利範圍第1項之表面處理銅箔,其中,該表面處理層包含粗化處理層。 For example, the surface-treated copper foil according to item 1 of the patent application scope, wherein the surface-treated layer includes a roughened layer. 如申請專利範圍第6項之表面處理銅箔,其中,該粗化處理層中之Cu附著量為0.10g/dm2以下。 For example, the surface-treated copper foil of item 6 of the patent application scope, wherein the amount of Cu deposited in the roughened layer is 0.10 g / dm 2 or less. 如申請專利範圍第6項之表面處理銅箔,其中,於該表面處理層中,於該粗化處理層上設置有該Zn金屬層或含有Zn之合金處理層。 For example, the surface-treated copper foil according to item 6 of the scope of patent application, wherein the surface-treated layer is provided with the Zn metal layer or an alloy-treated layer containing Zn on the roughened layer. 如申請專利範圍第1項之表面處理銅箔,其中,該含有Zn之合金處理 層為Cu-Zn合金層。 For example, the surface-treated copper foil of the scope of application for patent No. 1, wherein the alloy containing Zn is treated The layer is a Cu-Zn alloy layer. 如申請專利範圍第1項之表面處理銅箔,其中,該表面處理層中之Zn附著量為5mg/dm2以下。 For example, the surface-treated copper foil of item 1 of the patent application scope, wherein the Zn adhesion amount in the surface-treated layer is 5 mg / dm 2 or less. 如申請專利範圍第1項之表面處理銅箔,其中,於該表面處理層中,於該Zn金屬層或含有Zn之合金處理層上設置有鉻酸處理(chromate treatment)層。 For example, the surface-treated copper foil according to item 1 of the application, wherein a chromate treatment layer is provided on the Zn metal layer or an Zn-containing alloy treatment layer in the surface treatment layer. 如申請專利範圍第11項之表面處理銅箔,其中,於該鉻酸處理層上設置有矽烷偶合處理層。 For example, the surface-treated copper foil according to item 11 of the application, wherein a silane coupling treatment layer is provided on the chromic acid treatment layer. 如申請專利範圍第1項之表面處理銅箔,其中,該表面處理層中之Cu、Zn、Co、Ni、Fe合計附著量為0.10g/dm2以下。 For example, the surface-treated copper foil in the first scope of the patent application, wherein the total adhesion amount of Cu, Zn, Co, Ni, and Fe in the surface-treated layer is 0.10 g / dm 2 or less. 如申請專利範圍第1至13項中任一項之表面處理銅箔,其用於軟性印刷配線板。 For example, the surface-treated copper foil according to any one of claims 1 to 13 is used for flexible printed wiring boards. 如申請專利範圍第1至13項中任一項之表面處理銅箔,其用於5GHz以上之高頻電路基板。 For example, the surface-treated copper foil according to any one of claims 1 to 13 is used for high-frequency circuit substrates above 5 GHz. 一種積層板,係將申請專利範圍第1至13項中任一項之表面處理銅箔與樹脂基板積層而製造。 A laminated board is manufactured by laminating a surface-treated copper foil and a resin substrate in any one of the scope of application for patents 1 to 13. 一種印刷配線板,係以申請專利範圍第16項之積層板作為材料。 A printed wiring board is made of a laminated board with the scope of patent application No. 16 as a material. 一種電子機器,使用有申請專利範圍第17項之印刷配線板。 An electronic device using a printed wiring board having the scope of application for item 17 of the patent. 一種附載體銅箔,係於載體之一面或兩面依序具有中間層、極薄銅層,該極薄銅層為申請專利範圍第1至13項中任一項之表面處理銅箔。 A copper foil with a carrier is provided on one or both sides of the carrier with an intermediate layer and an ultra-thin copper layer in order. The ultra-thin copper layer is a surface-treated copper foil according to any one of claims 1 to 13. 如申請專利範圍第19項之附載體銅箔,其中,於該載體之一面依序具有該中間層、該極薄銅層,於該載體之另一面具有粗化處理層。 For example, the copper foil with a carrier of the scope of application for item 19 has the intermediate layer, the ultra-thin copper layer in order on one side of the carrier, and a roughening layer on the other side of the carrier. 一種積層板,係將申請專利範圍第19或20項之附載體銅箔與樹脂基板積層而製造。 A laminated board is manufactured by laminating a copper foil with a carrier and a resin substrate in the scope of patent application No. 19 or 20. 一種印刷配線板,係使用申請專利範圍第21項之積層板而製造。 A printed wiring board is manufactured by using a laminated board with the scope of patent application No. 21. 一種電子機器,使用有申請專利範圍第22項之印刷配線板。 An electronic device using a printed wiring board having a scope of application for patent No. 22. 一種印刷配線板之製造方法,包括如下步驟:準備申請專利範圍第19或20項之附載體銅箔與絕緣基板之步驟;將該附載體銅箔與絕緣基板積層之步驟;將該附載體銅箔與絕緣基板積層後,經過將該附載體銅箔之載體剝離的步驟而形成覆金屬積層板,然後,藉由半加成法(semi-additive process)、減成法(subtractive process)、部分加成法(partly additive process)或改良半加成法(modified semi-additive process)形成電路之步驟。 A method for manufacturing a printed wiring board includes the following steps: a step of preparing a copper foil with a carrier and an insulating substrate for applying for a patent application No. 19 or 20; a step of laminating the copper foil with a carrier and an insulating substrate; After the foil and the insulating substrate are laminated, a metal-clad laminated board is formed through a step of peeling the carrier of the copper foil with the carrier, and then, by a semi-additive process, a subtractive process, a part A step of forming a circuit by a partially additive process or a modified semi-additive process. 一種印刷配線板之製造方法,包括如下步驟:於申請專利範圍第19或20項之附載體銅箔的該極薄銅層側表面或該載體側表面形成電路之步驟;以掩埋該電路之方式,於該附載體銅箔之該極薄銅層側表面或該載體側表面形成樹脂層之步驟;於該樹脂層上形成電路之步驟;於該樹脂層上形成電路後,將該載體或該極薄銅層剝離之步驟;及將該載體或該極薄銅層剝離後,將該極薄銅層或該載體去除,藉此使形成於該極薄銅層側表面或該載體側表面被該樹脂層掩埋之電路露出之步驟。 A method for manufacturing a printed wiring board includes the steps of: forming a circuit on the ultra-thin copper layer side surface of the copper foil with a carrier or on the carrier side surface of a copper foil with a carrier in the scope of application for a patent; A step of forming a resin layer on the ultra-thin copper layer side surface of the copper foil with a carrier or the carrier side surface; a step of forming a circuit on the resin layer; after forming a circuit on the resin layer, the carrier or the A step of peeling the ultra-thin copper layer; and removing the carrier or the ultra-thin copper layer, removing the ultra-thin copper layer or the carrier, thereby forming the side surface of the ultra-thin copper layer or the side surface of the carrier The step of exposing the buried circuit of the resin layer.
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KR20170046632A (en) 2017-05-02

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