TWI595625B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TWI595625B
TWI595625B TW102145872A TW102145872A TWI595625B TW I595625 B TWI595625 B TW I595625B TW 102145872 A TW102145872 A TW 102145872A TW 102145872 A TW102145872 A TW 102145872A TW I595625 B TWI595625 B TW I595625B
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type diffusion
pad
field
diffusion field
semiconductor substrate
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TW201432876A (zh
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Hitomi Sakurai
Yoshitsugu Hirose
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Sii Semiconductor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

半導體裝置
本發明是關於半導體裝置。更詳細是有關可抑制閉鎖(Latch up)的發生之半導體裝置。
首先，說明有關以往的半導體裝置。圖5是表示以往的半導體裝置的剖面圖。
當被施加具有往輸入焊墊(pad)71的負電壓之突波時，P型半導體基板87的少數載體(carrier)之電子會有從ESD保護電路的領域的N型擴散領域81露出至P型的半導體基板87的情形。此少數載體是從半導體基板87往被連接至接地焊墊72的P型擴散領域82流入、吸收。在此，由於從ESD保護電路往內部電路的方向的P型擴散領域82的水平方向的長度夠長，所以少數載體會充分地被P型擴散領域82吸收。未被P型擴散領域82吸收的少數載體是從半導體基板87經由被連接至電源焊墊73的N型擴散領域83來強制性地抽出。藉由往輸入焊墊71的突波所產生的少數載體是在內部電路之閉鎖的發生的主要原因，但如以上般從半導體基板87逃脫下，可使在內部電 路的閉鎖不易發生(例如參照專利文獻1)。
[先行技術文獻] [專利文獻]
[專利文獻1]日本特開2007-019345號公報
但，就專利文獻1所揭示的技術而言，由於從ESD保護電路往內部電路的方向之P型擴散領域82的水平方向的長度長，因此該部分造成半導體裝置的面積變大。
本發明是有鑑於上述課題而研發者，提供一種可以小的面積來抑制閉鎖的發生之半導體裝置。
本發明是為了解決上述課題，而提供一種半導體裝置，其特徵係具備：擴散領域之汲極，其係連接至焊墊；內部電路的領域；及少數載體捕獲領域，其係設在前述汲極與前述內部電路的領域之間，具備：第一P型擴散領域、第二P型擴散領域、及被前述第一P型擴散領域與前述第二P型擴散領域所夾的N型擴散領域之3重保護環(guard ring)，捕獲往前述焊墊的突波所產生的少數載體，前述第一P型擴散領域與前述第二P型擴散領域係藉 由非最短距離迂迴金屬膜配線來連接，且分別被連接至接地焊墊，前述N型擴散領域係被連接至電源焊墊。
本發明是在3重保護環內，藉由具有接地電位的P型擴散領域來夾持具有正的電源電位的N型的擴散領域，藉此即使縮短從ESD保護電路往內部電路的方向之P型擴散領域的長度，還是可抑制在內部電路的閉鎖的發生。可縮小半導體裝置的面積。
11‧‧‧輸入焊墊
12‧‧‧接地焊墊
13‧‧‧電源焊墊
21‧‧‧N型擴散領域
22‧‧‧P型擴散領域
23‧‧‧N型擴散領域
24‧‧‧N型阱
25‧‧‧P型擴散領域
26‧‧‧N型阱
27‧‧‧半導體基板
圖1是表示半導體裝置的剖面圖。
圖2是表示半導體裝置的平面圖。
圖3是表示半導體裝置的剖面圖。
圖4是表示半導體裝置的剖面圖。
圖5是表示以往的半導體裝置的剖面圖。
以下，參照圖面說明有關本發明的實施形態。首先，說明有關半導體裝置的構成。圖1是表示半導體裝置的剖面圖，圖2是表示半導體裝置的平面圖。
如圖1所示般，半導體基板27是由ESD保護電路的領域、內部電路的領域及少數載體捕獲領域的3個領域所形成，該ESD保護電路的領域是自ESD保護半導體裝 置，該少數載體捕獲領域是捕獲藉由具有往輸入或輸出的焊墊11之負的電壓的突波來產生於半導體基板27的少數載體，且少數載體捕獲領域是包圍內部電路的領域，通常形成保護環。輸入或輸出的焊墊11、接地焊墊12、電源焊墊13、及保護電路基本上是配置於保護環的外側。
在ESD保護電路的領域中，N型擴散領域21是被形成於P型的半導體基板27的表面。此N型擴散領域21通常是作為自ESD保護半導體裝置的ESD保護電路的機能之NMOS電晶體的汲極。此汲極(N型擴散領域21)是被連接至焊墊11。雖未圖示，但實際此NMOS電晶體的源極及閘極是被連接至接地焊墊12，汲極是被連接至焊墊11，藉此此NMOS電晶體是作為ESD保護電路的機能。並且，作為其他的構成，N型擴散領域21是亦為保護二極體的陰極。
在內部電路的領域中，N型阱26是被形成於P型的半導體基板27的表面。P型擴散領域雖未圖示，但實際被形成於N型阱26的表面。此P型擴散領域是成為PMOS電晶體的源極或汲極。並且，N型擴散領域雖未圖示，但實際被形成於P型的半導體基板27的表面。此N型擴散領域是成為NMOS電晶體的源極或汲極。
在少數載體捕獲領域中，P型擴散領域22、N型阱24及P型擴散領域25是被形成於P型的半導體基板27的表面。N型擴散領域23是被形成於N型阱24的表面。此時、N型阱24是被P型擴散領域22及P型擴散領域 25所夾。該等的P型擴散領域22、P型擴散領域25及N型阱24內部的N型擴散領域23是成為汲極(N型擴散領域21)與內部電路的領域之間的3重保護環。P型擴散領域22及P型擴散領域25是分別被連接至接地焊墊12、N型擴散領域23是被連接至電源焊墊13。
圖2是表示P型擴散領域22及P型擴散領域25與接地焊墊12的配置方法之例。如圖2所示般，P型擴散領域22是藉由觸點(contact)22A來電性連接至金屬膜配線22B，P型擴散領域25是藉由觸點25A來電性連接至金屬膜配線25B。此金屬膜配線22B是被電性連接至外部連接用焊墊的接地焊墊12。同樣，金屬膜配線25B也被電性連接至外部連接用焊墊的接地焊墊12。此時，金屬膜配線22B是儘可能至接地焊墊12的附近，不與金屬膜配線25B一起地作為別的配線分離而獨立配線佈局設計。同樣，金屬膜配線25B也是儘可能至接地焊墊12的附近，不與金屬膜配線22B、25B一起地作為別的配線分離而獨立配線佈局設計。亦即，P型擴散領域22與P型擴散領域25是藉由非最短距離互相避開接觸而分離迂迴的金屬膜配線來連接，且雙方皆被連接至接地焊墊12。
其次，說明有關半導體裝置的動作。
往焊墊11的突波所產生的少數載體(電子)是有從ESD保護電路的領域的N型擴散領域21(保護電晶體的汲極或保護二極體的陰極)露出至P型的半導體基板27的情形。此少數載體是從半導體基板27往被連接至接地焊墊 12的P型擴散領域22流入、吸收。未被P型擴散領域22吸收的少數載體是從半導體基板27經由被連接至電源焊墊13的N型擴散領域23來強制性地抽出。未被抽出至N型擴散領域23的少數載體是從半導體基板27往被連接至接地焊墊12的P型擴散領域25流入、吸收。亦即，藉由P型擴散領域22、P型擴散領域25及N型阱24內部的N型擴散領域23的3重保護環來使往焊墊11的突波所產生的少數載體從半導體基板27逃脫。
在此、3重保護環的P型擴散領域22與P型擴散領域25是非最短距離迂迴藉由金屬膜配線22B、25B來連接至接地焊墊12。因此，在P型擴散領域22與P型擴散領域25之間存在金屬膜配線22B及金屬膜配線25B所產生的寄生電阻。藉由此寄生電阻，被P型擴散領域22吸收的少數載體是不流入P型擴散領域25地流入接地焊墊12。亦即，P型擴散領域22所產生的少數載體吸收機能被確實地發揮。往焊墊11的突波所產生的少數載體是在內部電路之閉鎖的發生的主要原因，但如前述般從半導體基板27逃脫下，可使在內部電路的閉鎖不易發生。
另外，在圖1中，N型擴散領域21是作為自ESD保護半導體裝置的ESD保護電路的機能之NMOS電晶體的汲極或保護二極體的陰極。NMOS電晶體的情況，此NMOS電晶體的源極及閘極是被連接至接地焊墊12，汲極是被連接至焊墊11。
作為其他的實施形態，如圖3所示般，N型擴散領域 21是亦可為開放汲極輸出的NMOS電晶體的汲極。此NMOS電晶體的源極是被連接至接地焊墊12，汲極是被連接至輸出焊墊31。
又，如圖4所示般，汲極是亦可為開放汲極輸出的PMOS電晶體的汲極。此PMOS電晶體的源極是被連接至電源焊墊13，汲極(N型阱29內部的P型擴散領域28)是被連接至輸出焊墊31。
11‧‧‧輸入焊墊
12‧‧‧接地焊墊
13‧‧‧電源焊墊
21‧‧‧N型擴散領域
22‧‧‧P型擴散領域
23‧‧‧N型擴散領域
24‧‧‧N型阱
25‧‧‧P型擴散領域
26‧‧‧N型阱
27‧‧‧半導體基板

Claims (4)

  1. 一種半導體裝置，其特徵係具備：P型的半導體基板，其係具有焊墊、接地焊墊、及電源焊墊；第一N型擴散領域，其係設於前述半導體基板，連接至前述焊墊；內部電路的領域，其係設於前述半導體基板；及少數載體捕獲領域，其係設於前述第一N型擴散領域與前述內部電路的領域之間，具有：第一P型擴散領域、第二P型擴散領域、及被前述第一P型擴散領域與前述第二P型擴散領域所夾的第二N型擴散領域之3重保護環，捕獲藉由往前述焊墊的突波來產生於前述半導體基板的少數載體，前述第一P型擴散領域與前述第二P型擴散領域係經由分離配置的金屬膜配線來分別連接至前述接地焊墊，前述第二N型擴散領域係被連接至前述電源焊墊。
  2. 如申請專利範圍第1項之半導體裝置，其中，更具備NMOS電晶體，其係源極及閘極被連接至前述接地焊墊，前述第一N型擴散領域之汲極被連接至前述焊墊，作為ESD保護電路的機能。
  3. 如申請專利範圍第1項之半導體裝置，其中，更具備開放汲極輸出的NMOS電晶體，其係源極被連接至前述接地焊墊，前述第一N型擴散領域之汲極被連接至前述焊墊。
  4. 一種半導體裝置，其特徵係具備：P型的半導體基板，其係具有焊墊、接地焊墊、及電源焊墊；焊墊連接用P型擴散領域，其係經由第一N型擴散領域來設於前述半導體基板，被連接至前述焊墊；內部電路的領域，其係設於前述半導體基板；及少數載體捕獲領域，其係設於前述焊墊連接用P型擴散領域與前述內部電路的領域之間，具有：第一P型擴散領域、第二P型擴散領域、及被前述第一P型擴散領域與前述第二P型擴散領域所夾的第二N型擴散領域之3重保護環，捕獲藉由往前述焊墊的突波來產生於前述半導體基板的少數載體，前述第一P型擴散領域與前述第二P型擴散領域係經由分離配置的金屬膜配線來分別連接至前述接地焊墊，前述第二N型擴散領域係被連接至前述電源焊墊，更具備開放汲極輸出的PMOS電晶體，其係源極被連接至前述電源焊墊，前述焊墊連接用P型擴散領域之汲極被連接至前述焊墊。
TW102145872A 2012-12-20 2013-12-12 半導體裝置 TWI595625B (zh)

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