TWI588938B - 全部在一整合蝕刻中的金屬硬遮罩 - Google Patents

全部在一整合蝕刻中的金屬硬遮罩 Download PDF

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TWI588938B
TWI588938B TW102115736A TW102115736A TWI588938B TW I588938 B TWI588938 B TW I588938B TW 102115736 A TW102115736 A TW 102115736A TW 102115736 A TW102115736 A TW 102115736A TW I588938 B TWI588938 B TW I588938B
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dielectric layer
trenches
trench
contact hole
forming
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TW201405709A (zh
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程宇
黄均文
裴慧元
劉健鋼
崔□軫
王亮
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蘭姆研究公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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Description

全部在一整合蝕刻中的金屬硬遮罩
本發明涉及在介電層中形成穿孔及渠溝。更具體而言，本發明涉及利用渠溝金屬硬遮罩來形成穿孔及渠溝。
於半導體晶圓處理期間，將穿孔及渠溝的雙重鑲嵌結構蝕刻至介電層中。隨後將雙重鑲嵌結構填滿導電材料以形成接觸孔。
為達到以上所述並依據本發明之目的，故提供一種在介電層中形成導電接觸孔的方法。經由穿孔遮罩蝕刻部份穿孔至介電層中。經由渠溝遮罩蝕刻渠溝至該介電層中，其中蝕刻渠溝之步驟完成並過蝕刻該等穿孔，以使該等穿孔的底部變寬。將該等渠溝或穿孔的頂部修圓。
在本發明的另一表現形式中，提供一種在介電層中形成導電接觸孔的方法，介電層設置在渠溝遮罩下方，渠溝遮罩設置在穿孔遮罩下方，從而形成一堆疊。經由穿孔遮罩蝕刻部份穿孔至介電層中。使渠溝遮罩露出。經由渠溝遮罩蝕刻渠溝至介電層中，其中蝕刻渠溝之步驟完成並過蝕刻穿孔，以使穿孔的底部變寬。將一平坦化線以上的渠溝或穿孔的頂部修圓。將穿孔及渠溝填滿導電材料。將堆疊平坦化至該平坦化線。
本發明的這些和其他特徵將在以下本發明的實施方式並配合下列圖式更加詳細描述。
104、108、112、116、120、124、128‧‧‧步驟
200‧‧‧堆疊
204‧‧‧基板
208‧‧‧接觸孔層
212‧‧‧蝕刻停止層
216‧‧‧接觸孔
220‧‧‧介電層
224‧‧‧渠溝遮罩
228‧‧‧平坦化層
232‧‧‧穿孔遮罩
240‧‧‧穿孔
244‧‧‧渠溝
248‧‧‧平坦化目標線或平面
252‧‧‧頂部
256‧‧‧導電金屬
3-3‧‧‧切線
本發明係藉由舉例的方式而非限制的方式於附圖之圖式中加以說明，且其中相似的參考數字表示類似元件，且其中：圖1係本發明之實施例的高階流程圖。
圖2A-G係根據本發明之實施例之所處理的堆疊之示意圖。
圖3係沿著圖2G的切線3-3之堆疊200的橫剖面圖。
現將參考幾個如附圖所示之關於本發明的較佳實施例來詳細描述本發明。在以下的描述中，為提供對本發明的徹底瞭解而提出許多具體細節。然而，對於本領域中具有通常技術者而言將顯而易見，本發明可在不具有這些具體細節之部份或全部的情形下加以實施。在其他情況下，為了不非必要地混淆本發明，故已不詳細地描述熟知的製程步驟及/或結構。
圖1係使用在本發明之實施例中之製程的高階流程圖以幫助瞭解本發明。基板設有介電層，渠溝遮罩設置在介電層上方，穿孔遮罩設置在渠溝遮罩上方(步驟104)。渠溝遮罩可為硬遮罩，其中平坦化層將渠溝遮罩與穿孔遮罩隔開。經由穿孔遮罩將穿孔部份蝕刻至介電層中(步驟108)。使渠溝遮罩露出(步驟112)。將渠溝蝕刻至介電層中，同時將穿孔完成並且過蝕刻(步驟116)。穿孔的過蝕刻可增加穿孔底部的寬度。將渠溝或穿孔的頂部修圓，這在本說明書及申請專利範圍中包括將頂角刻面或使頂角傾斜(步驟120)。將穿孔及渠溝填滿導電材料以形成接觸孔(步驟124)。將介電層平坦化至一平坦化目標(步驟128)。
範例
在本發明之一範例中，基板設有介電層，渠溝遮罩設置在介電層上方，穿孔遮罩設置在渠溝遮罩上方(步驟104)。圖2A係堆疊200的橫剖面圖，該堆疊200具有其上方已形成接觸孔層208之基板204。接觸孔層208上方為蝕刻停止或阻障層212。接觸孔層208內部為接觸孔216。介電層220已形成在蝕刻停止層212上方。在此實施例中，蝕刻停止層212為氮摻雜之矽碳化物(SiCN)的襯墊。圖案化渠溝遮罩224已形成在介電層 220上方。在此範例中，圖案化渠溝遮罩224為硬遮罩。例如，圖案化渠溝遮罩224為鈦氮化物(TiN)。平坦化層228係形成在圖案化渠溝遮罩224上方。圖案化穿孔遮罩232係形成在平坦化層228上方。圖案化穿孔遮罩232可為光阻或一些其他材料。在本發明的其他實施例中，可在各個層與遮罩之間增加額外的層、或可以其他層來取代各個層、或可將層移除。
經由穿孔遮罩232將穿孔部份蝕刻至介電層220中。圖2B係已將穿孔240部份蝕刻至介電層220中之後的堆疊200的橫剖面圖。在此範例中，穿孔側壁稍微成錐形。可用以蝕刻部份穿孔之處方的範例提供了C4F8、CF4、N2、Ar、及O2之穿孔蝕刻氣體。腔室壓力維持在介於20至60mTorr之間。晶圓溫度維持在介於50℃至100℃之間。
隨後使渠溝遮罩224露出(步驟112)。在一實施例中，將餘留的穿孔遮罩232及平坦化層228同時移除，以使渠溝遮罩224露出。在另一實施例中，可在蝕刻部份穿孔期間移除穿孔遮罩232，以及可在使渠溝遮罩224露出期間移除平坦化層228。圖2C係已將穿孔遮罩232及平坦化層228移除後而露出渠溝遮罩224之堆疊200的橫剖面圖。可用以使渠溝遮罩露出之處方的範例提供了CO2及O2之剝除氣體。腔室壓力維持在介於20至60mTorr之間。晶圓溫度維持在介於50℃至100℃之間。
經由圖案化渠溝遮罩將渠溝蝕刻至介電層中，這也完成並過蝕刻穿孔而使穿孔的底部變寬(步驟116)。圖2D顯示在蝕刻渠溝244並且過蝕刻穿孔240之後的堆疊200，這使穿孔240的底部變寬，從而形成較不成錐形而且更為垂直的側壁。在此範例中，穿孔具有圓形橫剖面，其中渠溝沿著進入頁面的直線具有線形橫剖面，其中每一渠溝連接複數穿孔。較佳地，用於形成渠溝及過蝕刻穿孔之蝕刻比部份穿孔蝕刻更具選擇性。較不具選擇性之部份穿孔蝕刻的優點為這類蝕刻較快。較具選擇性之渠溝蝕刻及穿孔過蝕刻的優點為這類蝕刻提供了更垂直而較不成錐形的側壁。可用以蝕刻渠溝及過蝕刻穿孔之處方的範例提供了C4F8、CF4、N2、Ar、及O2之渠溝蝕刻氣體。供應20至60mTorr的腔室壓力。晶圓溫度維持在介於50℃至100℃之間。
將渠溝的頂部修圓(步驟120)。圖2E顯示渠溝244的頂部252已被修圓之後的堆疊。此修圓發生在平坦化目標線或平面248以上。較 佳地，在平坦化目標線248以下沒有修圓發生。因為頂部在平坦化目標線或平面248以上被修圓，所以在平坦化目標線248以上的渠溝244之頂部252的側壁較平坦化目標線248以下的側壁為淺。在此實施例中，於蝕刻停止層212的開通期間，同時將渠溝的頂部252修圓。更佳地，修圓及蝕刻停止層開通為二步驟製程。在如此處方的範例中，提供了包含CF4、C4F8、N2、及Ar之修圓氣體(rounding gas)。該修圓氣體形成為電漿。夾盤溫度維持在介於50℃與100℃之間。
將穿孔及渠溝填滿(步驟124)。在此實施例中，將渠溝及穿孔填滿含銅導體。圖2F顯示在穿孔240及渠溝244填滿含銅導體256之後的堆疊200。將渠溝及穿孔填滿的一範例處方為提供銅電鍍。在此範例中，首先將阻障層形成在穿孔及渠溝的壁上。然後在阻障層上形成晶種層。將一電壓施加至晶種層，並將穿孔及渠溝置於含銅酸浴中。含銅金屬便沉積在晶種層上的渠溝及穿孔中。在其他實施例中，可使用無電銅沉積。
將堆疊200平坦化(步驟128)。在此實施例中，化學機械研磨(CMP)係用以將堆疊200平坦化至平坦化目標線或平面248。圖2G顯示將堆疊平坦化至平坦化目標線或平面248之後的堆疊。圖3係沿著圖2G的切線3-3之堆疊200的橫剖面圖。圖3中的視圖更清楚顯示渠溝244的線形橫剖面以及穿孔240的橫剖面。
所產生的結構提供具有實質上垂直側壁之渠溝及穿孔。填滿渠溝244及穿孔240之導電金屬256形成導電接觸孔及互連。對於28nm閘極CD而言，已發現到將渠溝的頂部修圓移除了角、並提供了較寬的開口，從而提供用於填滿穿孔及渠溝之改善沉積。角的移除亦減少突出物，這改善了沉積。亦發現到較寬的開口使接觸孔之間的漏電增加。藉由僅將平坦化目標以上的渠溝頂部變寬、並隨後將平坦化目標以上的堆疊移除，進而改善導電材料的填入而不使漏電增加。此外，使用較不具選擇性的蝕刻來部份蝕刻穿孔、並隨後使用高選擇性的蝕刻來蝕刻渠溝以及過蝕刻穿孔的組合，這允許其提供垂直側壁的較快速蝕刻製程。本發明之此實施例避免彎曲(bowing)。本發明之實施例提供更好穩健性及額外控制，其可用來調整參數以減少條紋或彎曲、或提供其他益處。
可使用額外製程以完成半導體裝置的形成。
雖然已就一些較佳實施例對本發明加以說明，惟仍有落於本發明之範圍內的變化、置換、修改、及各種替代相等者。亦應注意有許多實施本發明之方法及設備的替代方式。因此欲使以下隨附之申請專利範圍被理解成包括所有落於本發明之真正精神及範圍內的此類變化、置換、及各種替代相等者。
104、108、112、116、120、124、128‧‧‧步驟

Claims (17)

  1. 一種在介電層中形成導電接觸孔的方法，該方法包含：經由穿孔遮罩蝕刻部份複數穿孔至該介電層中；經由渠溝遮罩蝕刻複數渠溝至該介電層中，其中蝕刻該等渠溝之步驟完成並過蝕刻該等穿孔，以使該等穿孔的底部變寬；以及將該等渠溝或穿孔的頂部修圓，其中一渠溝圖案化硬遮罩係位於該介電層上方，且其中一平坦化層係位於該渠溝圖案化硬遮罩及該介電層上方，且其中一穿孔圖案化遮罩係位於該平坦化層上方。
  2. 如申請專利範圍第1項之在介電層中形成導電接觸孔的方法，其中將該等渠溝或穿孔的頂部修圓之步驟在該等穿孔的底部處將蝕刻停止層開通。
  3. 如申請專利範圍第2項之在介電層中形成導電接觸孔的方法，更包含：將該等穿孔及渠溝填滿含銅導電材料；以及將該等穿孔、渠溝及該介電層平坦化至一平坦化目標。
  4. 如申請專利範圍第3項之在介電層中形成導電接觸孔的方法，其中將該等渠溝或穿孔的頂部修圓之步驟不將該平坦化目標以下的部份該等渠溝及穿孔修圓。
  5. 如申請專利範圍第4項之在介電層中形成導電接觸孔的方法，其中將該等渠溝或穿孔的頂部修圓之步驟提供一介於50℃至100℃之間的靜電夾盤溫度，且其中蝕刻該等渠溝之步驟較蝕刻部份該等穿孔之步驟更具選擇性。
  6. 如申請專利範圍第5項之在介電層中形成導電接觸孔的方法，其中將該等渠溝或穿孔的頂部修圓之步驟更包含：提供包含CF4、C4F8、及N2的氣體。
  7. 如申請專利範圍第6項之在介電層中形成導電接觸孔的方法，其中該氣 體更包含Ar。
  8. 如申請專利範圍第7項之在介電層中形成導電接觸孔的方法，其中將該等渠溝或穿孔的頂部修圓之步驟導致在該等渠溝或穿孔的頂部處之側壁具有與在該平坦化目標處之側壁不同的斜度。
  9. 如申請專利範圍第8項之在介電層中形成導電接觸孔的方法，更包含在蝕刻部份該等穿孔之步驟後並且在該蝕刻該等渠溝之步驟前，使該渠溝遮罩露出。
  10. 如申請專利範圍第1項之在介電層中形成導電接觸孔的方法，更包含：將該等穿孔及渠溝填滿含銅導電材料；以及將該等穿孔、渠溝及該介電層平坦化至一平坦化目標。
  11. 如申請專利範圍第1項之在介電層中形成導電接觸孔的方法，其中將該等渠溝或穿孔的頂部修圓之步驟不將該平坦化目標以下的部份該等穿孔修圓。
  12. 如申請專利範圍第1項之在介電層中形成導電接觸孔的方法，其中將該等渠溝或穿孔的頂部修圓之步驟提供一介於50℃至100℃之間的靜電夾盤溫度。
  13. 如申請專利範圍第12項之在介電層中形成導電接觸孔的方法，其中將該等渠溝或穿孔的頂部修圓之步驟更包含：提供包含CF4、C4F8、及N2的氣體。
  14. 如申請專利範圍第13項之在介電層中形成導電接觸孔的方法，其中該氣體更包含Ar。
  15. 如申請專利範圍第1項之在介電層中形成導電接觸孔的方法，更包含在蝕刻部份該等穿孔之步驟後並且在蝕刻該等渠溝之步驟前，使該渠溝遮罩露出。
  16. 如申請專利範圍第1項之在介電層中形成導電接觸孔的方法，其中將該等渠溝或穿孔的頂部修圓之步驟導致在該等渠溝或穿孔的頂部處之側壁具有與在該平坦化目標處之側壁不同的斜度。
  17. 一種在介電層中形成導電接觸孔的方法，該介電層設置在渠溝遮罩下方，該渠溝遮罩設置在穿孔遮罩下方，從而形成一堆疊，該方法包含：經由該穿孔遮罩蝕刻部份複數穿孔至該介電層中；使該渠溝遮罩露出；經由該渠溝遮罩蝕刻複數渠溝至該介電層中，其中蝕刻該等渠溝之步驟完成並過蝕刻該等穿孔，以使該等穿孔的底部變寬；將一平坦化線以上的該等渠溝或穿孔的頂部修圓；將該等穿孔及渠溝填滿導電材料；以及將該堆疊平坦化至該平坦化線。
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