CN104302811A - 全部在一整合蚀刻中的金属硬掩模 - Google Patents

全部在一整合蚀刻中的金属硬掩模 Download PDF

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CN104302811A
CN104302811A CN201280072908.2A CN201280072908A CN104302811A CN 104302811 A CN104302811 A CN 104302811A CN 201280072908 A CN201280072908 A CN 201280072908A CN 104302811 A CN104302811 A CN 104302811A
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hole
groove
dielectric layer
full circle
mask
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CN104302811B (zh
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程宇
黄举文
裴慧远
刘建刚
崔英辰
王亮
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Lam Research Corp
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Abstract

本发明提供了一种用于在介电层中形成半导体触头的方法。部分通孔通过通孔掩模被蚀刻到介电层中。沟槽通过沟槽掩模被蚀刻到介电层中，其中蚀刻沟槽完成并过蚀刻通孔以拓宽通孔的底部。沟槽或通孔的顶部被整圆。

Description

全部在一整合蚀刻中的金属硬掩模
技术领域
本发明涉及介电层中的通孔和沟槽的形成。更具体地，本发明涉及利用沟槽金属硬掩模来形成通孔和沟槽。
背景技术
在半导体晶片处理过程中，通孔和沟槽的双镶嵌结构被蚀刻到介电层中。接着用导电材料填充该双镶嵌结构以形成触头。
发明内容
为了实现上述工艺以及根据本发明的目的，一种用于在介电层中形成导电触头的方法被提供。部分通孔(partial vias)通过通孔掩模被蚀刻到所述介电层中。沟槽通过沟槽掩模被蚀刻到所述介电层中，其中蚀刻所述沟槽完成且过蚀刻所述通孔以拓宽通孔的底部。沟槽或通孔的顶部被整圆(round)。
在本发明的另一表现中，一种用于在形成叠层的在置于置于通孔掩模下面的沟槽掩模下面的介电层中形成导电触头的方法被提供。部分通孔(partial vias)通过通孔掩模被蚀刻到所述介电层中。沟槽掩模暴露。沟槽通过沟槽掩模被蚀刻到所述介电层中，其中蚀刻所述沟槽完成并过蚀刻所述通孔以拓宽通孔的底部。沟槽或通孔的顶部被整圆到整平线(planarization line)以上。用导电材料填充所述通孔和沟槽。所述叠层被整平到所述整平线。
下面，在本发明的详细描述中，结合随后的附图，将更详细地描述本发明的这些特征以及其它特征。
附图说明
在附图中，本发明通过实施例的方式而非限制的方式进行阐释，其中类同的附图标记指代类同的元素，且其中：
图1是本发明的实施方式的高阶流程图。
图2A-2G是根据本发明的实施方式加工的叠层的示意图。
图3是沿着图2G的切割线3-3的剖视图。
具体实施方式
现在将参考附图中所示的本发明的一些优选实施方式详细描述本发明。在接下来的描述中，阐述了若干具体细节以便提供对本发明的彻底理解。然而，对本领域技术人员来说，显而易见的是，本发明可在没有这些具体细节中的一些或全部的情况下被实施。另一方面，公知的工艺步骤和结构没有被详细描述以免不必要地模糊本发明。
为方便理解，图1是本发明实施方式中所使用的工艺的高阶流程图。衬底被提供有介电层，在该介电层上放置沟槽掩模，在该沟槽掩模上放置通孔掩模(步骤104)。沟槽掩模可以是硬掩模，其中整平层将沟槽掩模与通孔掩模分开。通孔通过通孔掩模被部分蚀刻到介电层中(步骤108)。沟槽掩模暴露(步骤112)。沟槽被蚀刻到介电层中，同时通孔完成且被过蚀刻(步骤116)。过蚀刻通孔可增加通孔底部的宽度。沟槽或通孔的顶部被整圆，这在说明书和权利要求书中包括在顶角(top corner)上琢面(faceting)或使顶角倾斜(sloping)(步骤120)。用导电材料填充通孔和沟槽以形成触头(步骤124)。介电层被整平到整平目标(planarization target)(步骤128)。
实施例
在本发明的实施例中，衬底被提供有介电层，在该介电层上放置通孔掩模，在该通孔掩模上放置沟槽掩模(步骤104)。图2A是具有上面已形成接触层208的衬底204的叠层200的剖视图。在接触层208之上是蚀刻停止层或阻挡层212。在接触层208内是触头216。介电层220已被形成在蚀刻停止层212之上。在该实施例中，蚀刻停止层212是氮掺杂碳化硅(SiCN)衬垫。图案化的沟槽掩模224已被形成在介电层220之上。在该实施例中，图案化的沟槽掩模224是硬掩模。例如，图案化的沟槽掩模224是氮化钛(TiN)。整平层228被形成在图案化的沟槽掩模224之上。图案化的通孔掩模232被形成在整平层228之上。图案化的通孔掩模232可以由光刻胶或一些其它材料制成。在本发明的其它实施例中，附加层可被添加到各个层和掩模之间或者各个层可被其它层替代或者层可被移除。
通孔通过通孔掩模232被部分蚀刻到介电层220中。图2B是在通孔240已被部分蚀刻到介电层220中之后的叠层200的剖视图。在该实施例中，通孔侧壁稍微变尖细(taper)。可用于蚀刻部分通孔的配方的实例提供由C4F8、CF4、N2、Ar和O2组成的通孔蚀刻气体。室压被维持在20到60毫托(mTorr)之间。晶片温度被维持在50℃到100℃之间。
接着，沟槽掩模224暴露(步骤112)。在一实施例中，剩余的通孔掩模232和整平层228被同时移除以暴露沟槽掩模224。在另一实施例中，通孔掩模232可在部分通孔的蚀刻过程中被移除，而整平层228在沟槽掩模224的暴露过程中被移除。图2C是在通孔掩模232和整平层228已被移除以暴露沟槽掩模224之后的叠层200的剖视图。可用于暴露沟槽掩模的配方的实例提供由CO2和O2组成的剥离气体。室压被维持在20到60mTorr之间。晶片温度被维持在50℃到100℃之间。
沟槽通过图案化的沟槽掩模被蚀刻到介电层中，这也完成并过蚀刻通孔以拓宽通孔的底部(步骤116)。图2D示出了在沟槽244被蚀刻且通孔240被过蚀刻之后的叠层200，拓宽了通孔240的底部，形成较少变尖细且更垂直的侧壁。在该实施例中，通孔具有圆形横截面，其中沟槽沿着到页(page)中的线具有线性横截面，每个沟槽连接多个通孔。优选地，用于形成沟槽和过蚀刻通孔的蚀刻比部分通孔蚀刻更有选择性。较少选择性的部分通孔蚀刻的优点在于这样的蚀刻比较快。更有选择性的沟槽蚀刻和通孔过蚀刻的优点在于这样的蚀刻提供较少变尖细的更垂直的侧壁。可用于蚀刻沟槽和过蚀刻通孔的配方的实例提供由C4F8、CF4、N2、Ar和O2组成的沟槽蚀刻气体。20到60mTorr的室压被提供。晶片温度被维持在50℃到100℃之间。
沟槽的顶部被整圆(步骤120)。图2E示出了沟槽244的顶部252已被整圆之后的叠层。所述整圆发生在整平目标线或平面248之上。优选地，在整平目标线248以下不发生整圆。因为所述顶部在整平目标线或平面248之上被整圆，所以在整平目标线248之上的沟槽244的顶部252的侧壁薄(shallow)于整平目标线248之下的侧壁。在该实施例中，沟槽的顶部252在蚀刻停止层212的开口过程中被整圆。更优选地，整圆和蚀刻停止开口是两个步骤的工艺。在这种配方的实例中，包括CF4、C4F8、N2和Ar的整圆气体被提供。整圆气体被形成为等离子体。卡盘温度被维持在50℃到100℃之间。
通孔和沟槽被填充(步骤124)。在该实施例中，用含铜导体填充沟槽和通孔。图2F示出了用含铜导体256填充通孔240和沟槽244之后的叠层200。用于填充沟槽和通孔的一种示例性配方提供铜电镀。在该实施例中，首先，阻挡层被形成在通孔和沟槽的壁上。接着，种子层被形成在阻挡层上。电压被施加到种子层，通孔和沟槽被置于含铜酸浴中。含铜金属被沉积在种子层上的沟槽和通孔中。在其它实施例中，可以使用无电镀铜沉积。
叠层200被整平(步骤128)。在该实施例中，化学机械抛光(CMP)被用来将叠层200整平到整平目标线或平面248。图2G示出了在叠层被整平到整平目标线或平面248之后的叠层。图3是叠层200的沿着图2G的切割线3-3的剖视图。图3中的视图更清楚地示出了沟槽244的线性剖视图和通孔240的剖视图。
所得的结构提供了具有基本上垂直的侧壁的沟槽和通孔。填充沟槽244和通孔240的导电金属256形成导电触头和互连体。对于28nm的栅CD而言，已发现整圆沟槽的顶部移除了角且提供了允许改进的沉积的更宽的开口以用于填充通孔和沟槽。角的移除还减少了突出部分(overhang)，从而改进了沉积。还发现更宽的开口增加了触头之间的渗漏。通过只拓宽沟槽在整平目标以上的顶部以及然后移除整平目标以上的叠层，导电材料的填充被改进但不增加渗漏。另外，使用较小选择性的蚀刻来部分蚀刻通孔以及然后使用较高选择性的蚀刻来蚀刻沟槽和过蚀刻通孔的组合实现了较快的提供垂直侧壁的蚀刻工艺。本发明的实施例避免了弯曲。本发明的实施例提供了更好的鲁棒性和额外的控制，这可用于调整参数以减少条纹或弯曲或者提供其它有益效果。
可以使用附加工艺来完成半导体器件的形成。
虽然本发明已就若干优选实施例进行了描述，但还有落在本发明的范围内的变更方式、置换方式、修改方式和各种替代等同方式。还应当注意，实施本发明的方法和装置有许多替代方式。因此，意图在于将接下来所附的权利要求书解释为包括落在本发明的真实精神和范围内的所有这样的变更方式、置换方式和各种替代等同方式。

Claims (27)

1.一种用于在介电层中形成导电触头的方法，其包括：
通过通孔掩模将部分通孔蚀刻到所述介电层中；
通过沟槽掩模将沟槽蚀刻到所述介电层中，其中蚀刻所述沟槽完成并过蚀刻所述通孔以拓宽所述通孔的底部；以及
整圆所述沟槽或通孔的顶部。
2.如权利要求1所述的方法，其中所述整圆所述沟槽或通孔的顶部使位于所述通孔的底部的蚀刻停止层开口。
3.如权利要求2所述的方法，其进一步包括：
用含铜导电材料填充所述通孔和沟槽；以及
将所述通孔、沟槽和介电层整平到整平目标。
4.如权利要求3所述的方法，其中所述整圆所述沟槽或通孔的顶部不整圆所述沟槽和通孔在所述整平目标之下的部分。
5.如权利要求4所述的方法，其中所述整圆所述沟槽或通孔的顶部提供了50℃到100℃之间的静电卡盘温度，且其中蚀刻所述沟槽比蚀刻所述部分通孔更有选择性。
6.如权利要求5所述的方法，其中所述整圆所述沟槽或通孔的顶部进一步包括提供包括CF4、C4F8和N2的气体。
7.如权利要求6所述的方法，其中所述气体进一步包括Ar。
8.如权利要求7所述的方法，其中沟槽图案化硬掩模在所述介电层之上，且其中整平层在所述沟槽图案化硬掩模和介电层之上，且其中通孔图案化掩模在所述整平层之上。
9.如权利要求8所述的方法，其中所述整圆所述沟槽或通孔的顶部使得位于所述沟槽或通孔的顶部的侧壁具有与位于所述整平目标的侧壁不同的斜率。
10.如权利要求9所述的方法，其进一步包括在蚀刻部分通孔之后且在蚀刻沟槽之前暴露所述沟槽掩模。
11.如权利要求1所述的方法，其进一步包括：
用含铜导电材料填充所述通孔和沟槽；以及
将所述通孔、沟槽和介电层整平到整平目标。
12.如权利要求1所述的方法，其中所述整圆所述沟槽或通孔的顶部不整圆所述通孔在所述整平目标之下的部分。
13.如权利要求1所述的方法，其中所述整圆所述沟槽或通孔的顶部提供了50℃到100℃之间的静电卡盘温度。
14.如权利要求13所述的方法，其中所述整圆所述沟槽或通孔的顶部进一步包括提供包括CF4、C4F8和N2的气体。
15.如权利要求14所述的方法，其中所述气体进一步包括Ar。
16.如权利要求1所述的方法，其中沟槽图案化硬掩模在所述介电层之上，且其中整平层在所述沟槽图案化硬掩模和介电层之上，且其中通孔图案化掩模在所述整平层之上。
17.如权利要求16所述的方法，其进一步包括在蚀刻部分通孔之后且在蚀刻沟槽之前暴露所述沟槽掩模。
18.如权利要求1所述的方法，其中所述整圆所述沟槽或通孔的顶部使得位于所述沟槽或通孔的顶部的侧壁具有与位于所述整平目标的侧壁不同的斜率。
19.如权利要求1-2中任一项所述的方法，其进一步包括：
用含铜导电材料填充所述通孔和沟槽；以及
将所述通孔、沟槽和介电层整平到整平目标。
20.如权利要求1-2和19中任一项所述的方法，其中所述整圆所述沟槽或通孔的顶部不整圆所述沟槽和通孔在所述整平目标之下的部分。
21.如权利要求1-2和19-20中任一项所述的方法，其中所述整圆所述沟槽或通孔的顶部提供了50℃到100℃之间的静电卡盘温度，且其中蚀刻所述沟槽比蚀刻所述部分通孔更有选择性。
22.如权利要求1-2和19-21中任一项所述的方法，其中所述整圆所述沟槽或通孔的顶部进一步包括提供包括CF4、C4F8和N2的气体。
23.如权利要求22所述的方法，其中所述气体进一步包括Ar。
24.如权利要求1-2和19-23中任一项所述的方法，其中沟槽图案化硬掩模在所述介电层之上，且其中整平层在所述沟槽图案化硬掩模和介电层之上，且其中通孔图案化掩模在所述整平层之上。
25.如权利要求24所述的方法，其进一步包括在蚀刻部分通孔之后且在蚀刻沟槽之前暴露所述沟槽掩模。
26.如权利要求1-2和19-25中任一项所述的方法，其中所述整圆所述沟槽或通孔的顶部使得位于所述沟槽或通孔的顶部的侧壁具有与位于所述整平目标的侧壁不同的斜率。
27.一种用于在形成叠层的在置于置于通孔掩模下面的沟槽掩模下面的介电层中形成导电触头的方法，其包括：
通过所述通孔掩模将部分通孔蚀刻到所述介电层中；
暴露所述沟槽掩模；
通过所述沟槽掩模将沟槽蚀刻到所述介电层中，其中蚀刻所述沟槽完成并过蚀刻所述通孔以拓宽所述通孔的底部；
整圆所述沟槽或通孔在整平线以上的顶部；
用导电材料填充所述通孔和沟槽；以及
将所述叠层整平到所述整平线。
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