TWI588871B - 在導體圖案間之間隙中包含支撐圖案的半導體裝置及其製造方法 - Google Patents

在導體圖案間之間隙中包含支撐圖案的半導體裝置及其製造方法 Download PDF

Info

Publication number
TWI588871B
TWI588871B TW102131163A TW102131163A TWI588871B TW I588871 B TWI588871 B TW I588871B TW 102131163 A TW102131163 A TW 102131163A TW 102131163 A TW102131163 A TW 102131163A TW I588871 B TWI588871 B TW I588871B
Authority
TW
Taiwan
Prior art keywords
pattern
layer
region
conductor
semiconductor device
Prior art date
Application number
TW102131163A
Other languages
English (en)
Chinese (zh)
Other versions
TW201417144A (zh
Inventor
韓奎熙
商燻 安
Original Assignee
三星電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三星電子股份有限公司 filed Critical 三星電子股份有限公司
Publication of TW201417144A publication Critical patent/TW201417144A/zh
Application granted granted Critical
Publication of TWI588871B publication Critical patent/TWI588871B/zh

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/011Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/20Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/08Planarisation of organic insulating materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/072Manufacture or treatment of dielectric parts thereof of dielectric parts comprising air gaps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/074Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/075Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers of multilayered thin functional dielectric layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/074Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/077Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/081Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/093Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/096Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by contacting with gases, liquids or plasmas
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43Layouts of interconnections
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/46Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising air gaps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48Insulating materials thereof
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495Capacitive arrangements or effects of, or between wiring layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/037Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being on top of a main fill metal
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425Barrier, adhesion or liner layers

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Geometry (AREA)
  • Formation Of Insulating Films (AREA)
  • Semiconductor Memories (AREA)
TW102131163A 2012-09-05 2013-08-30 在導體圖案間之間隙中包含支撐圖案的半導體裝置及其製造方法 TWI588871B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020120098464A KR102002815B1 (ko) 2012-09-05 2012-09-05 반도체 장치 및 이의 제조 방법

Publications (2)

Publication Number Publication Date
TW201417144A TW201417144A (zh) 2014-05-01
TWI588871B true TWI588871B (zh) 2017-06-21

Family

ID=50153452

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102131163A TWI588871B (zh) 2012-09-05 2013-08-30 在導體圖案間之間隙中包含支撐圖案的半導體裝置及其製造方法

Country Status (6)

Country Link
US (2) US9337150B2 (https=)
JP (1) JP6356396B2 (https=)
KR (1) KR102002815B1 (https=)
CN (1) CN103681600B (https=)
DE (1) DE102013109297B4 (https=)
TW (1) TWI588871B (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI686928B (zh) * 2018-08-15 2020-03-01 台灣積體電路製造股份有限公司 積體電路與其形成方法

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102119829B1 (ko) * 2013-09-27 2020-06-05 에스케이하이닉스 주식회사 반도체 장치 및 그 제조 방법
US9312168B2 (en) * 2013-12-16 2016-04-12 Applied Materials, Inc. Air gap structure integration using a processing system
US9330969B2 (en) * 2014-02-12 2016-05-03 Sandisk Technologies Inc. Air gap formation between bit lines with top protection
FR3018951B1 (fr) * 2014-03-18 2017-06-09 Commissariat Energie Atomique Procede de gravure d'un materiau dielectrique poreux
US9583380B2 (en) * 2014-07-17 2017-02-28 Globalfoundries Inc. Anisotropic material damage process for etching low-K dielectric materials
KR102201092B1 (ko) * 2014-09-16 2021-01-11 삼성전자주식회사 반도체 장치 제조 방법
CN104327850B (zh) * 2014-11-03 2016-04-06 天津理工大学 一种氮化物荧光粉的低温等离子体制备方法
US10483160B2 (en) * 2015-09-23 2019-11-19 Intel Corporation Ultra thin helmet dielectric layer for maskless air gap and replacement ILD processes
US9449871B1 (en) * 2015-11-18 2016-09-20 International Business Machines Corporation Hybrid airgap structure with oxide liner
US9865616B2 (en) 2016-02-09 2018-01-09 Toshiba Memory Corporation Semiconductor memory device and method for manufacturing same
US9887134B2 (en) * 2016-02-10 2018-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, methods of manufacture thereof, and methods of singulating semiconductor devices
US10504915B2 (en) 2016-03-03 2019-12-10 Toshiba Memory Corporation Integrated circuit device having an air gap between interconnects and method for manufacturing the same
KR102658192B1 (ko) * 2016-07-27 2024-04-18 삼성전자주식회사 반도체 장치 및 반도체 장치의 제조 방법
CN107394007B (zh) * 2017-07-31 2019-06-14 渤海大学 一种适用于superstrate结构薄膜太阳电池硫化或硒化的方法
EP3654372B1 (en) 2018-11-13 2021-04-21 IMEC vzw Method of forming an integrated circuit with airgaps and corresponding integrated circuit
WO2020205335A1 (en) * 2019-04-05 2020-10-08 Tokyo Electron Limited Independent control of etching and passivation gas components for highly selective silicon oxide/silicon nitride etching
US12575143B2 (en) 2020-07-23 2026-03-10 Nanya Technology Corporation Semiconductor device with air gap and boron nitride cap and method for preparing the same
US11380758B2 (en) 2020-07-23 2022-07-05 Nanya Technology Corporation Semiconductor device with air gap and boron nitride cap and method for forming the same
CN114695270B (zh) 2020-12-30 2024-11-01 长鑫存储技术有限公司 半导体器件的制备方法及半导体器件
US12381113B2 (en) * 2021-08-27 2025-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device structure having air gap and methods of forming the same
JPWO2024134907A1 (https=) * 2022-12-23 2024-06-27
DE102023133538B4 (de) 2023-11-30 2025-12-31 Infineon Technologies Ag Leistungs-halbleiterbauelement mit metallstrukturpassivierung und verfahren zur herstellung des leistungs-halbleiterbauelements

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100270677A1 (en) * 2009-04-24 2010-10-28 Nec Electronics Corporation Semiconductor device and method of manufacturing semiconductor device
US20120126302A1 (en) * 2010-11-18 2012-05-24 Mitsuhiko Noda Nonvolatile semiconductor memory device and manufacturing method of the same

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6093634A (en) * 1999-07-26 2000-07-25 United Microelectronics Corp. Method of forming a dielectric layer on a semiconductor wafer
US6252290B1 (en) 1999-10-25 2001-06-26 Chartered Semiconductor Manufacturing Ltd. Method to form, and structure of, a dual damascene interconnect device
JP2001217310A (ja) * 2000-02-02 2001-08-10 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US6917109B2 (en) 2002-11-15 2005-07-12 United Micorelectronics, Corp. Air gap structure and formation method for reducing undesired capacitive coupling between interconnects in an integrated circuit device
KR100508538B1 (ko) 2003-02-04 2005-08-17 동부아남반도체 주식회사 반도체 금속 라인 제조 공정에서의 에어 갭 형성 방법
JP2007523465A (ja) 2003-05-26 2007-08-16 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 多孔質の誘電体層とエアギャップとを有する基板の製造方法、および基板
KR100772835B1 (ko) 2006-07-12 2007-11-01 동부일렉트로닉스 주식회사 에어갭을 포함하는 반도체 소자 및 그 제조방법
US7803713B2 (en) * 2006-09-21 2010-09-28 Taiwan Semiconductor Manufacturing Co. Ltd. Method for fabricating air gap for semiconductor device
JP2008294335A (ja) * 2007-05-28 2008-12-04 Panasonic Corp 半導体装置の製造方法
US7868455B2 (en) 2007-11-01 2011-01-11 Taiwan Semiconductor Manufacturing Company, Ltd. Solving via-misalignment issues in interconnect structures having air-gaps
US20090121356A1 (en) 2007-11-12 2009-05-14 Rohm Co., Ltd. Semiconductor device and method of manufacturing semiconductor device
JP2009123775A (ja) * 2007-11-12 2009-06-04 Rohm Co Ltd 半導体装置および半導体装置の製造方法
JP2009212218A (ja) * 2008-03-03 2009-09-17 Toshiba Corp 半導体記憶装置及びその製造方法
US7754601B2 (en) 2008-06-03 2010-07-13 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor interconnect air gap formation process
JP2010056112A (ja) * 2008-08-26 2010-03-11 Fujitsu Microelectronics Ltd 半導体装置の製造方法
KR101005669B1 (ko) 2008-09-03 2011-01-05 주식회사 동부하이텍 반도체 소자의 에어갭 제조 방법
US8298911B2 (en) * 2009-03-26 2012-10-30 Samsung Electronics Co., Ltd. Methods of forming wiring structures
KR101517851B1 (ko) 2009-03-26 2015-05-06 삼성전자 주식회사 반도체 소자의 제조 방법
KR20100122700A (ko) 2009-05-13 2010-11-23 주식회사 하이닉스반도체 반도체 소자의 제조방법
KR20110013162A (ko) 2009-07-31 2011-02-09 주식회사 하이닉스반도체 반도체 장치 제조 방법
US8390079B2 (en) * 2010-10-28 2013-03-05 International Business Machines Corporation Sealed air gap for semiconductor chip
US8182682B1 (en) 2011-02-25 2012-05-22 Pall Corporation Fluid treatment elements and assemblies
JP2012204537A (ja) * 2011-03-24 2012-10-22 Toshiba Corp 半導体記憶装置およびその製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100270677A1 (en) * 2009-04-24 2010-10-28 Nec Electronics Corporation Semiconductor device and method of manufacturing semiconductor device
US20120126302A1 (en) * 2010-11-18 2012-05-24 Mitsuhiko Noda Nonvolatile semiconductor memory device and manufacturing method of the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI686928B (zh) * 2018-08-15 2020-03-01 台灣積體電路製造股份有限公司 積體電路與其形成方法

Also Published As

Publication number Publication date
CN103681600A (zh) 2014-03-26
CN103681600B (zh) 2017-12-12
TW201417144A (zh) 2014-05-01
KR102002815B1 (ko) 2019-07-23
JP2014053612A (ja) 2014-03-20
US20160225658A1 (en) 2016-08-04
DE102013109297A1 (de) 2014-03-13
US9741608B2 (en) 2017-08-22
US20140061926A1 (en) 2014-03-06
US9337150B2 (en) 2016-05-10
DE102013109297B4 (de) 2026-01-15
KR20140033579A (ko) 2014-03-19
JP6356396B2 (ja) 2018-07-11

Similar Documents

Publication Publication Date Title
TWI588871B (zh) 在導體圖案間之間隙中包含支撐圖案的半導體裝置及其製造方法
TWI524491B (zh) 半導體裝置及半導體裝置的製造方法
KR101600217B1 (ko) 자기-폐쇄 비대칭 상호연결 구조
TWI249774B (en) Forming method of self-aligned contact for semiconductor device
TWI549245B (zh) 用於形成具有緊密間距互連結構之互連層的方法
US8822287B2 (en) Methods of manufacturing semiconductor devices
KR101583516B1 (ko) 전극 구조체를 구비하는 캐패시터, 이의 제조 방법 및 전극 구조체를 포함하는 반도체 장치
TW503473B (en) Semiconductor wafer device having separated conductive patterns in peripheral area and its manufacture method
US8513809B2 (en) Semiconductor device
CN107464813A (zh) 一种半导体器件及其制作方法和电子装置
US8431485B2 (en) Manufacturing method for a buried circuit structure
CN101006576B (zh) 集成低k硬掩膜
TW200418106A (en) Method for fabricating semiconductor device
TW201735303A (zh) 用於形成具有改善的調正及電容降低之導電特徵的技術
CN106898575B (zh) 一种半导体器件及其制造方法、电子装置
US20090014886A1 (en) Dynamic random access memory with an electrostatic discharge structure and method for manufacturing the same
CN100527382C (zh) 制造半导体存储器件的方法
CN108364953A (zh) 三维存储器件及其制作过程的器件保护方法
TWI770050B (zh) 積體電路裝置及其形成方法
CN107527913B (zh) 一种半导体器件及其制造方法和电子装置
KR101103550B1 (ko) 반도체 소자의 금속배선 형성방법
US20080050878A1 (en) Method for preparing a memory structure
CN118943127A (zh) 堆叠电容结构及其形成方法
JP2009182262A (ja) フラッシュメモリ及びその製造方法
JP2009253245A (ja) 半導体装置の製造方法