TWI580005B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TWI580005B
TWI580005B TW103105849A TW103105849A TWI580005B TW I580005 B TWI580005 B TW I580005B TW 103105849 A TW103105849 A TW 103105849A TW 103105849 A TW103105849 A TW 103105849A TW I580005 B TWI580005 B TW I580005B
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Tomomitsu Risaki
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Sii Semiconductor Corp
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    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
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    • H01L27/0203—Particular design considerations for integrated circuits
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    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
    • H01L27/0274—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path involving a parasitic bipolar transistor triggered by the electrical biasing of the gate electrode of the field effect transistor, e.g. gate coupled transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
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Description

半導體裝置
本發明係關於具有使用N通道型MOS電晶體之ESD保護電路的半導體裝置。
由半導體積體電路所成的半導體裝置，係具有作為外部連接用電極的焊墊。於該焊墊的附近，通常會設置從ESD(靜電放電)保護半導體裝置之內部電路的ESD保護電路。於ESD保護電路之一，有使用多指型的N通道型MOS電晶體(以下稱為NMOS電晶體)者。在此，該NMOS電晶體的閘極與源極連接於接地端子，汲極連接於焊墊及內部電路(例如，參照專利文獻1)。
〔先前技術文獻〕 〔專利文獻〕
〔專利文獻1〕日本特開2007-116049號公報
在專利文獻1所揭示之技術中，於使用NMOS電晶體 的ESD保護電路中，利用調整汲極的接點與閘極電極之間的金屬矽化物阻擋層寬度，來提升ESD耐受量。該構造之狀況中，於汲極的接點與閘極電極之間有金屬矽化物阻擋層，於源極的接點與閘極電極之間並無金屬矽化物阻擋層。圖3係揭示此種狀況之電晶體的範例。ESD保護電路的NMOS電晶體30係具有連接於焊墊40及內部電路的汲極配線53a，與連接於接地配線的閘極51及源極配線52a。如圖3所示，通常於NMOS電晶體50的區域中，因為佈局設計成汲極配線53a的配線寬度大於源極配線52a的配線寬度，所以，汲極配線53a的電阻值低於源極配線52a的電阻值。
正的突波電壓被施加至焊墊40時，產生之突波電流係從焊墊40透過NMOS電晶體50，流至接地端子。具體來說，突波電流係依序流至汲極配線53a所代表之電阻與閘極51下的通道區域之電阻與源極配線52a所代表之電阻。該電流路徑係對於閘極寬度存在無數，例如圖3的路徑1與路徑2也成為電流路徑。
假設，NMOS電晶體50於通道寬度方向均等地被5分割時，將該分割之1個長度之汲極配線與源極配線的電阻設為Rd0與Rs0，將路徑1假定為從汲極配線3a側(圖3的上方側)觀看，閘極寬度為1/5之處的路徑，將路徑2假定為閘極寬度為4/5之處的路徑的話，路徑1及路徑2的電阻成分，係分別如以下所示。
路徑1的電阻成分=1Rd0+Rch+4Rs0
路徑2的電阻成分=4Rd0+Rch+1Rs0
於圖4揭示以該式表示之被分割的NMOS電晶體的等效電路圖。如該圖所示，例如汲極配線的電阻Rd0係包含配線金屬的電阻、接點的電阻、汲極區域的電阻等的所有電阻成分。在此，因為汲極配線寬度>源極配線寬度，所以，Rd0<Rs0，路徑1的電阻成分>路徑2的電阻成分可成立，突波電流係相較於路徑1，於路徑2中更容易流動。亦即，於各梳指中突波電流集中於源極配線52a側(圖3的下方側)的閘極。因此，該部分的通道區域附近容易被破壞，NMOS電晶體50及半導體裝置的ESD耐受量會變低。
本發明係有鑑於前述課題所發明者，提供ESD耐受量高的半導體裝置。
本發明係為了解決前述課題，提供一種半導體裝置，係具有NMOS電晶體型ESD保護電路的半導體裝置，其特徵為：具備：前述NMOS電晶體，係多指型，且具有被交互配置於半導體基板表面之複數源極及複數汲極、被配置於前述源極與前述汲極之間的複數通道區域、及設置於前述通道區域上的閘極；源極配線，係於前述NMOS電晶體的區域中設置於前述閘極及前述源極之上，電性連接前述閘極與前述源極與接地端子；及汲極配線，係於前述NMOS電晶體的區域中設置於前述汲極之上，電性連接前 述汲極與作為外部連接用電極的焊墊，且於前述NMOS電晶體的區域中與前述源極配線的配線寬度相同的配線寬度。
依據本發明，即使不增加晶片尺寸，也可提高半導體裝置的ESD耐受量。
30‧‧‧NMOS電晶體
31‧‧‧閘極
32‧‧‧源極
33‧‧‧汲極
32a‧‧‧源極配線
33a‧‧‧汲極配線
34‧‧‧接點
20‧‧‧焊墊
Rs‧‧‧源極配線的寄生電阻
Rd‧‧‧汲極配線的寄生電阻
Rch‧‧‧通道區域的寄生電阻
〔圖1〕揭示使用半導體裝置內之NMOS電晶體的ESD保護電路的俯視圖。
〔圖2〕揭示半導體裝置內的ESD保護電路的電路圖。
〔圖3〕揭示先前之使用半導體裝置內之NMOS電晶體的ESD保護電路的俯視圖。
〔圖4〕被分割之NMOS電晶體的等效電路圖。
以下，針對本發明的實施形態，參照圖面來進行說明。
首先，針對使用NMOS電晶體之ESD保護電路的半導體裝置的構造，使用圖1來說明。圖1係揭示使用NMOS電晶體的ESD保護電路的俯視圖。
NMOS電晶體30係多指型，複數源極區域32及複數 汲極區域33係交互配置於半導體基板表面。複數通道區域係配置於源極區域32與汲極區域33之間，閘極電極31設置於通道區域之上。源極配線32a係於NMOS電晶體30的區域中設置於閘極電極31及源極區域32之上。源極配線32a係電性連接閘極電極31與源極區域32與接地端子。汲極配線33a係於NMOS電晶體30的區域中設置於汲極區域33之上，並未設置於閘極電極31之上。汲極配線33a係電性連接汲極區域33與作為外部連接用電極的焊墊20。又，於NMOS電晶體30的區域中，汲極配線33a係具有與源極配線32a的配線寬度相同的配線寬度，接點34的配置方法係在兩配線同等。在此，將挾持一個閘極電極的源極區域及源極配線與汲極區域及汲極配線，稱為一個梳指。然後，NMOS電晶體30係一個梳指折返，依序連續配置所形成。
接著，針對NMOS電晶體30的ESD保護動作，進行說明。圖2係揭示半導體裝置的ESD保護電路的電路圖。
對焊墊20施加突波電壓時，突波電流係以從焊墊20往接地端子透過ESD保護電路流動之方式設計。此時，NMOS電晶體30係藉由以表面擊穿作為觸發點的雙極動作，讓該突波電流從汲極流向源極，突波電流係流動於NMOS電晶體30，不會流至內部電路。如此，從突波電流保護內部電路。
此時，突波電流係依序流至汲極配線33a的電阻與閘 極31之下的通道區域的電阻與源極配線32a的電阻。即使於圖1中，也與圖3的狀況相同，將NMOS電晶體30的一個梳指往通道寬度方向均等地5分割，將各區域之汲極配線33a的電阻設為Rd0，通道區域的電阻設為Rch，源極配線的電阻設為Rs0的話，路徑1及路徑2的電阻成分可以下列式表示：路徑1的電阻成分=1Rd0+Rch+4Rs0
路徑2的電阻成分=4Rd0+Rch+1Rs0
與先前例相同，於圖4所示，可利用被分割之NMOS電晶體的等效電路來表示。但是，如圖1所示，在NMOS電晶體30的區域中，汲極配線53a的配線寬度與源極配線52a的配線寬度相同地佈局設計，接點34的配置也同等，所以，可成立Rd0=Rs0，路徑1的電阻成分=路徑2的電阻成分。
亦即，被均等分割之各部分的電阻相等。電阻被均等分割時，突波電流於NMOS電晶體30的一個梳指中即使流至哪個通道區域，從焊墊20到接地端子為止之間，突波電流相對之配線的電阻的合計電阻值也相同。於是，突波電流係於通道區域中，不會集中於特定部分。因此，該特定部分的通道區域附近不容易被破壞，NMOS電晶體30及半導體裝置的ESD耐受量會變高。
又，將源極配線32a不僅配置於源極區域32之上，也配置於閘極電極31上的理由，是為了避免元件尺寸的增大，與ESD耐受量的降低。根據前述內容，為了使寄 生電阻相同，汲極配線33a與源極配線32a的配線寬度相同有助於ESD耐受量提升，但是，即使使該等配線寬度相同，配線寬度過細的話，也會因為突波電流，造成配線熔解，導致ESD耐受量降低。因此，汲極配線33a與源極配線32a的配線寬度為至少與汲極區域33同等的寬度較理想。但是，於具有比汲極區域33的寬度更狹窄之寬度的源極區域32之上，配置與汲極區域33同等之寬度的源極配線32a來說，源極區域32過於狹小。作為其解決策之一，可舉出使源極區域32的寬度成為與汲極區域33的寬度同等，但是，這樣的話，元件尺寸會變大，會影響晶片尺寸增加。因此，利用不擴張源極區域32，將源極配線32a設置至閘極電極31上為止，可避免元件尺寸的增大，與ESD耐受量的降低。
20‧‧‧焊墊
30‧‧‧NMOS電晶體
31‧‧‧閘極
32‧‧‧源極
32a‧‧‧源極配線
33‧‧‧汲極
33a‧‧‧汲極配線
34‧‧‧接點

Claims (3)

  1. 一種半導體裝置，其特徵為：具備：多指型的NMOS電晶體，係組合具有被交互配置於半導體基板表面之複數源極區域及複數汲極區域、被配置於前述源極區域與前述汲極區域之間的複數通道區域、及設置於前述通道區域上的閘極電極的相同梳指；源極配線，係於前述NMOS電晶體的前述梳指的區域中設置於前述閘極電極及前述源極區域之上，電性連接前述閘極電極與前述源極區域與接地端子；及汲極配線，係於前述NMOS電晶體的區域中設置於前述汲極區域之上，電性連接前述汲極區域與作為外部連接用電極的焊墊，前述NMOS電晶體的各梳指，係於通道寬度方向均等分割時，被分割之各部分的電阻值相等。
  2. 如申請專利範圍第1項所記載之半導體裝置，其中，前述源極配線與前述汲極配線的寬度於前述各梳指中相等。
  3. 一種半導體裝置，其特徵為具備：多指型的NMOS電晶體，係組合具有被交互配置於半導體基板表面之複數源極區域及複數汲極區域、被配置於前述源極區域與前述汲極區域之間的複數通道區域、及設置於前述通道區域上的閘極電極的相同梳指； 源極配線，係於前述NMOS電晶體的前述梳指的區域中設置於前述閘極電極及前述源極區域之上，電性連接前述閘極電極與前述源極區域與接地端子；及汲極配線，係於前述NMOS電晶體的區域中設置於前述汲極區域之上，電性連接前述汲極區域與作為外部連接用電極的焊墊，於前述NMOS電晶體的區域中具有與前述源極配線的配線寬度相同的配線寬度。
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