CN105009264A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN105009264A
CN105009264A CN201480012059.0A CN201480012059A CN105009264A CN 105009264 A CN105009264 A CN 105009264A CN 201480012059 A CN201480012059 A CN 201480012059A CN 105009264 A CN105009264 A CN 105009264A
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理崎智光
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Ablic Inc
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    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
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    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
    • H01L27/0274—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path involving a parasitic bipolar transistor triggered by the electrical biasing of the gate electrode of the field effect transistor, e.g. gate coupled transistors
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Abstract

为了提供ESD耐量高的半导体装置，源布线(32a)在NMOS晶体管(30)的区域中设置在栅极(31)和源极(32)上。源布线(32a)将栅极(31)、源极(32)和接地端子电连接。漏布线(33a)在NMOS晶体管(30)的区域中设置在漏极(33)上。漏布线(33a)将漏极(33)和作为外部连接用电极的焊盘(20)电连接。此外，在NMOS晶体管(30)的区域中，漏布线(33a)具有与源布线(32a)的布线宽度相同的布线宽度。

Description

半导体装置
技术领域
本发明涉及具有使用了N沟道型MOS晶体管的ESD保护电路的半导体装置。
背景技术
由半导体集成电路构成的半导体装置具有作为外部连接用电极的焊盘。在该焊盘的附近通常设置有保护半导体装置的内部电路免受ESD(静电放电)损伤的ESD保护电路。ESD保护电路之一有使用了多指型的N沟道型MOS晶体管(以下记作NMOS晶体管)的ESD保护电路。这里，该NMOS晶体管的栅极和源极与接地端子连接，漏极与焊盘和内部电路连接(例如，参照专利文献1)。
现有技术文献
专利文献
专利文献1：日本特开2007-116049号公报
发明内容
发明所要解决的问题
在专利文献1公开的技术中，在使用了NMOS晶体管的ESD保护电路中，通过调整漏极的触点与栅电极之间的自对准硅化物(salicide)块宽度，提高了ESD耐量。在该结构的情况下，在漏极的触点与栅电极之间存在自对准硅化物块，在源极的触点与栅电极之间不存在自对准硅化物块。图3示出这种状况的晶体管的例子。ESD保护电路的NMOS晶体管30具有：与焊盘40和内部电路连接的漏布线53a、以及与接地布线连接的栅极51和源布线52a。如图3所示，通常，在NMOS晶体管50的区域中，由于布局设计成漏布线53a的布线宽度比源布线52a的布线宽度粗，所以漏布线53a的电阻值比源布线52a的电阻值低。
当正的浪涌电压被施加到焊盘40时，产生的浪涌电流从焊盘40经由NMOS晶体管50流向接地端子。具体而言，浪涌电流依次流过以漏布线53a为代表的电阻、栅极51下方的沟道区域的电阻、和以源布线52a为代表的电阻。该电流路径相对于栅极宽度存在无数个，例如，图3的路径1和路径2都为电流路径。
在假设NMOS晶体管50沿沟道宽度方向被均等地分割成5个部分的情况下，如果将该分割后的一个长度中的漏布线与源布线的电阻设为Rd0和Rs0，将路径1假设为从漏布线3a侧(图3的上方侧)观察时栅极宽度为1/5的场所的路径，将路径2假设为栅极宽度为4/5的场所的路径，则路径1和路径2的电阻分量分别如下所示。
路径1的电阻分量＝1Rd0+Rch+4Rs0
路径2的电阻分量＝4Rd0+Rch+1Rs0
图4示出由该式表示的被分割的NMOS晶体管的等效电路图。如该图所示，例如漏布线的电阻Rd0包含布线金属的电阻、触点的电阻和漏区域的电阻等全部电阻分量。这里，由于漏布线宽度＞源布线宽度，所以，Rd0＜Rs0，由于路径1的电阻分量＞路径2的电阻分量成立，所以相比路径1，浪涌电流更容易在路径2中流过。也就是说，在各个指中，浪涌电流集中在源布线52a侧(图3的下方侧)的栅极。因此，该部分的沟道区域附近容易被破坏，NMOS晶体管50和半导体装置的ESD耐量降低。
本发明是鉴于上述课题而完成的，提供ESD耐量高的半导体装置。
用于解决问题的手段
本发明为了解决上述课题，提供一种半导体装置，其具有NMOS晶体管型的ESD保护电路，所述半导体装置的特征在于，具有：所述NMOS晶体管，其为多指型，具有交替配置于半导体衬底表面的多个源极和多个漏极、配置于所述源极与所述漏极之间的多个沟道区域、和设置在所述沟道区域上的栅极；源布线，其在所述NMOS晶体管的区域中设置在所述栅极和所述源极上，将所述栅极、所述源极和接地端子电连接；以及漏布线，其在所述NMOS晶体管的区域中设置在所述漏极上，将所述漏极和作为外部连接用电极的焊盘电连接，并在所述NMOS晶体管的区域中，具有与所述源布线的布线宽度相同的布线宽度。
发明效果
根据本发明，无需增大芯片尺寸就能够提高半导体装置的ESD耐量。
附图说明
图1是示出半导体装置内的使用了NMOS晶体管的ESD保护电路的俯视图。
图2是示出半导体装置内的ESD保护电路的电路图。
图3是示出现有的半导体装置内的使用了NMOS晶体管的ESD保护电路的俯视图。
图4是被分割的NMOS晶体管的等效电路图。
具体实施方式
以下，参照附图来说明本发明的实施方式。
首先，使用图1说明具有使用了NMOS晶体管的ESD保护电路的半导体装置的构造。图1是示出使用了NMOS晶体管的ESD保护电路的俯视图。
NMOS晶体管30为多指型，多个源区域32和多个漏区域33交替配置于半导体衬底表面。多个沟道区域配置在源区域32与漏区域33之间，栅电极31设置在沟道区域上。源布线32a在NMOS晶体管30的区域中设置在栅电极31和源区域32上。源布线32a将栅电极31、源区域32以及接地端子电连接。漏布线33a在NMOS晶体管30的区域中设置在漏区域33上，不设置在栅电极31上。漏布线33a将漏区域33和作为外部连接用电极的焊盘20(图2)电连接。此外，在NMOS晶体管30的区域中，漏布线33a具有与源布线32a的布线宽度相同的布线宽度，触点34的配置方式在两个布线中是相同的。这里，将夹着一个栅电极的源区域和源布线以及漏区域和漏布线称作一个指。而且，通过使一个指折返并依次连续配置，形成NMOS晶体管30。
接着，说明NMOS晶体管30的ESD保护动作。图2是示出半导体装置的ESD保护电路的电路图。
当向焊盘20施加浪涌电压时，浪涌电流被设计为从焊盘20经由ESD保护电路流向接地端子。这时，NMOS晶体管30利用将表面击穿作为触发的双极动作，使该浪涌电流从漏极流向源极，所以，浪涌电流在NMOS晶体管30中流过，而不流过内部电路。这样，保护内部电路不受浪涌电流的损伤。
这时，浪涌电流依次流过漏布线33a的电阻、栅极31下方的沟道区域的电阻和源布线32a的电阻。即使在图1中，与图3的情况相同地，沿沟道宽度方向将NMOS晶体管30的一个指均等地分割成5个部分，在将各个区域中的漏布线33a的电阻设为Rd0、沟道区域的电阻设为Rch、源布线的电阻设为Rs0时，路径1和路径2的电阻分量能够表示为：
路径1的电阻分量＝1Rd0+Rch+4Rs0
路径2的电阻分量＝4Rd0+Rch+1Rs0，
与现有例同样，能够通过图4所示的、被分割的NMOS晶体管的等效电路表示。但是，如图1所示，在NMOS晶体管30的区域中，由于将漏布线53a的布线宽度布局设计成与源布线52a的布线宽度相同，触点34的配置也相同，所以，Rd0＝Rs0成立，且路径1的电阻分量＝路径2的电阻分量。
即，被均等地分割的各部分的电阻相等。在电阻被均等地分配的情况下，不论浪涌电流在NMOS晶体管30的一个指中流过何处的沟道区域，在焊盘20到接地端子之间，相对于浪涌电流的布线电阻的合计电阻值相同。于是，浪涌电流在沟道区域中，不集中在特定的部分。由此，特定的部分的沟道区域附近不容易被破坏，NMOS晶体管30和半导体装置的ESD耐量增高。
此外，将源布线32a不仅设置在源区域32上，还设置到栅电极31上的理由是避免元件尺寸的增大和ESD耐量的下降。通过上述那样使寄生电阻相同，因此漏布线33a与源布线32a的布线宽度相同有助于ESD耐量提高，但是，即使将它们的布线宽度设为相同，如果布线宽度过细，也会由于浪涌电流造成布线熔断，从而导致ESD耐量下降。因此，漏布线33a与源布线32a的布线宽度理想的是至少与漏区域33相等的宽度。但是，在具有比漏区域33的宽度窄的宽度的源区域32上配置与漏区域33相等宽度的源布线32a时，源区域32过窄。作为解决方案之一，可以举出使源区域32的宽度与漏区域33的宽度相等，但是，这样的话元件尺寸会增大，从而带来芯片尺寸增大的影响。因此，不加宽源区域32，而是将源布线32a设置至栅电极31上，由此能够避免元件尺寸的增大和ESD耐量的下降。
标号说明
30：NMOS晶体管；31：栅极；32：源极；33：漏极；32a：源布线；33a：漏布线；34：触点；20：焊盘；Rs：源布线的寄生电阻；Rd：漏布线的寄生电阻；Rch：沟道区域的寄生电阻。

Claims (2)

1.一种半导体装置，其特征在于，所述半导体装置具有：
多指型的NMOS晶体管，其组合相同的指而成，具有交替配置于半导体衬底表面的多个源区域和多个漏区域、配置于所述源区域与所述漏区域之间的多个沟道区域、和设置在所述沟道区域上的栅电极；
源布线，其在所述NMOS晶体管的区域中设置在所述栅电极和所述源区域上，将所述栅电极、所述源区域和接地端子电连接；以及
漏布线，其在所述NMOS晶体管的区域中设置在所述漏区域上，将所述漏区域和作为外部连接用电极的焊盘电连接，
所述NMOS晶体管的各指在沟道宽度方向上均等地进行了分割时，分割而成的各部分的电阻值相等。
2.根据权利要求1所述的半导体装置，其特征在于，
所述源布线和所述漏布线的宽度在所述各指中是相等的。
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