TWI575622B - 製造半導體構件的方法及相關的半導體構件 - Google Patents

製造半導體構件的方法及相關的半導體構件 Download PDF

Info

Publication number
TWI575622B
TWI575622B TW100118796A TW100118796A TWI575622B TW I575622 B TWI575622 B TW I575622B TW 100118796 A TW100118796 A TW 100118796A TW 100118796 A TW100118796 A TW 100118796A TW I575622 B TWI575622 B TW I575622B
Authority
TW
Taiwan
Prior art keywords
semiconductor wafer
conductive film
wafer
adhesive layer
structured
Prior art date
Application number
TW100118796A
Other languages
English (en)
Other versions
TW201201298A (en
Inventor
瑪堤亞斯 布魯德爾
弗里德爾 哈格
烏爾立克 秀茲
Original Assignee
羅伯特博斯奇股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 羅伯特博斯奇股份有限公司 filed Critical 羅伯特博斯奇股份有限公司
Publication of TW201201298A publication Critical patent/TW201201298A/zh
Application granted granted Critical
Publication of TWI575622B publication Critical patent/TWI575622B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Description

製造半導體構件的方法及相關的半導體構件
本發明關於一種製造半導體構件的方法及利用此方法得到的半導體構件。
在終消費者電子裝置(Consumer Electronics；CE)，一般將微電子構件(積體電路；IC)在一導線架(Leadframe)(Quad Flat Paok No Lead；QFN)或層疊物基材(leadless Grid Array；LGA或Ball Grid Array；BGA)上設成相鄰或上下重疊並利用金屬絲結合件或倒裝(Flip)晶片技術接觸，以作第一位準封裝(First-Level-Package)。在晶片安裝後，將導線架或層疊物基材用模料(Fi-稱壓模料)灌鑄，並鋸切以作切分。這些裝置在一道回流(Reflow)軟銲方法中軟銲到第二位準電路板上。
所謂的「無導線(Leadless)殼體」，例如LGA或QFN，越來越多的方面將傳統的殼體隨支腳(Beechen)撕離，例如：小外輪廓積體電路(SOIC)或塑膠晶片載體(RLCC)撕離。
LGA技術係一種系列封裝程序：包括晶片附著(Die-Attach)，電線結合及模鑄(亦稱灌膠壓鑄)。此外，在封裝時需較多空間以作金屬絲結合連接，在進步的小型化的過程，為了應用微電子，作新的封裝。在所謂的Embedded Wafer Level Ball Grid-Array方法中，晶片在一「拾取及放置程序(Pick and Place)中以活性表面朝下設到一個一設有雙面粘著膜的載體上，然後灌膠。如此造成所謂的複合晶圓或再組構的(rekonfiguriert)晶圓[再建構晶圓(reconstituted Wafer)]，呈一塑膠盤(特別是晶圓形式)的形態，晶片埋入該塑膠盤中，然後將塑膠盤從載體分開，如此，晶片的端子露空。如此，隨後可作配線(Umverdrahtung)。要作配線，係使用一般的薄層技術和材料。複合晶圓的端子墊片(Anschluβpad)(亦稱端子接點)隨後設以銲錫團(Lotbump)。利用鋸切將這些構件從複合晶圓切分出來。
DE 10 2007 020 656 A1發表了一種具半導體晶片的工作物以及製造這種工作物的方法。此製造方法包含以下步驟：提供至少二個半導體晶片(它們具一第一主表面和一第二主表面)，將半導體晶片以其第一主表面放在一載體板的上側，將一導電層施到第二主表面的區域上，將一鑄造料施到導電層上。
依申請專利範圍第1項之製造半導體構件的本發明方法以及依申請專利範圍第9項之利用此方法得到的半導體構件提供一種極端小型化的晶片封裝，其優點由：敏感的晶片表面在灌膠後已受保護以免環境影響及污染。此外它們提供異於除塵室技術所需之薄膜技術的另一種廉價的方式。同時可用簡單方式製造一種到埋入的晶片的媒通道。
本發明基於一項認知：該敏感的晶片表面可用以下方式以簡單的方式保護：將一導電膜施到載體(它需暫時設以半導體晶片)上，並將半導體晶片以活性表面朝入(亦即朝向導電膜)利用一構造化的粘著層施到導電膜上。由於使用構造化粘著層，故端子墊式晶片的敏感區域可保持不帶有塑膠。將施到導電膜上的晶片灌膠。然後將導電的膜隨灌了膠的晶片從載體撕離，晶片之不帶模料的活性表面完全用導電膜蓋住，因此晶片表面不會有在此階段受污染之虞。「粘著」一詞在這方面表示一種材料液的接合。
最好在載體撕離後，在該半導體構件切分之前，宜製造接觸件以將導電膜與半導體晶片的端子接點連接，然後將導電膜構造化。
在申請專利範圍附屬項中係本發明標的之有利之進一步特點及改良。
在一較佳實施例中，該導電的膜為一金屬膜，特別是一銅膜。粘著層係指可撕離而不留殘餘物的粘著層。在此，粘著層係用熱撕離，或者，如使用一透明載體，則利用紫外線照射撕離。
構造化的粘著層(它用於將半導體晶片固定在導電膜上)可施覆到晶圓複合物中的導電膜上或半導體晶片上。因此粘著層的施覆作業係一平行程序，此程序比起粘著劑的系列供應作業來快得多，因此也廉價得多。
粘著層之構造化方式的施覆作業可利用網版印刷達成。舉例而言，也可使用可光構造化的粘著劑，先施覆粘著劑，然後構造化，在和種情形，在晶片固定在導電膜上之前，將導電膜與晶片表面之間的粘著層構造化，如此不須作後續的粘著層構造化(例如利用雷射，它有損壞半導體晶片之虞)。關於導線路的構造化，可使用電路板技術習知的光刻版程序。
粘著層的構造化作業有數個目的。一方面係將晶片的端子墊片用粘著劑牢牢保持住。如此，以後要將導電膜作貫穿接點接到端子墊片就比較簡單。另方面，該半導體晶片的敏感區域可保持露空。
本發明實施例示於圖式中並在以下說明中詳細敘述。
圖中相同的圖號表示相同或功能相同的元件。
圖1係依本發明的一較佳實施例的一道製造程序的一第一程序階段的一橫截面圖。依本發明此較佳實施例，首先將一粘著層(12)施在一載體板(10)上。粘著層(12)做成使它可撕離而不留殘餘物料。圖1顯示具有施覆上去的粘著層(12)的載體板(10)。
圖2係一本發明構件的一實施例的製造程序的第二階段的橫截面圖。依本發明此較佳實施例，一銅膜利用粘著層(12)固定在載體板(10)上。載體板(10)宜具有晶圓形式，但也可用其他格式加工。
在隨後的步驟，將一粘著層(16)施在一半導體晶圓上，並適當地構造化。為此，該粘著劑宜可用光作構造化，如不用此方式，舉例而言，也可將粘著劑利用網版印刷施覆。 粘著劑構造化成使端子墊片以及位在晶圓上的晶片的敏感的區域不含粘著劑。然後將半導體晶圓切分成個別的半導體晶片。
如不將粘著劑施在半導體晶圓上，也可將粘著劑施到銅膜(14)上。
圖3係一本發明構件的一實施例的製造程序的第三階段的橫截面圖。依本發明此較佳實施例，在切分後，將半導體晶片(18)及(20)利用構造化之粘著層(16)粘到銅膜形式的導電的膜(14)上，使它的含有端子墊片形式的端子接點(22)的表面朝向導電的膜(14)，但不與膜接觸成導電方式。圖3中可看到二個晶片(18)(20)，它們利用構造化的粘著層(16)施在該導電的膜(14)〔它固定在載體上〕上。此例子係不同的晶片。它們來自不同晶圓，二者皆依本發明方法製備半導體晶片(18)係一種因用途而異的積體電路。半導體晶片(20)係為一感測器，具一敏感的區域(24)。用此方式，一模組之相關半導體晶片在重組態的晶圓中已互相組合設置。然而，利用本發明的方法當然也可製造只具一種晶片種類的重組態之晶圓。
在粘到銅膜(14)上後，半導體晶片(18)及(20)用模料灌膠構成模封裝件(26)而封裝在模料中。這點可利用壓縮片(Sheet)或轉印模方法達成。在此，模製方法的選擇及加工格式的選擇可有變通性地互相配合。
圖4係一本發明構件的一實施例的製造程序的第四階段的橫截面圖。
圖4顯示從載體板(10)分離後的重組構的晶圓。此時將晶片(18)及(20)埋入模料中並將下側用銅膜形式的導電的膜(14)蓋住。
圖5係一本發明構件的一實施例的製造程序的第五階段的橫截面圖。將重組態的晶圓從載體板(10)撕離後，銅膜(14)的一些區域〔在這些區域中須做貫穿接點(28)接到晶片(18)及(20)的端子墊片形式的端子接點(22)〕露空，這點宜利用光刻版及蝕刻造成，並利用接到墊片的貫穿接點(28)造成導電連接。然後將導導的膜(14)構造化，以造成導線路的連或外部墊片，並使敏感區域(24)露空，以使媒能到達。此外，金屬面仍設以一適合的(例如可軟銲的)表面，並將其餘區域鈍化，例如用銲料阻擋漆(Lötstoplack)。各依用途而定，可將構造化的銅墊片設以銲料珠(30)(亦稱“ball”)，或當作LGA端子使用，最後將重組態過的晶圓沿圖5所示之虛線切分成個別元件。這點可利用鋸切、用雷射、水柱刀或類似習知技術達成。
依本發明此實施例的半導體構件係為一感測器模組，它具有一ASIC晶片形式的半導體晶片(18)及一感測器形式的半導體晶片(20)〔二者埋入模料構成的模封裝件(26)中並與構造化的導配的膜(14)互相連接成導電。此外，晶片(18)(20)經構造化的導電膜(14)與銲料珠(30)連接。
本發明特有利於用於終消費者電子產品用途的多功能感測器模組，例如用於行動無線電用途，個人數位幫手(PDA)，膝上型電膜等，其中需要有廉的封裝，同時構造尺 極端小型化。然而本發明當然不限於感測器晶片，而原則上可用於任何半導體晶片。
(1)‧‧‧載體板
(12)‧‧‧粘著層
(14)‧‧‧導電的膜(銅膜)
(16)‧‧‧粘著層
(18)‧‧‧半導體晶片
(20)‧‧‧半導體晶片(感測器)
(22)‧‧‧端子墊片(端子接點)
(24)‧‧‧敏感的區域
(26)‧‧‧(模料構成的模封裝件
(28)‧‧‧貫穿接點
(30)‧‧‧銲料珠
圖1係一本發明構件的一實施例的製造程序的第一階段的橫截面圖；圖2係一本發明構件的一實施例的製造程序的第二階段的橫截面圖；圖3係一本發明構件的一實施例的製造程序的第三階段的橫截面圖；圖4係一本發明構件的一實施例的製造程序的第四階段的橫截面圖；圖5係一本發明構件的一實施例的製造程序的第五階段的橫截面圖。
(14)‧‧‧銅膜
(16)‧‧‧粘著層
(18)‧‧‧半導體晶片
(20)‧‧‧半導體晶片(感測器)
(22)‧‧‧端子墊片(端子接點)
(24)‧‧‧敏感的區域
(26)‧‧‧模料(模封裝件)
(28)‧‧‧貫穿接點
(30)‧‧‧銲料珠

Claims (12)

  1. 一種製造半導體構件的方法，具有以下步驟：──將一導電的膜(14)固定在一載體(10)上；──使用一粘著層(16)將該半導體晶片(18)(20)粘到該導電的膜(14)上；其中：該半導體晶片(18)(20)之具端子接點(22)的活性表面位在該半導體晶片(18)(20)之朝向該膜(14)的那一面上；──將該粘在該導電的膜(14)上的該半導體晶片(18)(20)用一模料(26)灌膠；及──該將導電的膜(14)隨該灌過膠的半導體晶片(18)(20)從該載體(10)撕離，其特徵在：──將該粘著層(16)作構造化，使得至少該半導體晶片(18)(20)的該端子接點(22)不含該粘著層(16)且維持不具有該模料(26)。
  2. 如申請專利範圍第1項之方法，其中：該導電的膜(14)為一金屬膜。
  3. 如申請專利範圍第1或第2項之方法，其中：將該導電的膜(14)利用一粘著層(12)固定在該載體(10)上。
  4. 如申請專利範圍第1或第2項之方法，其中：將該導電的膜(14)設以該構造化的粘著層(16)。
  5. 如申請專利範圍第1或第2項之方法，其中：將一個具有該半導體晶片(18)(20)的晶圓在晶片切分前設以該構造化的粘著層(16)。
  6. 如申請專利範圍第1或第2項之方法，其中：該載體(10)撕離後，製造接觸件(28)以將該導電的膜(14)與該半導體晶片(18)(20)的該端子接點(22)連接。
  7. 如申請專利範圍第6項之方法，其中：該導電的膜(14)在製造該接觸件(22)後作構造化。
  8. 如申請專利範圍第7項之方法，其中：在該導電的膜(14)作構造化後將該半導體構件作切分。
  9. 一種半導體構件，具有：──至少一半導體晶片(18)(20)，該半導體晶片(18)(20)具有一個帶有端子接點(22)的活性表面；──一模料構成之模封裝件(26)，其中該至少一半導體晶片(18)(20)埋入該模料中的方式使得至少該端子接點(22)露空；及──一配線，以將該至少一半導體晶片(18)(20)的端子接點(22)作接觸；其特徵在：該配線包含一構造化之導電的膜(14)，且利用一構造化的粘著層(16)固定在該至少一個半導體晶片(18)(20)上，該粘著層(16)至少部分地蓋住該活性表面；其中該粘著層(16)構造化成使得至少該半導體晶片(18)(20)的端子接點(22)不含該粘著層(16)。
  10. 如申請專利範圍第9項之半導體構件，其中：該半導體晶片(20)係一感測器。
  11. 如申請專利範圍第9或第10項之半導體構件，其中：該構造化的粘著層(16)具有露空部以供該感測器形式 的半導體晶片(20)的敏感區域露空。
  12. 如申請專利範圍第9項之半導體構件，其中：在模封裝件(26)中至少設另一半導體晶片(18)，該另一半導體晶片(18)利用該構造化之導電的膜(14)與半導體晶片(20)呈導電連接。
TW100118796A 2010-06-01 2011-05-30 製造半導體構件的方法及相關的半導體構件 TWI575622B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102010029550.7A DE102010029550B4 (de) 2010-06-01 2010-06-01 Verfahren zur Herstellung von Halbleiter-Bauelementen

Publications (2)

Publication Number Publication Date
TW201201298A TW201201298A (en) 2012-01-01
TWI575622B true TWI575622B (zh) 2017-03-21

Family

ID=44924766

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100118796A TWI575622B (zh) 2010-06-01 2011-05-30 製造半導體構件的方法及相關的半導體構件

Country Status (5)

Country Link
US (1) US8759988B2 (zh)
CN (1) CN102270589B (zh)
DE (1) DE102010029550B4 (zh)
FR (1) FR2960701B1 (zh)
TW (1) TWI575622B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9230894B2 (en) 2012-05-02 2016-01-05 Infineon Technologies Ag Methods for manufacturing a chip package
US9385075B2 (en) 2012-10-26 2016-07-05 Infineon Technologies Ag Glass carrier with embedded semiconductor device and metal layers on the top surface
US10872832B2 (en) * 2015-12-16 2020-12-22 Intel Corporation Pre-molded active IC of passive components to miniaturize system in package
DE102018200140A1 (de) * 2018-01-08 2019-07-11 Robert Bosch Gmbh Umweltsensor, Umweltsensorzwischenprodukt und Verfahren zum Herstellen einer Vielzahl von Umweltsensoren
CN113436979B (zh) * 2021-06-15 2024-02-27 矽磐微电子(重庆)有限公司 半导体封装方法
CN113611616B (zh) * 2021-07-29 2023-12-26 矽磐微电子(重庆)有限公司 半导体封装方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090039496A1 (en) * 2007-08-10 2009-02-12 Infineon Technologies Ag Method for fabricating a semiconductor and semiconductor package
US20100127386A1 (en) * 2008-11-26 2010-05-27 Infineon Technologies Ag Device including a semiconductor chip

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020027294A1 (en) * 2000-07-21 2002-03-07 Neuhaus Herbert J. Electrical component assembly and method of fabrication
US7304362B2 (en) * 2002-05-20 2007-12-04 Stmicroelectronics, Inc. Molded integrated circuit package with exposed active area
DE102007020656B4 (de) * 2007-04-30 2009-05-07 Infineon Technologies Ag Werkstück mit Halbleiterchips, Halbleiterbauteil und Verfahren zur Herstellung eines Werkstücks mit Halbleiterchips
US8696917B2 (en) * 2009-02-09 2014-04-15 Edwards Lifesciences Corporation Analyte sensor and fabrication methods

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090039496A1 (en) * 2007-08-10 2009-02-12 Infineon Technologies Ag Method for fabricating a semiconductor and semiconductor package
US20100127386A1 (en) * 2008-11-26 2010-05-27 Infineon Technologies Ag Device including a semiconductor chip

Also Published As

Publication number Publication date
US8759988B2 (en) 2014-06-24
CN102270589A (zh) 2011-12-07
TW201201298A (en) 2012-01-01
CN102270589B (zh) 2016-11-02
FR2960701A1 (fr) 2011-12-02
DE102010029550B4 (de) 2019-08-22
US20110291301A1 (en) 2011-12-01
FR2960701B1 (fr) 2016-12-16
DE102010029550A1 (de) 2011-12-01

Similar Documents

Publication Publication Date Title
JP5161732B2 (ja) 半導体装置の製造方法
JP5095113B2 (ja) 固体撮像装置の製造方法、及び固体撮像装置
JP5095114B2 (ja) 固体撮像装置の製造方法
TWI575622B (zh) 製造半導體構件的方法及相關的半導體構件
JP4452235B2 (ja) パッケージ構造とその製造方法
JP2002076040A (ja) 半導体装置及びその製造方法
KR20030067562A (ko) 반도체 장치의 제조방법
US20060209514A1 (en) Semiconductor device and manufacturing method therefor
JP2003332542A (ja) 半導体装置およびその製造方法
CN110943710A (zh) 一种滤波器芯片封装结构及其晶圆级封装方法
TW201705426A (zh) 樹脂密封型半導體裝置及其製造方法
US7579680B2 (en) Packaging system for semiconductor devices
TW202226464A (zh) 具有堆疊被動組件的多層半導體封裝
KR20070080324A (ko) 접착력이 있는 폴리이미드층을 이용한 반도체 칩의 접착 및적층 방법
US20050266614A1 (en) Method of manufacturing semiconductor device and method of manufacturing electronic device
CN217590771U (zh) 芯片封装结构
KR100388287B1 (ko) 웨이퍼의 백그라인딩 방법과 이를 이용한 반도체패키지 및 그 제조방법
JP4978244B2 (ja) 半導体装置及びその製造方法
CN211321304U (zh) 一种滤波器芯片封装结构
KR100456815B1 (ko) 반도체 패키지 및 이것의 반도체 칩 부착방법
KR20030045224A (ko) 와이어 본딩 방식의 칩 스케일 패키지 및 그 제조방법
JP2004311603A (ja) 半導体装置の製造方法
JP4473668B2 (ja) 半導体装置およびその製造方法
CN115037269A (zh) 芯片封装方法及封装结构
KR100728956B1 (ko) 반도체 패키지의 제조방법

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees